mirror of
https://github.com/CTCaer/hekate
synced 2024-07-03 15:03:29 +00:00
185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
144 lines
5.5 KiB
C
144 lines
5.5 KiB
C
#include "../mem/mc.h"
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#include "../soc/t210.h"
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#include "../soc/clock.h"
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#include "../utils/util.h"
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void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock)
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{
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MC(MC_SEC_CARVEOUT_BOM) = bom;
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MC(MC_SEC_CARVEOUT_SIZE_MB) = size1mb;
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if (lock)
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MC(MC_SEC_CARVEOUT_REG_CTRL) = 1;
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}
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void mc_config_carveout()
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{
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*(vu32 *)0x8005FFFC = 0xC0EDBBCC;
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MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
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MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
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MC(MC_VIDEO_PROTECT_BOM) = 0;
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MC(MC_VIDEO_PROTECT_SIZE_MB) = 0;
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MC(MC_VIDEO_PROTECT_REG_CTRL) = 1;
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// Configure TSEC carveout @ 0x90000000, 1MB.
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//mc_config_tsec_carveout(0x90000000, 1, false);
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mc_config_tsec_carveout(0, 0, true);
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MC(MC_MTS_CARVEOUT_BOM) = 0;
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MC(MC_MTS_CARVEOUT_SIZE_MB) = 0;
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MC(MC_MTS_CARVEOUT_ADR_HI) = 0;
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MC(MC_MTS_CARVEOUT_REG_CTRL) = 1;
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MC(MC_SECURITY_CARVEOUT1_BOM) = 0;
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MC(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
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MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
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MC(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006;
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MC(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000;
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MC(MC_SECURITY_CARVEOUT2_BOM_HI) = 0;
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MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = 0x3100000;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = 0x300;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
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MC(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E;
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MC(MC_SECURITY_CARVEOUT3_BOM) = 0;
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MC(MC_SECURITY_CARVEOUT3_BOM_HI) = 0;
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MC(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0x3000000;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0x300;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
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MC(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
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MC(MC_SECURITY_CARVEOUT4_BOM) = 0;
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MC(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
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MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
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MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
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MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
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MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0;
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MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0;
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MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
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MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
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MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
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MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
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MC(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
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MC(MC_SECURITY_CARVEOUT5_BOM) = 0;
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MC(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
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MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
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MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
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MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
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MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0;
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MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
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MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
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MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
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MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
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MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
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MC(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
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}
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void mc_enable_ahb_redirect()
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{
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// Enable ARC_CLK_OVR_ON.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = (CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) & 0xFFF7FFFF) | 0x80000;
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//MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE;
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MC(MC_IRAM_BOM) = 0x40000000;
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MC(MC_IRAM_TOM) = 0x4003F000;
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}
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void mc_disable_ahb_redirect()
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{
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MC(MC_IRAM_BOM) = 0xFFFFF000;
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MC(MC_IRAM_TOM) = 0;
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// Disable IRAM_CFG_WRITE_ACCESS (sticky).
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//MC(MC_IRAM_REG_CTRL) = MC(MC_IRAM_REG_CTRL) & 0xFFFFFFFE | 1;
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// Disable ARC_CLK_OVR_ON.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= 0xFFF7FFFF;
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}
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void mc_enable()
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{
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | 0x40000000;
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// Enable EMC clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFDFFFFFF) | 0x2000000;
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// Enable MC clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE) | 1;
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// Enable EMC DLL clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF) | 0x4000;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x2000001; //Clear EMC and MC reset.
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usleep(5);
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//#ifdef CONFIG_ENABLE_AHB_REDIRECT
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mc_disable_ahb_redirect();
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//mc_enable_ahb_redirect();
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//#endif
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}
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