/*
* Defining registers address and its bit definitions of MAX77620 and MAX20024
*
* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/

#ifndef _MAX77620_H_
#define _MAX77620_H_

/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
#define MAX77620_REG_CNFGGLBL1			0x00
#define MAX77620_REG_CNFGGLBL2			0x01
#define MAX77620_REG_CNFGGLBL3			0x02
#define MAX77620_REG_CNFG1_32K			0x03
#define MAX77620_REG_CNFGBBC			0x04
#define MAX77620_REG_IRQTOP			0x05
#define MAX77620_REG_INTLBT			0x06
#define MAX77620_REG_IRQSD			0x07
#define MAX77620_REG_IRQ_LVL2_L0_7		0x08
#define MAX77620_REG_IRQ_LVL2_L8		0x09
#define MAX77620_REG_IRQ_LVL2_GPIO		0x0A
#define MAX77620_REG_ONOFFIRQ			0x0B
#define MAX77620_REG_NVERC			0x0C
#define MAX77620_REG_IRQTOPM			0x0D
#define MAX77620_REG_INTENLBT			0x0E
#define MAX77620_REG_IRQMASKSD			0x0F
#define MAX77620_REG_IRQ_MSK_L0_7		0x10
#define MAX77620_REG_IRQ_MSK_L8			0x11
#define MAX77620_REG_ONOFFIRQM			0x12
#define MAX77620_REG_STATLBT			0x13
#define MAX77620_REG_STATSD			0x14
#define MAX77620_REG_ONOFFSTAT			0x15

/* SD and LDO Registers */
#define MAX77620_REG_SD0			0x16
#define MAX77620_REG_SD1			0x17
#define MAX77620_REG_SD2			0x18
#define MAX77620_REG_SD3			0x19
#define MAX77620_REG_SD4			0x1A
#define MAX77620_REG_DVSSD0			0x1B
#define MAX77620_REG_DVSSD1			0x1C
#define MAX77620_REG_SD0_CFG			0x1D
#define MAX77620_REG_SD1_CFG			0x1E
#define MAX77620_REG_SD2_CFG			0x1F
#define MAX77620_REG_SD3_CFG			0x20
#define MAX77620_REG_SD4_CFG			0x21
#define MAX77620_REG_SD_CFG2			0x22
#define MAX77620_REG_LDO0_CFG			0x23
#define MAX77620_REG_LDO0_CFG2			0x24
#define MAX77620_REG_LDO1_CFG			0x25
#define MAX77620_REG_LDO1_CFG2			0x26
#define MAX77620_REG_LDO2_CFG			0x27
#define MAX77620_REG_LDO2_CFG2			0x28
#define MAX77620_REG_LDO3_CFG			0x29
#define MAX77620_REG_LDO3_CFG2			0x2A
#define MAX77620_REG_LDO4_CFG			0x2B
#define MAX77620_REG_LDO4_CFG2			0x2C
#define MAX77620_REG_LDO5_CFG			0x2D
#define MAX77620_REG_LDO5_CFG2			0x2E
#define MAX77620_REG_LDO6_CFG			0x2F
#define MAX77620_REG_LDO6_CFG2			0x30
#define MAX77620_REG_LDO7_CFG			0x31
#define MAX77620_REG_LDO7_CFG2			0x32
#define MAX77620_REG_LDO8_CFG			0x33
#define MAX77620_REG_LDO8_CFG2			0x34
#define MAX77620_REG_LDO_CFG3			0x35

#define MAX77620_LDO_SLEW_RATE_MASK		0x1

/* LDO Configuration 3 */
#define MAX77620_TRACK4_MASK			BIT(5)
#define MAX77620_TRACK4_SHIFT			5

/* Voltage */
#define MAX77620_SDX_VOLT_MASK			0xFF
#define MAX77620_SD0_VOLT_MASK			0x3F
#define MAX77620_SD1_VOLT_MASK			0x7F
#define MAX77620_LDO_VOLT_MASK			0x3F

#define MAX77620_REG_GPIO0			0x36
#define MAX77620_REG_GPIO1			0x37
#define MAX77620_REG_GPIO2			0x38
#define MAX77620_REG_GPIO3			0x39
#define MAX77620_REG_GPIO4			0x3A
#define MAX77620_REG_GPIO5			0x3B
#define MAX77620_REG_GPIO6			0x3C
#define MAX77620_REG_GPIO7			0x3D
#define MAX77620_REG_PUE_GPIO			0x3E
#define MAX77620_REG_PDE_GPIO			0x3F
#define MAX77620_REG_AME_GPIO			0x40
#define MAX77620_REG_ONOFFCNFG1			0x41
#define MAX77620_REG_ONOFFCNFG2			0x42

/* FPS Registers */
#define MAX77620_REG_FPS_CFG0			0x43
#define MAX77620_REG_FPS_CFG1			0x44
#define MAX77620_REG_FPS_CFG2			0x45
#define MAX77620_REG_FPS_LDO0			0x46
#define MAX77620_REG_FPS_LDO1			0x47
#define MAX77620_REG_FPS_LDO2			0x48
#define MAX77620_REG_FPS_LDO3			0x49
#define MAX77620_REG_FPS_LDO4			0x4A
#define MAX77620_REG_FPS_LDO5			0x4B
#define MAX77620_REG_FPS_LDO6			0x4C
#define MAX77620_REG_FPS_LDO7			0x4D
#define MAX77620_REG_FPS_LDO8			0x4E
#define MAX77620_REG_FPS_SD0			0x4F
#define MAX77620_REG_FPS_SD1			0x50
#define MAX77620_REG_FPS_SD2			0x51
#define MAX77620_REG_FPS_SD3			0x52
#define MAX77620_REG_FPS_SD4			0x53

#define MAX77620_REG_FPS_GPIO1			0x54
#define MAX77620_REG_FPS_GPIO2			0x55
#define MAX77620_REG_FPS_GPIO3			0x56
#define MAX77620_REG_FPS_RSO			0x57
#define MAX77620_REG_CID0			0x58
#define MAX77620_REG_CID1			0x59
#define MAX77620_REG_CID2			0x5A
#define MAX77620_REG_CID3			0x5B
#define MAX77620_REG_CID4			0x5C
#define MAX77620_REG_CID5			0x5D

#define MAX77620_REG_DVSSD4			0x5E
#define MAX20024_REG_MAX_ADD			0x70

#endif