Bump hekate to v6.1.0 and Nyx to v1.6.0

nyx: add error code info on lite gamepad dumping
bdk: sdram: adjust sdmmc1 la for l4t
2025-01-06 20:27:56 +00:00 · 2024-02-22 11:45:19 +02:00 · 2024-02-22 11:44:43 +02:00 · 2024-02-21 10:50:15 +02:00 · 2024-02-21 10:42:28 +02:00 · 2024-02-21 10:40:46 +02:00
40 changed files with 941 additions and 4069 deletions
--- a/Versions.inc
+++ b/Versions.inc
@ -1,11 +1,11 @@
 # IPL Version.
 BLVERSION_MAJOR := 6
-BLVERSION_MINOR := 0
-BLVERSION_HOTFX := 7
+BLVERSION_MINOR := 1
+BLVERSION_HOTFX := 0
 BLVERSION_RSVD := 0

 # Nyx Version.
 NYXVERSION_MAJOR := 1
-NYXVERSION_MINOR := 5
-NYXVERSION_HOTFX := 6
+NYXVERSION_MINOR := 6
+NYXVERSION_HOTFX := 0
 NYXVERSION_RSVD := 0
--- a/bdk/display/di.c
+++ b/bdk/display/di.c
@ -42,6 +42,26 @@ static bool _nx_aula = false;

 static void _display_panel_and_hw_end(bool no_panel_deinit);

+void display_enable_interrupt(u32 intr)
+{
+	DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) |= intr;
+}
+
+void display_disable_interrupt(u32 intr)
+{
+	DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) &= ~intr;
+	DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = intr;
+}
+
+void display_wait_interrupt(u32 intr)
+{
+	DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = intr;
+
+	// Interrupts are masked. Poll status register for checking if fired.
+	while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & intr))
+			;
+}
+
 static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
 {
 	u32 end = get_tmr_us() + timeout;
@ -64,22 +84,18 @@ static void _display_dsi_wait_vblank(bool enable)
 	if (enable)
 	{
 		// Enable vblank interrupt.
-		DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = DC_CMD_INT_FRAME_END_INT;
+		display_enable_interrupt(DC_CMD_INT_FRAME_END_INT);

 		// Use the 4th line to transmit the host cmd packet.
 		DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE | DSI_DSI_LINE_TYPE(4);

 		// Wait for vblank before starting the transfer.
-		DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
-		while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
-			;
+		display_wait_interrupt(DC_CMD_INT_FRAME_END_INT);
 	}
 	else
 	{
 		// Wait for vblank before resetting sync points.
-		DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
-		while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
-			;
+		display_wait_interrupt(DC_CMD_INT_FRAME_END_INT);
 		usleep(14);

 		// Reset all states of syncpt block.
@ -94,8 +110,7 @@ static void _display_dsi_wait_vblank(bool enable)
 		DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;

 		// Disable and clear vblank interrupt.
-		DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = 0;
-		DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT;
+		display_disable_interrupt(DC_CMD_INT_FRAME_END_INT);
 	}
 }

--- a/bdk/display/di.h
+++ b/bdk/display/di.h
@ -732,9 +732,10 @@
 * [10] 96 [09]: JDI LAM062M109A
 * [20] 93 [0F]: InnoLux P062CCA-AZ1 (Rev A1)
 * [20] 95 [0F]: InnoLux P062CCA-AZ2 (Rev B1)
- * [20] 96 [0F]: InnoLux P062CCA-AZ3 (Rev XX) [UNCONFIRMED MODEL+REV]
+ * [20] 96 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV]
 * [20] 97 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV]
 * [20] 98 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV]
+ * [20] 99 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV]
 * [30] 93 [0F]: AUO A062TAN00 (59.06A33.000)
 * [30] 94 [0F]: AUO A062TAN01 (59.06A33.001)
 * [30] 95 [0F]: AUO A062TAN02 (59.06A33.002)
@ -786,13 +787,23 @@ enum
 	PANEL_INL_2J055IA_27A = 0x1020,
 	PANEL_AUO_A055TAN01   = 0x1030,
 	PANEL_SHP_LQ055T1SW10 = 0x1040,
-	PANEL_SAM_AMS699VC01  = 0x2050
+	PANEL_SAM_AMS699VC01  = 0x2050,
+
+	// Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings.
+	PANEL_OEM_CLONE_5_5   = 0xB3,
+	// Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings.
+	PANEL_OEM_CLONE       = 0
 };

 void display_init();
 void display_backlight_pwm_init();
 void display_end();

+/*! Interrupt management. */
+void display_enable_interrupt(u32 intr);
+void display_disable_interrupt(u32 intr);
+void display_wait_interrupt(u32 intr);
+
 /*! Get/Set Display panel ID. */
 u16  display_get_decoded_panel_id();
 void display_set_decoded_panel_id(u32 id);
--- a/bdk/input/touch.c
+++ b/bdk/input/touch.c
@ -39,7 +39,7 @@ static touch_panel_info_t _panels[] =
 	{  1,  0, 1, 1,  "GiS GGM6 B2X"    },// 1.
 	{  2,  0, 0, 0,  "NISSHA NBF-K9A"  },// 3.
 	{  3,  1, 0, 0,  "GiS 5.5\""       },// 4.
-	{  4,  0, 0, 1,  "Samsung BH2109"  },// 5?
+	{  4,  0, 0, 1,  "Samsung TSP"     },// 5?
 	{ -1,  1, 0, 1,  "GiS VA 6.2\""    } // 2.
 };

--- a/bdk/mem/emc.h
+++ b/bdk/mem/emc.h
@ -712,7 +712,7 @@ enum
 	EMC_CHAN1 = 1
 };

-typedef struct _emc_mr_data_t
+typedef struct _emc_mr_chip_data_t
 {
 	// Device 0.
 	u8 rank0_ch0;
@ -721,6 +721,12 @@ typedef struct _emc_mr_data_t
 	// Device 1.
 	u8 rank1_ch0;
 	u8 rank1_ch1;
+} emc_mr_chip_data_t;
+
+typedef struct _emc_mr_data_t
+{
+	emc_mr_chip_data_t chip0;
+	emc_mr_chip_data_t chip1;
 } emc_mr_data_t;

 #endif
--- a/bdk/mem/mc.c
+++ b/bdk/mem/mc.c
@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2022 CTCaer
+ * Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -21,7 +21,7 @@
 #include <soc/t210.h>
 #include <soc/clock.h>

-void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock)
+void mc_config_tzdram_carveout(u32 bom, u32 size1mb, bool lock)
 {
 	MC(MC_SEC_CARVEOUT_BOM) = bom;
 	MC(MC_SEC_CARVEOUT_SIZE_MB) = size1mb;
@ -31,96 +31,47 @@ void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock)

 void mc_config_carveout()
 {
+	// Enable ACR GSR3.
 	*(vu32 *)0x8005FFFC = 0xC0EDBBCC;
 	MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
 	MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
 	MC(MC_VIDEO_PROTECT_BOM) = 0;
-	MC(MC_VIDEO_PROTECT_SIZE_MB) = 0;
-	MC(MC_VIDEO_PROTECT_REG_CTRL) = 1;
+	MC(MC_VIDEO_PROTECT_REG_CTRL) = VPR_CTRL_LOCKED;

-	// Configure TSEC carveout @ 0x90000000, 1MB.
-	//mc_config_tsec_carveout(0x90000000, 1, false);
-	mc_config_tsec_carveout(0, 0, true);
+	// Configure TZDRAM carveout @ 0x90000000, 1MB.
+	//mc_config_tzdram_carveout(0x90000000, 1, false);
+	mc_config_tzdram_carveout(0, 0, true);

 	MC(MC_MTS_CARVEOUT_BOM) = 0;
-	MC(MC_MTS_CARVEOUT_SIZE_MB) = 0;
-	MC(MC_MTS_CARVEOUT_ADR_HI) = 0;
 	MC(MC_MTS_CARVEOUT_REG_CTRL) = 1;

-	MC(MC_SECURITY_CARVEOUT1_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
 	MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0;
 	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0;
 	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006;
+	MC(MC_SECURITY_CARVEOUT1_CFG0) = SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_APERTURE_ID(0)    |
+									 SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH;

 	MC(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000;
-	MC(MC_SECURITY_CARVEOUT2_BOM_HI) = 0;
-	MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = 0x3100000;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = 0x300;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E;
+	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_GPU  | SEC_CARVEOUT_CA2_W_GPU | SEC_CARVEOUT_CA2_R_TSEC;

-	MC(MC_SECURITY_CARVEOUT3_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT3_BOM_HI) = 0;
-	MC(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0x3000000;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0x300;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
-
-	MC(MC_SECURITY_CARVEOUT4_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
 	MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
 	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
 	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
+	MC(MC_SECURITY_CARVEOUT4_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE         |
+									 SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_RD_NS             |
+									 SEC_CARVEOUT_CFG_WR_NS;

-	MC(MC_SECURITY_CARVEOUT5_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
 	MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
 	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
+	MC(MC_SECURITY_CARVEOUT5_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE         |
+									 SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_RD_NS             |
+									 SEC_CARVEOUT_CFG_WR_NS;
 }

 void mc_enable_ahb_redirect()
@ -157,12 +108,10 @@ bool mc_client_has_access(void *address)
 void mc_enable()
 {
 	// Reset EMC source to PLLP.
-	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | (2 << 29);
-	// Enable memory clocks.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC);
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MEM);
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | (2 << 29u);
+	// Enable and clear reset for memory clocks.
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
 	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_EMC_DLL);
-	// Clear clock resets for memory.
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
 	usleep(5);

--- a/bdk/mem/minerva.c
+++ b/bdk/mem/minerva.c
@ -27,10 +27,10 @@
 #include <soc/t210.h>
 #include <utils/util.h>

-#define LA_REGS_OFFSET_T210    0x1284
-#define LA_REGS_OFFSET_T210B01 0xFA4
+#define TABLE_FREQ_KHZ_OFFSET        0x40
+#define TABLE_LA_REGS_T210_OFFSET    0x1284
+#define TABLE_LA_REGS_T210B01_OFFSET 0xFA4
 #define LA_SDMMC1_INDEX 6
-#define LA_SDMMC4_INDEX 9

 extern volatile nyx_storage_t *nyx_str;

@ -148,10 +148,22 @@ void minerva_change_freq(minerva_freq_t freq)
 void minerva_sdmmc_la_program(void *table, bool t210b01)
 {

-	u32 *la_scale_regs = (u32 *)(table + (t210b01 ? LA_REGS_OFFSET_T210B01 : LA_REGS_OFFSET_T210));
+	u32 freq = *(u32 *)(table + TABLE_FREQ_KHZ_OFFSET);
+	u32 *la_scale_regs = (u32 *)(table + (t210b01 ? TABLE_LA_REGS_T210B01_OFFSET : TABLE_LA_REGS_T210_OFFSET));

-	// Promote SDMMC1 latency allowance to SDMMC4 (SD to eMMC).
-	la_scale_regs[LA_SDMMC1_INDEX] = la_scale_regs[LA_SDMMC4_INDEX];
+	// Adjust SDMMC1 latency allowance.
+	switch (freq)
+	{
+	case 204000:
+		la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 75;
+		break;
+	case 408000:
+		la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 37;
+		break;
+	default:
+		la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 30;
+		break;
+	}
 }

 void minerva_prep_boot_freq()
@ -171,7 +183,7 @@ void minerva_prep_boot_freq()
 	minerva_change_freq(FREQ_800);
 }

-void minerva_prep_boot_l4t(u32 oc_freq)
+void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom)
 {
 	if (!minerva_cfg)
 		return;
@ -188,7 +200,9 @@ void minerva_prep_boot_l4t(u32 oc_freq)
 		memcpy(&mtc_cfg->mtc_table[mtc_cfg->table_entries],
 			   &mtc_cfg->mtc_table[mtc_cfg->table_entries - 1],
 			   sizeof(emc_table_t));
-		mtc_cfg->mtc_table[mtc_cfg->table_entries].rate_khz = oc_freq;
+
+		mtc_cfg->mtc_table[mtc_cfg->table_entries].opt_custom = opt_custom;
+		mtc_cfg->mtc_table[mtc_cfg->table_entries].rate_khz   = oc_freq;
 		mtc_cfg->table_entries++;
 	}

--- a/bdk/mem/minerva.h
+++ b/bdk/mem/minerva.h
@ -63,7 +63,7 @@ u32  minerva_init();
 void minerva_change_freq(minerva_freq_t freq);
 void minerva_sdmmc_la_program(void *table, bool t210b01);
 void minerva_prep_boot_freq();
-void minerva_prep_boot_l4t(u32 oc_freq);
+void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom);
 void minerva_periodic_training();
 emc_table_t *minerva_get_mtc_table();
 int minerva_get_mtc_table_entries();
--- a/bdk/mem/mtc_table.h
+++ b/bdk/mem/mtc_table.h
@ -481,7 +481,8 @@ typedef struct
 	u32 rate_khz;
 	u32 min_volt;
 	u32 gpu_min_volt;
-	char clock_src[32];
+	char clock_src[28];
+	u32 opt_custom;
 	u32 clk_src_emc;
 	u32 needs_training;
 	u32 training_pattern;
--- a/bdk/mem/sdram.c
+++ b/bdk/mem/sdram.c
@ -42,8 +42,8 @@
 typedef struct _sdram_vendor_patch_t
 {
 	u32 val;
-	u32 offset:16;
 	u32 dramcf:16;
+	u32 offset:16;
 } sdram_vendor_patch_t;

 static const u8 dram_encoding_t210b01[] = {
@ -76,9 +76,9 @@ static const u8 dram_encoding_t210b01[] = {
 /* 26 */	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF,
 /* 27 */	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF,
 /* 28 */	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL,
-/* 29 */	LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEI,
-/* 30 */	LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEI,
-/* 31 */	LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEI,
+/* 29 */	LPDDR4X_4GB_HYNIX_H54G46CYRBX267,
+/* 30 */	LPDDR4X_4GB_HYNIX_H54G46CYRBX267,
+/* 31 */	LPDDR4X_4GB_HYNIX_H54G46CYRBX267,
 /* 32 */	LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB,
 /* 33 */	LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB,
 /* 34 */	LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB,
@ -127,15 +127,19 @@ static void _sdram_req_mrr_data(u32 data, bool dual_channel)
 emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)
 {
 	emc_mr_data_t data;
-	u32 dual_channel = (EMC(EMC_FBIO_CFG7) >> 2) & 1;
+	u32 mrr;
+	bool dual_rank    = EMC(EMC_ADR_CFG) & 1;
+	bool dual_channel = (EMC(EMC_FBIO_CFG7) >> 2) & 1; // Each EMC channel is a RAM chip module.

 	// Clear left overs.
-	for (u32 i = 0; i < 32; i++)
+	for (u32 i = 0; i < 16; i++)
 	{
 		(void)EMC(EMC_MRR);
 		usleep(1);
 	}

+	memset(&data, 0xFF, sizeof(emc_mr_data_t));
+
 	/*
 	 * When a dram chip has only one rank, then the info from the 2 ranks differs.
 	 * Info not matching is only allowed on different channels.
@ -143,21 +147,38 @@ emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)

 	// Get Device 0 (Rank 0) info from both dram chips (channels).
 	_sdram_req_mrr_data((2u << 30) | (mrx << 16), dual_channel);
-	data.rank0_ch0 = EMC(EMC_MRR) & 0xFF;
-	data.rank0_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
+
+	// Ram module 0 info.
+	mrr = EMC_CH0(EMC_MRR);
+	data.chip0.rank0_ch0 = mrr & 0xFF;
+	data.chip0.rank0_ch1 = (mrr & 0xFF00 >> 8);
+
+	// Ram module 1 info.
+	if (dual_channel)
+	{
+		mrr = EMC_CH1(EMC_MRR);
+		data.chip1.rank0_ch0 = mrr & 0xFF;
+		data.chip1.rank0_ch1 = (mrr & 0xFF00 >> 8);
+	}

 	// If Rank 1 exists, get info.
-	if (EMC(EMC_ADR_CFG) & 1)
+	if (dual_rank)
 	{
 		// Get Device 1 (Rank 1) info from both dram chips (channels).
 		_sdram_req_mrr_data((1u << 30) | (mrx << 16), dual_channel);
-		data.rank1_ch0 = EMC(EMC_MRR) & 0xFF;
-		data.rank1_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
-	}
-	else
-	{
-		data.rank1_ch0 = 0xFF;
-		data.rank1_ch1 = 0xFF;
+
+		// Ram module 0 info.
+		mrr = EMC_CH0(EMC_MRR);
+		data.chip0.rank1_ch0 = mrr & 0xFF;
+		data.chip0.rank1_ch1 = (mrr & 0xFF00 >> 8);
+
+		// Ram module 1 info.
+		if (dual_channel)
+		{
+			mrr = EMC_CH1(EMC_MRR);
+			data.chip1.rank1_ch0 = mrr & 0xFF;
+			data.chip1.rank1_ch1 = (mrr & 0xFF00 >> 8);
+		}
 	}

 	return data;
@ -167,12 +188,12 @@ static void _sdram_config_t210(const sdram_params_t210_t *params)
 {
 	// Program DPD3/DPD4 regs (coldboot path).
 	// Enable sel_dpd on unused pins.
-	u32 dpd_req = (params->emc_pmc_scratch1 & 0x3FFFFFFF) | 0x80000000;
+	u32 dpd_req = (params->emc_pmc_scratch1 & 0x3FFFFFFF) | (2 << 30u);
 	PMC(APBDEV_PMC_IO_DPD3_REQ) = (dpd_req ^ 0xFFFF) & 0xC000FFFF;
 	usleep(params->pmc_io_dpd3_req_wait);

 	// Disable e_dpd_vttgen.
-	dpd_req = (params->emc_pmc_scratch2 & 0x3FFFFFFF) | 0x80000000;
+	dpd_req = (params->emc_pmc_scratch2 & 0x3FFFFFFF) | (2 << 30u);
 	PMC(APBDEV_PMC_IO_DPD4_REQ) = (dpd_req & 0xFFFF0000) ^ 0x3FFF0000;
 	usleep(params->pmc_io_dpd4_req_wait);

@ -209,7 +230,7 @@ break_nosleep:
 	if (params->emc_clock_source_dll)
 		CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = params->emc_clock_source_dll;
 	if (params->clear_clock2_mc1)
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = 0x40000000; // Clear Reset to MC1.
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = BIT(CLK_W_MC1); // Clear Reset to MC1.

 	// Enable and clear reset for memory clocks.
 	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
@ -233,7 +254,7 @@ break_nosleep:

 	// Program CMD mapping. Required before brick mapping, else
 	// we can't guarantee CK will be differential at all times.
-	EMC(EMC_FBIO_CFG7) = params->emc_fbio_cfg7;
+	EMC(EMC_FBIO_CFG7)          = params->emc_fbio_cfg7;
 	EMC(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0;
 	EMC(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1;
 	EMC(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2;
@ -246,7 +267,7 @@ break_nosleep:
 	EMC(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0;
 	EMC(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1;
 	EMC(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2;
-	EMC(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte;
+	EMC(EMC_CMD_MAPPING_BYTE)   = params->emc_cmd_mapping_byte;

 	// Program brick mapping.
 	EMC(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0;
@ -289,13 +310,13 @@ break_nosleep:
 	EMC(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7;
 	EMC(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8;

-	EMC(EMC_PMACRO_RX_TERM)    = params->emc_pmacro_rx_term;
-	EMC(EMC_PMACRO_DQ_TX_DRV)  = params->emc_pmacro_dq_tx_drive;
-	EMC(EMC_PMACRO_CA_TX_DRV)  = params->emc_pmacro_ca_tx_drive;
-	EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive;
+	EMC(EMC_PMACRO_RX_TERM)            = params->emc_pmacro_rx_term;
+	EMC(EMC_PMACRO_DQ_TX_DRV)          = params->emc_pmacro_dq_tx_drive;
+	EMC(EMC_PMACRO_CA_TX_DRV)          = params->emc_pmacro_ca_tx_drive;
+	EMC(EMC_PMACRO_CMD_TX_DRV)         = params->emc_pmacro_cmd_tx_drive;
 	EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common;
-	EMC(EMC_AUTO_CAL_CHANNEL)  = params->emc_auto_cal_channel;
-	EMC(EMC_PMACRO_ZCTRL)      = params->emc_pmacro_zcrtl;
+	EMC(EMC_AUTO_CAL_CHANNEL)          = params->emc_auto_cal_channel;
+	EMC(EMC_PMACRO_ZCTRL)              = params->emc_pmacro_zcrtl;

 	EMC(EMC_DLL_CFG_0)     = params->emc_dll_cfg0;
 	EMC(EMC_DLL_CFG_1)     = params->emc_dll_cfg1;
@ -328,7 +349,7 @@ break_nosleep:
 	EMC(EMC_PMACRO_CMD_RX_TERM_MODE)     = params->emc_pmacro_cmd_rx_term_mode;
 	EMC(EMC_PMACRO_CMD_PAD_TX_CTRL)      = params->emc_pmacro_cmd_pad_tx_ctrl;

-	EMC(EMC_CFG_3) = params->emc_cfg3;
+	EMC(EMC_CFG_3)                   = params->emc_cfg3;
 	EMC(EMC_PMACRO_TX_PWRD_0)        = params->emc_pmacro_tx_pwrd0;
 	EMC(EMC_PMACRO_TX_PWRD_1)        = params->emc_pmacro_tx_pwrd1;
 	EMC(EMC_PMACRO_TX_PWRD_2)        = params->emc_pmacro_tx_pwrd2;
@ -561,9 +582,11 @@ break_nosleep:

 	EMC(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->emc_pmacro_common_pad_tx_ctrl;
 	EMC(EMC_DBG)                 = params->emc_dbg;
+
 	EMC(EMC_QRST)                = params->emc_qrst;
 	EMC(EMC_ISSUE_QRST)          = 1;
 	EMC(EMC_ISSUE_QRST)          = 0;
+
 	EMC(EMC_QSAFE)               = params->emc_qsafe;
 	EMC(EMC_RDV)                 = params->emc_rdv;
 	EMC(EMC_RDV_MASK)            = params->emc_rdv_mask;
@ -616,7 +639,7 @@ break_nosleep:
 	}

 	// Release SEL_DPD_CMD.
-	PMC(APBDEV_PMC_IO_DPD3_REQ) = ((params->emc_pmc_scratch1 & 0x3FFFFFFF) | 0x40000000) & 0xCFFF0000;
+	PMC(APBDEV_PMC_IO_DPD3_REQ) = (params->emc_pmc_scratch1 & 0xFFF0000) | (1 << 30u);
 	usleep(params->pmc_io_dpd3_req_wait);

 	// Set autocal interval if not configured.
@ -707,7 +730,7 @@ break_nosleep:
 		EMC(EMC_REF) = (((1 << params->emc_extra_refresh_num) - 1) << 8) | (params->emc_dev_select << 30) | 3;

 	// Enable refresh.
-	EMC(EMC_REFCTRL) = params->emc_dev_select | 0x80000000;
+	EMC(EMC_REFCTRL) = params->emc_dev_select | BIT(31);

 	EMC(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control;
 	EMC(EMC_CFG_UPDATE)    = params->emc_cfg_update;
@ -717,7 +740,7 @@ break_nosleep:
 	EMC(EMC_SEL_DPD_CTRL)  = params->emc_sel_dpd_ctrl;

 	// Write addr swizzle lock bit.
-	EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | 2;
+	EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | BIT(1);

 	EMC(EMC_TIMING_CONTROL) = 1; // Re-trigger timing to latch power saving functions.

@ -751,15 +774,15 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
 	// Program DPD3/DPD4 regs (coldboot path).
 	// Enable sel_dpd on unused pins.
 	PMC(APBDEV_PMC_WEAK_BIAS)   = (pmc_scratch1 & 0x1000) << 19 | (pmc_scratch1 & 0xFFF) << 18 | (pmc_scratch1 & 0x8000) << 15;
-	PMC(APBDEV_PMC_IO_DPD3_REQ) = (pmc_scratch1 & 0x9FFF) + 0x80000000;
+	PMC(APBDEV_PMC_IO_DPD3_REQ) = (pmc_scratch1 & 0x9FFF) | (2 << 30u);
 	usleep(params->pmc_io_dpd3_req_wait);

 	// Disable e_dpd_vttgen.
-	PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x3FFF0000) | 0x80000000;
+	PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x3FFF0000) | (2 << 30u);
 	usleep(params->pmc_io_dpd4_req_wait);

 	// Disable e_dpd_bg.
-	PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x1FFF) | 0x80000000;
+	PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x1FFF) | (2 << 30u);
 	usleep(1);

 	// Program CMD mapping. Required before brick mapping, else
@ -1155,9 +1178,11 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
 	EMC(EMC_PUTERM_WIDTH)    = params->emc_puterm_width;

 	EMC(EMC_DBG)                 = params->emc_dbg;
+
 	EMC(EMC_QRST)                = params->emc_qrst;
 	EMC(EMC_ISSUE_QRST)          = 1;
 	EMC(EMC_ISSUE_QRST)          = 0;
+
 	EMC(EMC_QSAFE)               = params->emc_qsafe;
 	EMC(EMC_RDV)                 = params->emc_rdv;
 	EMC(EMC_RDV_MASK)            = params->emc_rdv_mask;
@ -1219,7 +1244,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
 		*(vu32 *)params->emc_bct_spare_secure16 = params->emc_bct_spare_secure17;

 	// Release SEL_DPD_CMD.
-	PMC(APBDEV_PMC_IO_DPD3_REQ) = ((params->emc_pmc_scratch1 & 0x3FFFFFFF) | 0x40000000) & 0xCFFF0000;
+	PMC(APBDEV_PMC_IO_DPD3_REQ) = (params->emc_pmc_scratch1 & 0xFFF0000) | (1 << 30u);
 	usleep(params->pmc_io_dpd3_req_wait);

 	// Set transmission pad control parameters.
@ -1315,7 +1340,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
 		EMC(EMC_REF) = ((1 << params->emc_extra_refresh_num << 8) - 253) | (params->emc_dev_select << 30);

 	// Enable refresh.
-	EMC(EMC_REFCTRL) = params->emc_dev_select | 0x80000000;
+	EMC(EMC_REFCTRL) = params->emc_dev_select | BIT(31);

 	EMC(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control;
 	EMC(EMC_CFG)           = params->emc_cfg;
@ -1324,7 +1349,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
 	EMC(EMC_SEL_DPD_CTRL)  = params->emc_sel_dpd_ctrl;

 	// Write addr swizzle lock bit.
-	EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | 2;
+	EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | BIT(1);

 	EMC(EMC_TIMING_CONTROL) = 1; // Re-trigger timing to latch power saving functions.

--- a/bdk/mem/sdram.h
+++ b/bdk/mem/sdram.h
@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2020-2023 CTCaer
+ * Copyright (c) 2020-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -42,58 +42,67 @@
 enum sdram_ids_erista
 {
 	// LPDDR4 3200Mbps.
-	LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH        = 0,
-	LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE       = 1,
-	LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT  = 2, // WT:C.
+	LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH        = 0, // Die-B. (2y-01).
+	LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE       = 1, // Die-M. (2y-01).
+	LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WTC = 2, // Die-C. (2y-01).

-	LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH        = 4,
+	LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH        = 4, // Die-C. (2y-01).

-	LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX        = 7, // Custom 8GB. XX: CH/CJ/CL. 7 since it can be easily applied in fuses.
+	// Custom hekate/L4T supported 8GB. 7 dram id can be easily applied in fuses.
+	LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX        = 7, // XX: CH/CJ/CL.
 };

 enum sdram_ids_mariko
 {
+	/*
+	 * Nintendo Switch LPDRR4X generations:
+	 * - 1x   nm are 1st-gen
+	 * - 1y   nm are 2nd-gen
+	 * - 1z/a nm are 3rd-gen
+	 */
+
 	// LPDDR4X 4266Mbps.
-	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 3, // Replaced from Copper. Die-M. (1y-01).
-	LPDDR4X_AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 5, // Replaced from Copper. Die-M. (1y-01).
-	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 6, // Replaced from Copper. Die-M. (1y-01).
+	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 3, // Die-M. (1y-01).
+	LPDDR4X_AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 5, // Die-M. (1y-01).
+	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 6, // Die-M. (1y-01).

 	// LPDDR4X 3733Mbps.
-	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 8,  // Die-M. 1st gen. 3733Mbps.
-	LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 9,  // Die-M.
-	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 10, // Die-M.
-	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE = 11, // 4266Mbps. Die-E. D9WGB.
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 8,  // Die-M. (1x-03).
+	LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 9,  // Die-M. (1x-03).
+	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 10, // Die-M. (1x-03).
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE = 11, // Die-E. (1x-03). D9WGB. 4266Mbps.

-	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 12, // Die-M. 1st gen. 3733Mbps.
-	LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 13, // Die-M.
-	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 14, // Die-M.
-	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE = 15, // 4266Mbps. Die-E. D9WGB.
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 12, // Die-M. (1x-03).
+	LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 13, // Die-M. (1x-03).
+	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 14, // Die-M. (1x-03).
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE = 15, // Die-E. (1x-03). D9WGB. 4266Mbps.

 	// LPDDR4X 4266Mbps.
-	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 17, // Die-A. (1y-X03). 2nd gen. 4266Mbps.
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 17, // Die-A. (1y-X03).
 	LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 18, // Die-A. (1y-X03).
-	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 19, // Die-A. (1y-X03). 2nd gen. 4266Mbps.
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 19, // Die-A. (1y-X03).

-	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 20, // Die-B. 1z nm. 40% lower power usage. (1z-01).
-	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 21, // Die-B. 1z nm. 40% lower power usage. (1z-01).
-	LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 22, // Die-B. 1z nm. 40% lower power usage. (1z-01).
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 20, // Die-B. (1z-01). 40% lp.
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 21, // Die-B. (1z-01). 40% lp.
+	LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 22, // Die-B. (1z-01). 40% lp.

 	LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 23, // Die-A. (1y-X03).
-	LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 24, // Die-A. (1y-X03). 2nd gen. 4266Mbps.
+	LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 24, // Die-A. (1y-X03).

-	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 25, // 4266Mbps. Die-F. D9XRR. 10nm-class (1y-01).
-	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTF = 26, // 4266Mbps. Die-F. D9XRR. 10nm-class (1y-01).
-	LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 27, // 4266Mbps. Die-F. D9XRR. 10nm-class (1y-01).
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 25, // Die-F. (1y-01). D9XRR.
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTF = 26, // Die-F. (1y-01). D9XRR.
+	LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 27, // Die-F. (1y-01). D9XRR.

-	LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 28, // Die-A.
+	LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 28, // Die-A. (1y-X03). 2nd gen.

-	LPDDR4X_UNK0_4GB_HYNIX_H9HCNNNBKMMLXR_NEI       = 29, // Die-M. 1a nm. 61% lower power usage. (1a-01).
-	LPDDR4X_UNK1_4GB_HYNIX_H9HCNNNBKMMLXR_NEI       = 30, // Die-M. 1a nm. 61% lower power usage. (1a-01).
-	LPDDR4X_UNK2_4GB_HYNIX_H9HCNNNBKMMLXR_NEI       = 31, // Die-M. 1a nm. 61% lower power usage. (1a-01).
+	// Old naming scheme: H9HCNNNBKMCLXR-NEE
+	LPDDR4X_IOWA_4GB_HYNIX_H54G46CYRBX267           = 29, // Die-C. (1a-01). 61% lp.
+	LPDDR4X_HOAG_4GB_HYNIX_H54G46CYRBX267           = 30, // Die-C. (1a-01). 61% lp.
+	LPDDR4X_AULA_4GB_HYNIX_H54G46CYRBX267           = 31, // Die-C. (1a-01). 61% lp.

-	LPDDR4X_UNK0_4GB_MICRON_MT53E512M32D1NP_046_WTB = 32, // 1a nm. 61% lower power usage. (1a-01).
-	LPDDR4X_UNK1_4GB_MICRON_MT53E512M32D1NP_046_WTB = 33, // 1a nm. 61% lower power usage. (1a-01).
-	LPDDR4X_UNK2_4GB_MICRON_MT53E512M32D1NP_046_WTB = 34, // 1a nm. 61% lower power usage. (1a-01).
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D1NP_046_WTB = 32, // Die-B. (1a-01). D8BQM. 61% lp.
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D1NP_046_WTB = 33, // Die-B. (1a-01). D8BQM. 61% lp.
+	LPDDR4X_AULA_4GB_MICRON_MT53E512M32D1NP_046_WTB = 34, // Die-B. (1a-01). D8BQM. 61% lp.
 };

 enum sdram_codes_mariko
@ -111,7 +120,7 @@ enum sdram_codes_mariko
 	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 5, // DRAM IDs: 20, 21, 22.
 	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF = 6, // DRAM IDs: 25, 26, 27.
 	LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 7, // DRAM IDs: 03, 05, 06.
-	LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEI       = 8, // DRAM IDs: 29, 30, 31.
+	LPDDR4X_4GB_HYNIX_H54G46CYRBX267           = 8, // DRAM IDs: 29, 30, 31.
 	LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB = 9, // DRAM IDs: 32, 33, 34.
 };

--- a/bdk/mem/sdram_config.inl
+++ b/bdk/mem/sdram_config.inl
@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2020-2022 CTCaer
+ * Copyright (c) 2020-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -434,9 +434,9 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
 	.emc_dll_cfg0                                    = 0x1F13412F,
 	.emc_dll_cfg1                                    = 0x00010014,

-	.emc_pmc_scratch1                                = 0x4FAFFFFF,
+	.emc_pmc_scratch1                                = 0x4FAFFFFF, // APBDEV_PMC_IO_DPD3_REQ.
 	.emc_pmc_scratch2                                = 0x7FFFFFFF,
-	.emc_pmc_scratch3                                = 0x4006D70B,
+	.emc_pmc_scratch3                                = 0x4006D70B, // APBDEV_PMC_DDR_CNTRL.

 	.emc_pmacro_pad_cfg_ctrl                         = 0x00020000,
 	.emc_pmacro_vttgen_ctrl0                         = 0x00030808,
@ -499,7 +499,7 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
 	 * Specifies the value for MC_EMEM_CFG which holds the external memory
 	 * size (in KBytes)
 	 */
-	.mc_emem_cfg                                     = 0x00001000, // 4GB total density.
+	.mc_emem_cfg                                     = 0x00001000, // 4GB total density. Max 8GB.

 	/* MC arbitration configuration */
 	.mc_emem_arb_cfg                                 = 0x08000001,
@ -542,16 +542,18 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
 	.mc_video_protect_bom_adr_hi                     = 0x00000000,
 	.mc_video_protect_size_mb                        = 0x00000000,

-	// AFI, BPMP, HC, ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1, SDMMC1A, SDMMC2A, SDMMC3A.
-	.mc_video_protect_vpr_override                   = 0xE4BAC343,
-	// SDMMC4A, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR.
-	.mc_video_protect_vpr_override1                  = 0x00001ED3,
+	// AFI, BPMP, HC, ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1, SDMMC1A, SDMMC2A, SDMMC3A. Plus TSEC, NVENC.
+	.mc_video_protect_vpr_override                   = 0xE4FACB43, // Default: 0xE4BAC343. New: 0xE4FACB43. + TSEC,  NVENC.
+	// SDMMC4A, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR. Plus TSECB, TSEC1, TSECB1.
+	.mc_video_protect_vpr_override1                  = 0x0000FED3, // Default: 0x00001ED3. New: 0x0000FED3. + TSECB, TSEC1, TSECB1.
+
+	.mc_video_protect_gpu_override0                  = 0x2A800000, // Default: 0x00000000. Forced to 1 by HOS Secmon.
+	.mc_video_protect_gpu_override1                  = 0x00000002, // Default: 0x00000000. Forced to 0 by HOS Secmon.

-	.mc_video_protect_gpu_override0                  = 0x00000000,
-	.mc_video_protect_gpu_override1                  = 0x00000000,
 	.mc_sec_carveout_bom                             = 0xFFF00000,
 	.mc_sec_carveout_adr_hi                          = 0x00000000,
 	.mc_sec_carveout_size_mb                         = 0x00000000,
+
 	.mc_video_protect_write_access                   = 0x00000000,
 	.mc_sec_carveout_protect_write_access            = 0x00000000,

@ -646,26 +648,27 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
 	.mc_mts_carveout_reg_ctrl                        = 0x00000000
 };

+#define DCFG_OFFSET_OF(m) (OFFSET_OF(sdram_params_t210_t, m) / 4)
 static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210[] = {
 	// Hynix timing config.
-	{ 0x0000000D, 0x10C / 4, DRAM_ID(1) }, // emc_r2w.
-	{ 0x00000001, 0x16C / 4, DRAM_ID(1) }, // emc_puterm_extra.
-	{ 0x80000000, 0x170 / 4, DRAM_ID(1) }, // emc_puterm_width.
-	{ 0x00000210, 0x4F4 / 4, DRAM_ID(1) }, // emc_pmacro_data_rx_term_mode.
-	{ 0x00000005, 0x5C0 / 4, DRAM_ID(1) }, // mc_emem_arb_timing_r2w.
+	{ 0x0000000D, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_r2w)                      },
+	{ 0x00000001, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_puterm_extra)             },
+	{ 0x80000000, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_puterm_width)             },
+	{ 0x00000210, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_pmacro_data_rx_term_mode) },
+	{ 0x00000005, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(mc_emem_arb_timing_r2w)       },

 	// Samsung 6GB density config.
-	{ 0x000C0302, 0x56C / 4, DRAM_ID(4) }, // mc_emem_adr_cfg_dev0. 768MB Chip 0 density.
-	{ 0x000C0302, 0x570 / 4, DRAM_ID(4) }, // mc_emem_adr_cfg_dev1. 768MB Chip 1 density.
-	{ 0x00001800, 0x584 / 4, DRAM_ID(4) }, // mc_emem_cfg. 6GB total density.
+	{ 0x000C0302, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev0)         }, // 768MB Chip 0 density.
+	{ 0x000C0302, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev1)         }, // 768MB Chip 1 density.
+	{ 0x00001800, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH),  DCFG_OFFSET_OF(mc_emem_cfg)                  }, // 6GB total density. Max 8GB.

 	// Samsung 8GB density config.
-	{ 0x0000003A,  0xEC / 4, DRAM_ID(7) }, // emc_rfc.
-	{ 0x0000001D,  0xF0 / 4, DRAM_ID(7) }, // emc_rfc_pb.
-	{ 0x0000003B, 0x1C0 / 4, DRAM_ID(7) }, // emc_txsr.
-	{ 0x0000003B, 0x1C4 / 4, DRAM_ID(7) }, // emc_txsr_dll.
-	{ 0x00000713, 0x2B4 / 4, DRAM_ID(7) }, // emc_dyn_self_ref_control.
-	{ 0x00080302, 0x56C / 4, DRAM_ID(7) }, // mc_emem_adr_cfg_dev0. 1024MB Chip 0 density.
-	{ 0x00080302, 0x570 / 4, DRAM_ID(7) }, // mc_emem_adr_cfg_dev1. 1024MB Chip 1 density.
-	{ 0x00002000, 0x584 / 4, DRAM_ID(7) }, // mc_emem_cfg. 8GB total density.
+	{ 0x0000003A, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_rfc)                      },
+	{ 0x0000001D, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_rfc_pb)                   },
+	{ 0x0000003B, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_txsr)                     },
+	{ 0x0000003B, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_txsr_dll)                 },
+	{ 0x00080302, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev0)         }, // 1024MB Chip 0 density.
+	{ 0x00080302, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev1)         }, // 1024MB Chip 1 density.
+	{ 0x00002000, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_cfg)                  }, // 8GB total density. Max 8GB.
 };
+#undef DCFG_OFFSET_OF
--- a/bdk/mem/sdram_config_t210b01.inl
+++ b/bdk/mem/sdram_config_t210b01.inl
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2023 CTCaer
+ * Copyright (c) 2020-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -552,7 +552,7 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
 	 * Specifies the value for MC_EMEM_CFG which holds the external memory
 	 * size (in KBytes)
 	 */
-	.mc_emem_cfg                                     = 0x00001000, // 4GB total density.
+	.mc_emem_cfg                                     = 0x00001000, // 4GB total density. Max 8GB.

 	/* MC arbitration configuration */
 	.mc_emem_arb_cfg                                 = 0x08000001,
@ -595,17 +595,18 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
 	.mc_video_protect_bom_adr_hi                     = 0x00000000,
 	.mc_video_protect_size_mb                        = 0x00000000,

-	// AFI, BPMP, HC, ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1, SDMMC1A, SDMMC2A, SDMMC3A.
-	.mc_video_protect_vpr_override                   = 0xE4BAC343,
-	// SDMMC4A, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR. Plus SE2, SE2B.
-	.mc_video_protect_vpr_override1                  = 0x06001ED3,
+	// AFI, BPMP, HC, ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1, SDMMC1A, SDMMC2A, SDMMC3A. Plus TSEC, NVENC.
+	.mc_video_protect_vpr_override                   = 0xE4FACB43, // Default: 0xE4BAC343.
+	// SDMMC4A, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR. Plus SE2, SE2B and TSECB, TSEC1, TSECB1.
+	.mc_video_protect_vpr_override1                  = 0x0600FED3, // Default: 0x06001ED3.

-	.mc_video_protect_gpu_override0                  = 0x00000000,
-	.mc_video_protect_gpu_override1                  = 0x00000000,
+	.mc_video_protect_gpu_override0                  = 0x2A800000, // Default: 0x00000000. Forced to 1 by HOS Secmon.
+	.mc_video_protect_gpu_override1                  = 0x00000002, // Default: 0x00000000. Forced to 0 by HOS Secmon.

 	.mc_sec_carveout_bom                             = 0xFFF00000,
 	.mc_sec_carveout_adr_hi                          = 0x00000000,
 	.mc_sec_carveout_size_mb                         = 0x00000000,
+
 	.mc_video_protect_write_access                   = 0x00000000,
 	.mc_sec_carveout_protect_write_access            = 0x00000000,

@ -708,30 +709,30 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {

 #define DRAM_CC_LPDDR4X_PMACRO_IB      (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ))

-#define DRAM_CC_LPDDR4X_AUTOCAL_VPR    (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
+#define DRAM_CC_LPDDR4X_PUPD_VPR       (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \
 										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
 										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
-										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEI)       | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
 										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))

-#define DRAM_CC_LPDDR4X_DYN_SELF_CTRL  (DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \
+#define DRAM_CC_LPDDR4X_DSR            (DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \
 										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
 										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
-										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEI)       | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
 										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))

-#define DRAM_CC_LPDDR4X_QUSE_EINPUT    (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
+#define DRAM_CC_LPDDR4X_QUSE           (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
 										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
 										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
-										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEI)       | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
 										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))

@ -741,67 +742,71 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB))

 #define DRAM_CC_LPDDR4X_VPR            (DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
-										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEI)       | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
 										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))

 #define DRAM_CC_LPDDR4X_8GB            (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
 										DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL))

+#define DCFG_OFFSET_OF(m) (OFFSET_OF(sdram_params_t210b01_t, m) / 4)
 static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {

 	// Samsung LPDDR4X 8GB K4UBE3D4AM-MGCJ Die-M for SDEV Iowa and Hoag.
-	{ 0x35353535, 0x350 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_vref_dq_0.
-	{ 0x35353535, 0x354 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_vref_dq_1.
-	{ 0x00100010, 0x3FC / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank0_0.
-	{ 0x00100010, 0x400 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank0_1.
-	{ 0x00100010, 0x404 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank0_2.
-	{ 0x00100010, 0x408 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank0_3.
-	{ 0x00100010, 0x40C / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank1_0.
-	{ 0x00100010, 0x410 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank1_1.
-	{ 0x00100010, 0x414 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank1_2.
-	{ 0x00100010, 0x418 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank1_3.
+	{ 0x35353535, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_vref_dq_0)             },
+	{ 0x35353535, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_vref_dq_1)             },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_0) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_1) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_2) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_3) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_0) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_1) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_2) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_3) },

 	/*! Shared patched between DRAM Codes. */
-	{ 0x05500000, 0x0D4 / 4, DRAM_CC_LPDDR4X_AUTOCAL_VPR }, // emc_auto_cal_config2.
-	{ 0xC9AFBCBC, 0x0F4 / 4, DRAM_CC_LPDDR4X_AUTOCAL_VPR }, // emc_auto_cal_vref_sel0.
-	{ 0x2A800000, 0x6DC / 4, DRAM_CC_LPDDR4X_AUTOCAL_VPR }, // mc_video_protect_gpu_override0.
-	{ 0x00000002, 0x6E0 / 4, DRAM_CC_LPDDR4X_AUTOCAL_VPR }, // mc_video_protect_gpu_override1.
-	//!TODO Find out what mc_video_protect_gpu_override0 and mc_video_protect_gpu_override1 new bits are.
+	{ 0x05500000, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(emc_auto_cal_config2)                },
+	{ 0xC9AFBCBC, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(emc_auto_cal_vref_sel0)              },

-	{ 0x88161414, 0x2E0 / 4, DRAM_CC_LPDDR4X_DYN_SELF_CTRL }, // emc_mrw14.
-	{ 0x80000713, 0x32C / 4, DRAM_CC_LPDDR4X_DYN_SELF_CTRL }, // emc_dyn_self_ref_control.
+	// Moved to default config.
+	// { 0x2A800000, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(mc_video_protect_gpu_override0)      },
+	// { 0x00000002, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(mc_video_protect_gpu_override1)      },

-	{ 0x00000006, 0x1CC / 4, DRAM_CC_LPDDR4X_QUSE_EINPUT }, // emc_quse.
-	{ 0x00000005, 0x1D0 / 4, DRAM_CC_LPDDR4X_QUSE_EINPUT }, // emc_quse_width.
-	{ 0x00000003, 0x1DC / 4, DRAM_CC_LPDDR4X_QUSE_EINPUT }, // emc_einput.
-	{ 0x0000000C, 0x1E0 / 4, DRAM_CC_LPDDR4X_QUSE_EINPUT }, // emc_einput_duration.
+	{ 0x88161414, DRAM_CC_LPDDR4X_DSR,       DCFG_OFFSET_OF(emc_mrw14)                           },
+	{ 0x80000713, DRAM_CC_LPDDR4X_DSR,       DCFG_OFFSET_OF(emc_dyn_self_ref_control)            },

-	{ 0x00000008, 0x24C / 4, DRAM_CC_LPDDR4X_FAW }, // emc_tfaw.
-	{ 0x00000001, 0x670 / 4, DRAM_CC_LPDDR4X_FAW }, // mc_emem_arb_timing_faw.
+	{ 0x00000006, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_quse)                            },
+	{ 0x00000005, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_quse_width)                      },
+	{ 0x00000003, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_einput)                          },
+	{ 0x0000000C, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_einput_duration)                 },

-	{ 0xE4FACB43, 0x6D4 / 4, DRAM_CC_LPDDR4X_VPR }, // mc_video_protect_vpr_override. + TSEC, NVENC.
-	{ 0x0600FED3, 0x6D8 / 4, DRAM_CC_LPDDR4X_VPR }, // mc_video_protect_vpr_override1. + TSECB, TSEC1, TSECB1.
+	{ 0x00000008, DRAM_CC_LPDDR4X_FAW,       DCFG_OFFSET_OF(emc_tfaw)                            },
+	{ 0x00000001, DRAM_CC_LPDDR4X_FAW,       DCFG_OFFSET_OF(mc_emem_arb_timing_faw)              },

-	{ 0x00000001, 0x134 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_adr_cfg. 2 Ranks.
-	{ 0x08010004, 0x2B8 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw1.
-	{ 0x08020000, 0x2BC / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw2.
-	{ 0x080D0000, 0x2C0 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw3.
-	{ 0x08033131, 0x2C8 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw6.
-	{ 0x080B0000, 0x2CC / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw8.
-	{ 0x0C0E5D5D, 0x2D0 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw9.
-	{ 0x080C5D5D, 0x2D4 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw10.
-	{ 0x0C0D0808, 0x2D8 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw12.
-	{ 0x0C0D0000, 0x2DC / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw13.
-	{ 0x08161414, 0x2E0 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw14.
-	{ 0x08010004, 0x2E4 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_mrw_extra.
-	{ 0x00000000, 0x340 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_dev_select. Both devices.
-	{ 0x0051004F, 0x450 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_zcal_mrw_cmd.
-	{ 0x40000001, 0x45C / 4, DRAM_CC_LPDDR4X_8GB }, // emc_zcal_init_dev1.
-	{ 0x00000000, 0x594 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_pmacro_tx_pwrd4.
-	{ 0x00001000, 0x598 / 4, DRAM_CC_LPDDR4X_8GB }, // emc_pmacro_tx_pwrd5.
-	{ 0x00000001, 0x630 / 4, DRAM_CC_LPDDR4X_8GB }, // mc_emem_adr_cfg. 2 Ranks.
-	{ 0x00002000, 0x64C / 4, DRAM_CC_LPDDR4X_8GB }, // mc_emem_cfg. 8GB total density.
-	{ 0x00000002, 0x680 / 4, DRAM_CC_LPDDR4X_8GB }, // mc_emem_arb_timing_r2r.
-	{ 0x02020001, 0x694 / 4, DRAM_CC_LPDDR4X_8GB }, // mc_emem_arb_da_turns.
+	// Moved to default config.
+	// { 0xE4FACB43, DRAM_CC_LPDDR4X_VPR,       DCFG_OFFSET_OF(mc_video_protect_vpr_override)       }, // + TSEC,  NVENC.
+	// { 0x0600FED3, DRAM_CC_LPDDR4X_VPR,       DCFG_OFFSET_OF(mc_video_protect_vpr_override1)      }, // + TSECB, TSEC1, TSECB1.
+
+	{ 0x00000001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_adr_cfg)                         }, // 2 Ranks.
+	{ 0x08010004, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw1)                            },
+	{ 0x08020000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw2)                            },
+	{ 0x080D0000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw3)                            },
+	{ 0x08033131, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw6)                            },
+	{ 0x080B0000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw8)                            },
+	{ 0x0C0E5D5D, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw9)                            },
+	{ 0x080C5D5D, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw10)                           },
+	{ 0x0C0D0808, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw12)                           },
+	{ 0x0C0D0000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw13)                           },
+	{ 0x08161414, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw14)                           },
+	{ 0x08010004, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw_extra)                       },
+	{ 0x00000000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_dev_select)                      }, // Both devices.
+	{ 0x0051004F, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_zcal_mrw_cmd)                    },
+	{ 0x40000001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_zcal_init_dev1)                  },
+	{ 0x00000000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_pmacro_tx_pwrd4)                 },
+	{ 0x00001000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_pmacro_tx_pwrd5)                 },
+	{ 0x00000001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_adr_cfg)                     }, // 2 Ranks.
+	{ 0x00002000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_cfg)                         }, // 8GB total density. Max 8GB.
+	{ 0x00000002, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_arb_timing_r2r)              },
+	{ 0x02020001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_arb_da_turns)                },
 };
+#undef DCFG_OFFSET_OF
--- a/bdk/mem/sdram_lp0.c
+++ b/bdk/mem/sdram_lp0.c
--- a/bdk/mem/sdram_lp0_param_t210.h
+++ b/bdk/mem/sdram_lp0_param_t210.h
@ -1,964 +0,0 @@
-/*
- * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
- * Copyright 2014 Google Inc.
- * Copyright (c) 2018 CTCaer
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-
-/**
- * Defines the SDRAM parameter structure.
- *
- * Note that PLLM is used by EMC. The field names are in camel case to ease
- * directly converting BCT config files (*.cfg) into C structure.
- */
-
-#ifndef __TEGRA210_SDRAM_PARAM_H__
-#define __TEGRA210_SDRAM_PARAM_H__
-
-#include <utils/types.h>
-
-enum
-{
-	/* Specifies the memory type to be undefined */
-	NvBootMemoryType_None = 0,
-
-	/* Specifies the memory type to be DDR SDRAM */
-	NvBootMemoryType_Ddr = 0,
-
-	/* Specifies the memory type to be LPDDR SDRAM */
-	NvBootMemoryType_LpDdr = 0,
-
-	/* Specifies the memory type to be DDR2 SDRAM */
-	NvBootMemoryType_Ddr2 = 0,
-
-	/* Specifies the memory type to be LPDDR2 SDRAM */
-	NvBootMemoryType_LpDdr2,
-
-	/* Specifies the memory type to be DDR3 SDRAM */
-	NvBootMemoryType_Ddr3,
-
-	/* Specifies the memory type to be LPDDR4 SDRAM */
-	NvBootMemoryType_LpDdr4,
-
-	NvBootMemoryType_Num,
-
-	/* Specifies an entry in the ram_code table that's not in use */
-	NvBootMemoryType_Unused = 0X7FFFFFF,
-};
-
-/**
- * Defines the SDRAM parameter structure
- */
-struct sdram_params_t210
-{
-
-	/* Specifies the type of memory device */
-	u32 MemoryType;
-
-	/* MC/EMC clock source configuration */
-
-	/* Specifies the M value for PllM */
-	u32 PllMInputDivider;
-	/* Specifies the N value for PllM */
-	u32 PllMFeedbackDivider;
-	/* Specifies the time to wait for PLLM to lock (in microseconds) */
-	u32 PllMStableTime;
-	/* Specifies misc. control bits */
-	u32 PllMSetupControl;
-	/* Specifies the P value for PLLM */
-	u32 PllMPostDivider;
-	/* Specifies value for Charge Pump Gain Control */
-	u32 PllMKCP;
-	/* Specifies VCO gain */
-	u32 PllMKVCO;
-	/* Spare BCT param */
-	u32 EmcBctSpare0;
-	/* Spare BCT param */
-	u32 EmcBctSpare1;
-	/* Spare BCT param */
-	u32 EmcBctSpare2;
-	/* Spare BCT param */
-	u32 EmcBctSpare3;
-	/* Spare BCT param */
-	u32 EmcBctSpare4;
-	/* Spare BCT param */
-	u32 EmcBctSpare5;
-	/* Spare BCT param */
-	u32 EmcBctSpare6;
-	/* Spare BCT param */
-	u32 EmcBctSpare7;
-	/* Spare BCT param */
-	u32 EmcBctSpare8;
-	/* Spare BCT param */
-	u32 EmcBctSpare9;
-	/* Spare BCT param */
-	u32 EmcBctSpare10;
-	/* Spare BCT param */
-	u32 EmcBctSpare11;
-	/* Spare BCT param */
-	u32 EmcBctSpare12;
-	/* Spare BCT param */
-	u32 EmcBctSpare13;
-
-	/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
-	u32 EmcClockSource;
-	u32 EmcClockSourceDll;
-
-	/* Defines possible override for PLLLM_MISC2 */
-	u32 ClkRstControllerPllmMisc2Override;
-	/* enables override for PLLLM_MISC2 */
-	u32 ClkRstControllerPllmMisc2OverrideEnable;
-	/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
-	u32 ClearClk2Mc1;
-
-	/* Auto-calibration of EMC pads */
-
-	/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
-	u32 EmcAutoCalInterval;
-	/*
-	 * Specifies the value for EMC_AUTO_CAL_CONFIG
-	 * Note: Trigger bits are set by the SDRAM code.
-	 */
-	u32 EmcAutoCalConfig;
-
-	/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
-	u32 EmcAutoCalConfig2;
-
-	/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
-	u32 EmcAutoCalConfig3;
-
-	/* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */
-	u32 EmcAutoCalConfig4;
-	u32 EmcAutoCalConfig5;
-	u32 EmcAutoCalConfig6;
-	u32 EmcAutoCalConfig7;
-	u32 EmcAutoCalConfig8;
-
-	/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
-	u32 EmcAutoCalVrefSel0;
-	u32 EmcAutoCalVrefSel1;
-
-	/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
-	u32 EmcAutoCalChannel;
-
-	/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
-	u32 EmcPmacroAutocalCfg0;
-	u32 EmcPmacroAutocalCfg1;
-	u32 EmcPmacroAutocalCfg2;
-	u32 EmcPmacroRxTerm;
-	u32 EmcPmacroDqTxDrv;
-	u32 EmcPmacroCaTxDrv;
-	u32 EmcPmacroCmdTxDrv;
-	u32 EmcPmacroAutocalCfgCommon;
-	u32 EmcPmacroZctrl;
-
-	/*
-	 * Specifies the time for the calibration
-	 * to stabilize (in microseconds)
-	 */
-	u32 EmcAutoCalWait;
-
-	u32 EmcXm2CompPadCtrl;
-	u32 EmcXm2CompPadCtrl2;
-	u32 EmcXm2CompPadCtrl3;
-
-	/*
-	 * DRAM size information
-	 * Specifies the value for EMC_ADR_CFG
-	 */
-	u32 EmcAdrCfg;
-
-	/*
-	 * Specifies the time to wait after asserting pin
-	 * CKE (in microseconds)
-	 */
-	u32 EmcPinProgramWait;
-	/* Specifies the extra delay before/after pin RESET/CKE command */
-	u32 EmcPinExtraWait;
-
-	u32 EmcPinGpioEn;
-	u32 EmcPinGpio;
-
-	/*
-	 * Specifies the extra delay after the first writing
-	 * of EMC_TIMING_CONTROL
-	 */
-	u32 EmcTimingControlWait;
-
-	/* Timing parameters required for the SDRAM */
-
-	/* Specifies the value for EMC_RC */
-	u32 EmcRc;
-	/* Specifies the value for EMC_RFC */
-	u32 EmcRfc;
-	/* Specifies the value for EMC_RFC_PB */
-	u32 EmcRfcPb;
-	/* Specifies the value for EMC_RFC_CTRL2 */
-	u32 EmcRefctrl2;
-	/* Specifies the value for EMC_RFC_SLR */
-	u32 EmcRfcSlr;
-	/* Specifies the value for EMC_RAS */
-	u32 EmcRas;
-	/* Specifies the value for EMC_RP */
-	u32 EmcRp;
-	/* Specifies the value for EMC_R2R */
-	u32 EmcR2r;
-	/* Specifies the value for EMC_W2W */
-	u32 EmcW2w;
-	/* Specifies the value for EMC_R2W */
-	u32 EmcR2w;
-	/* Specifies the value for EMC_W2R */
-	u32 EmcW2r;
-	/* Specifies the value for EMC_R2P */
-	u32 EmcR2p;
-	/* Specifies the value for EMC_W2P */
-	u32 EmcW2p;
-
-	u32 EmcTppd;
-	u32 EmcCcdmw;
-
-	/* Specifies the value for EMC_RD_RCD */
-	u32 EmcRdRcd;
-	/* Specifies the value for EMC_WR_RCD */
-	u32 EmcWrRcd;
-	/* Specifies the value for EMC_RRD */
-	u32 EmcRrd;
-	/* Specifies the value for EMC_REXT */
-	u32 EmcRext;
-	/* Specifies the value for EMC_WEXT */
-	u32 EmcWext;
-	/* Specifies the value for EMC_WDV */
-	u32 EmcWdv;
-
-	u32 EmcWdvChk;
-	u32 EmcWsv;
-	u32 EmcWev;
-
-	/* Specifies the value for EMC_WDV_MASK */
-	u32 EmcWdvMask;
-
-	u32 EmcWsDuration;
-	u32 EmcWeDuration;
-
-	/* Specifies the value for EMC_QUSE */
-	u32 EmcQUse;
-	/* Specifies the value for EMC_QUSE_WIDTH */
-	u32 EmcQuseWidth;
-	/* Specifies the value for EMC_IBDLY */
-	u32 EmcIbdly;
-	/* Specifies the value for EMC_OBDLY */
-	u32 EmcObdly;
-	/* Specifies the value for EMC_EINPUT */
-	u32 EmcEInput;
-	/* Specifies the value for EMC_EINPUT_DURATION */
-	u32 EmcEInputDuration;
-	/* Specifies the value for EMC_PUTERM_EXTRA */
-	u32 EmcPutermExtra;
-	/* Specifies the value for EMC_PUTERM_WIDTH */
-	u32 EmcPutermWidth;
-	/* Specifies the value for EMC_PUTERM_ADJ */
-	////u32 EmcPutermAdj;
-
-	/* Specifies the value for EMC_QRST */
-	u32 EmcQRst;
-	/* Specifies the value for EMC_QSAFE */
-	u32 EmcQSafe;
-	/* Specifies the value for EMC_RDV */
-	u32 EmcRdv;
-	/* Specifies the value for EMC_RDV_MASK */
-	u32 EmcRdvMask;
-	/* Specifies the value for EMC_RDV_EARLY */
-	u32 EmcRdvEarly;
-	/* Specifies the value for EMC_RDV_EARLY_MASK */
-	u32 EmcRdvEarlyMask;
-	/* Specifies the value for EMC_QPOP */
-	u32 EmcQpop;
-
-	/* Specifies the value for EMC_REFRESH */
-	u32 EmcRefresh;
-	/* Specifies the value for EMC_BURST_REFRESH_NUM */
-	u32 EmcBurstRefreshNum;
-	/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
-	u32 EmcPreRefreshReqCnt;
-	/* Specifies the value for EMC_PDEX2WR */
-	u32 EmcPdEx2Wr;
-	/* Specifies the value for EMC_PDEX2RD */
-	u32 EmcPdEx2Rd;
-	/* Specifies the value for EMC_PCHG2PDEN */
-	u32 EmcPChg2Pden;
-	/* Specifies the value for EMC_ACT2PDEN */
-	u32 EmcAct2Pden;
-	/* Specifies the value for EMC_AR2PDEN */
-	u32 EmcAr2Pden;
-	/* Specifies the value for EMC_RW2PDEN */
-	u32 EmcRw2Pden;
-	/* Specifies the value for EMC_CKE2PDEN */
-	u32 EmcCke2Pden;
-	/* Specifies the value for EMC_PDEX2CKE */
-	u32 EmcPdex2Cke;
-	/* Specifies the value for EMC_PDEX2MRR */
-	u32 EmcPdex2Mrr;
-	/* Specifies the value for EMC_TXSR */
-	u32 EmcTxsr;
-	/* Specifies the value for EMC_TXSRDLL */
-	u32 EmcTxsrDll;
-	/* Specifies the value for EMC_TCKE */
-	u32 EmcTcke;
-	/* Specifies the value for EMC_TCKESR */
-	u32 EmcTckesr;
-	/* Specifies the value for EMC_TPD */
-	u32 EmcTpd;
-	/* Specifies the value for EMC_TFAW */
-	u32 EmcTfaw;
-	/* Specifies the value for EMC_TRPAB */
-	u32 EmcTrpab;
-	/* Specifies the value for EMC_TCLKSTABLE */
-	u32 EmcTClkStable;
-	/* Specifies the value for EMC_TCLKSTOP */
-	u32 EmcTClkStop;
-	/* Specifies the value for EMC_TREFBW */
-	u32 EmcTRefBw;
-
-	/* FBIO configuration values */
-
-	/* Specifies the value for EMC_FBIO_CFG5 */
-	u32 EmcFbioCfg5;
-	/* Specifies the value for EMC_FBIO_CFG7 */
-	u32 EmcFbioCfg7;
-	/* Specifies the value for EMC_FBIO_CFG8 */
-	u32 EmcFbioCfg8;
-
-	/* Command mapping for CMD brick 0 */
-	u32 EmcCmdMappingCmd0_0;
-	u32 EmcCmdMappingCmd0_1;
-	u32 EmcCmdMappingCmd0_2;
-	u32 EmcCmdMappingCmd1_0;
-	u32 EmcCmdMappingCmd1_1;
-	u32 EmcCmdMappingCmd1_2;
-	u32 EmcCmdMappingCmd2_0;
-	u32 EmcCmdMappingCmd2_1;
-	u32 EmcCmdMappingCmd2_2;
-	u32 EmcCmdMappingCmd3_0;
-	u32 EmcCmdMappingCmd3_1;
-	u32 EmcCmdMappingCmd3_2;
-	u32 EmcCmdMappingByte;
-
-	/* Specifies the value for EMC_FBIO_SPARE */
-	u32 EmcFbioSpare;
-
-	/* Specifies the value for EMC_CFG_RSV */
-	u32 EmcCfgRsv;
-
-	/* MRS command values */
-
-	/* Specifies the value for EMC_MRS */
-	u32 EmcMrs;
-	/* Specifies the MP0 command to initialize mode registers */
-	u32 EmcEmrs;
-	/* Specifies the MP2 command to initialize mode registers */
-	u32 EmcEmrs2;
-	/* Specifies the MP3 command to initialize mode registers */
-	u32 EmcEmrs3;
-	/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
-	u32 EmcMrw1;
-	/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
-	u32 EmcMrw2;
-	/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
-	u32 EmcMrw3;
-	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
-	u32 EmcMrw4;
-	/* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */
-	u32 EmcMrw6;
-	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
-	u32 EmcMrw8;
-	/* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */
-	u32 EmcMrw9;
-	/* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */
-	u32 EmcMrw10;
-	/* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */
-	u32 EmcMrw12;
-	/* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */
-	u32 EmcMrw13;
-	/* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */
-	u32 EmcMrw14;
-	/*
-	 * Specifies the programming to extra LPDDR2 Mode Register
-	 * at cold boot
-	 */
-	u32 EmcMrwExtra;
-	/*
-	 * Specifies the programming to extra LPDDR2 Mode Register
-	 * at warm boot
-	 */
-	u32 EmcWarmBootMrwExtra;
-	/*
-	 * Specify the enable of extra Mode Register programming at
-	 * warm boot
-	 */
-	u32 EmcWarmBootExtraModeRegWriteEnable;
-	/*
-	 * Specify the enable of extra Mode Register programming at
-	 * cold boot
-	 */
-	u32 EmcExtraModeRegWriteEnable;
-
-	/* Specifies the EMC_MRW reset command value */
-	u32 EmcMrwResetCommand;
-	/* Specifies the EMC Reset wait time (in microseconds) */
-	u32 EmcMrwResetNInitWait;
-	/* Specifies the value for EMC_MRS_WAIT_CNT */
-	u32 EmcMrsWaitCnt;
-	/* Specifies the value for EMC_MRS_WAIT_CNT2 */
-	u32 EmcMrsWaitCnt2;
-
-	/* EMC miscellaneous configurations */
-
-	/* Specifies the value for EMC_CFG */
-	u32 EmcCfg;
-	/* Specifies the value for EMC_CFG_2 */
-	u32 EmcCfg2;
-	/* Specifies the pipe bypass controls */
-	u32 EmcCfgPipe;
-	u32 EmcCfgPipeClk;
-	u32 EmcFdpdCtrlCmdNoRamp;
-	u32 EmcCfgUpdate;
-
-	/* Specifies the value for EMC_DBG */
-	u32 EmcDbg;
-	u32 EmcDbgWriteMux;
-
-	/* Specifies the value for EMC_CMDQ */
-	u32 EmcCmdQ;
-	/* Specifies the value for EMC_MC2EMCQ */
-	u32 EmcMc2EmcQ;
-	/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
-	u32 EmcDynSelfRefControl;
-
-	/* Specifies the value for MEM_INIT_DONE */
-	u32 AhbArbitrationXbarCtrlMemInitDone;
-
-	/* Specifies the value for EMC_CFG_DIG_DLL */
-	u32 EmcCfgDigDll;
-	u32 EmcCfgDigDll_1;
-	/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
-	u32 EmcCfgDigDllPeriod;
-	/* Specifies the value of *DEV_SELECTN of various EMC registers */
-	u32 EmcDevSelect;
-
-	/* Specifies the value for EMC_SEL_DPD_CTRL */
-	u32 EmcSelDpdCtrl;
-
-	/* Pads trimmer delays */
-	u32 EmcFdpdCtrlDq;
-	u32 EmcFdpdCtrlCmd;
-	u32 EmcPmacroIbVrefDq_0;
-	u32 EmcPmacroIbVrefDq_1;
-	u32 EmcPmacroIbVrefDqs_0;
-	u32 EmcPmacroIbVrefDqs_1;
-	u32 EmcPmacroIbRxrt;
-	u32 EmcCfgPipe1;
-	u32 EmcCfgPipe2;
-
-	/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
-	u32 EmcPmacroQuseDdllRank0_0;
-	u32 EmcPmacroQuseDdllRank0_1;
-	u32 EmcPmacroQuseDdllRank0_2;
-	u32 EmcPmacroQuseDdllRank0_3;
-	u32 EmcPmacroQuseDdllRank0_4;
-	u32 EmcPmacroQuseDdllRank0_5;
-	u32 EmcPmacroQuseDdllRank1_0;
-	u32 EmcPmacroQuseDdllRank1_1;
-	u32 EmcPmacroQuseDdllRank1_2;
-	u32 EmcPmacroQuseDdllRank1_3;
-	u32 EmcPmacroQuseDdllRank1_4;
-	u32 EmcPmacroQuseDdllRank1_5;
-
-	u32 EmcPmacroObDdllLongDqRank0_0;
-	u32 EmcPmacroObDdllLongDqRank0_1;
-	u32 EmcPmacroObDdllLongDqRank0_2;
-	u32 EmcPmacroObDdllLongDqRank0_3;
-	u32 EmcPmacroObDdllLongDqRank0_4;
-	u32 EmcPmacroObDdllLongDqRank0_5;
-	u32 EmcPmacroObDdllLongDqRank1_0;
-	u32 EmcPmacroObDdllLongDqRank1_1;
-	u32 EmcPmacroObDdllLongDqRank1_2;
-	u32 EmcPmacroObDdllLongDqRank1_3;
-	u32 EmcPmacroObDdllLongDqRank1_4;
-	u32 EmcPmacroObDdllLongDqRank1_5;
-
-	u32 EmcPmacroObDdllLongDqsRank0_0;
-	u32 EmcPmacroObDdllLongDqsRank0_1;
-	u32 EmcPmacroObDdllLongDqsRank0_2;
-	u32 EmcPmacroObDdllLongDqsRank0_3;
-	u32 EmcPmacroObDdllLongDqsRank0_4;
-	u32 EmcPmacroObDdllLongDqsRank0_5;
-	u32 EmcPmacroObDdllLongDqsRank1_0;
-	u32 EmcPmacroObDdllLongDqsRank1_1;
-	u32 EmcPmacroObDdllLongDqsRank1_2;
-	u32 EmcPmacroObDdllLongDqsRank1_3;
-	u32 EmcPmacroObDdllLongDqsRank1_4;
-	u32 EmcPmacroObDdllLongDqsRank1_5;
-
-	u32 EmcPmacroIbDdllLongDqsRank0_0;
-	u32 EmcPmacroIbDdllLongDqsRank0_1;
-	u32 EmcPmacroIbDdllLongDqsRank0_2;
-	u32 EmcPmacroIbDdllLongDqsRank0_3;
-	u32 EmcPmacroIbDdllLongDqsRank1_0;
-	u32 EmcPmacroIbDdllLongDqsRank1_1;
-	u32 EmcPmacroIbDdllLongDqsRank1_2;
-	u32 EmcPmacroIbDdllLongDqsRank1_3;
-
-	u32 EmcPmacroDdllLongCmd_0;
-	u32 EmcPmacroDdllLongCmd_1;
-	u32 EmcPmacroDdllLongCmd_2;
-	u32 EmcPmacroDdllLongCmd_3;
-	u32 EmcPmacroDdllLongCmd_4;
-	u32 EmcPmacroDdllShortCmd_0;
-	u32 EmcPmacroDdllShortCmd_1;
-	u32 EmcPmacroDdllShortCmd_2;
-
-	/*
-	 * Specifies the delay after asserting CKE pin during a WarmBoot0
-	 * sequence (in microseconds)
-	 */
-	u32 WarmBootWait;
-
-	/* Specifies the value for EMC_ODT_WRITE */
-	u32 EmcOdtWrite;
-
-	/* Periodic ZQ calibration */
-
-	/*
-	 * Specifies the value for EMC_ZCAL_INTERVAL
-	 * Value 0 disables ZQ calibration
-	 */
-	u32 EmcZcalInterval;
-	/* Specifies the value for EMC_ZCAL_WAIT_CNT */
-	u32 EmcZcalWaitCnt;
-	/* Specifies the value for EMC_ZCAL_MRW_CMD */
-	u32 EmcZcalMrwCmd;
-
-	/* DRAM initialization sequence flow control */
-
-	/* Specifies the MRS command value for resetting DLL */
-	u32 EmcMrsResetDll;
-	/* Specifies the command for ZQ initialization of device 0 */
-	u32 EmcZcalInitDev0;
-	/* Specifies the command for ZQ initialization of device 1 */
-	u32 EmcZcalInitDev1;
-	/*
-	 * Specifies the wait time after programming a ZQ initialization
-	 * command (in microseconds)
-	 */
-	u32 EmcZcalInitWait;
-	/*
-	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
-	 * and warm boot [bit 1]
-	 */
-	u32 EmcZcalWarmColdBootEnables;
-
-	/*
-	 * Specifies the MRW command to LPDDR2 for ZQ calibration
-	 * on warmboot
-	 */
-	/* Is issued to both devices separately */
-	u32 EmcMrwLpddr2ZcalWarmBoot;
-	/*
-	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
-	 * Is issued to both devices separately
-	 */
-	u32 EmcZqCalDdr3WarmBoot;
-	u32 EmcZqCalLpDdr4WarmBoot;
-	/*
-	 * Specifies the wait time for ZQ calibration on warmboot
-	 * (in microseconds)
-	 */
-	u32 EmcZcalWarmBootWait;
-	/*
-	 * Specifies the enable for DRAM Mode Register programming
-	 * at warm boot
-	 */
-	u32 EmcMrsWarmBootEnable;
-	/*
-	 * Specifies the wait time after sending an MRS DLL reset command
-	 * in microseconds)
-	 */
-	u32 EmcMrsResetDllWait;
-	/* Specifies the extra MRS command to initialize mode registers */
-	u32 EmcMrsExtra;
-	/* Specifies the extra MRS command at warm boot */
-	u32 EmcWarmBootMrsExtra;
-	/* Specifies the EMRS command to enable the DDR2 DLL */
-	u32 EmcEmrsDdr2DllEnable;
-	/* Specifies the MRS command to reset the DDR2 DLL */
-	u32 EmcMrsDdr2DllReset;
-	/* Specifies the EMRS command to set OCD calibration */
-	u32 EmcEmrsDdr2OcdCalib;
-	/*
-	 * Specifies the wait between initializing DDR and setting OCD
-	 * calibration (in microseconds)
-	 */
-	u32 EmcDdr2Wait;
-	/* Specifies the value for EMC_CLKEN_OVERRIDE */
-	u32 EmcClkenOverride;
-
-	/*
-	 * Specifies LOG2 of the extra refresh numbers after booting
-	 * Program 0 to disable
-	 */
-	u32 EmcExtraRefreshNum;
-	/* Specifies the master override for all EMC clocks */
-	u32 EmcClkenOverrideAllWarmBoot;
-	/* Specifies the master override for all MC clocks */
-	u32 McClkenOverrideAllWarmBoot;
-	/* Specifies digital dll period, choosing between 4 to 64 ms */
-	u32 EmcCfgDigDllPeriodWarmBoot;
-
-	/* Pad controls */
-
-	/* Specifies the value for PMC_VDDP_SEL */
-	u32 PmcVddpSel;
-	/* Specifies the wait time after programming PMC_VDDP_SEL */
-	u32 PmcVddpSelWait;
-	/* Specifies the value for PMC_DDR_PWR */
-	u32 PmcDdrPwr;
-	/* Specifies the value for PMC_DDR_CFG */
-	u32 PmcDdrCfg;
-	/* Specifies the value for PMC_IO_DPD3_REQ */
-	u32 PmcIoDpd3Req;
-	/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
-	u32 PmcIoDpd3ReqWait;
-	u32 PmcIoDpd4ReqWait;
-
-	/* Specifies the value for PMC_REG_SHORT */
-	u32 PmcRegShort;
-	/* Specifies the value for PMC_NO_IOPOWER */
-	u32 PmcNoIoPower;
-
-	u32 PmcDdrCntrlWait;
-	u32 PmcDdrCntrl;
-
-	/* Specifies the value for EMC_ACPD_CONTROL */
-	u32 EmcAcpdControl;
-
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */
-	////u32 EmcSwizzleRank0ByteCfg;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
-	u32 EmcSwizzleRank0Byte0;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
-	u32 EmcSwizzleRank0Byte1;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
-	u32 EmcSwizzleRank0Byte2;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
-	u32 EmcSwizzleRank0Byte3;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */
-	////u32 EmcSwizzleRank1ByteCfg;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
-	u32 EmcSwizzleRank1Byte0;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
-	u32 EmcSwizzleRank1Byte1;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
-	u32 EmcSwizzleRank1Byte2;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
-	u32 EmcSwizzleRank1Byte3;
-
-	/* Specifies the value for EMC_TXDSRVTTGEN */
-	u32 EmcTxdsrvttgen;
-
-	/* Specifies the value for EMC_DATA_BRLSHFT_0 */
-	u32 EmcDataBrlshft0;
-	u32 EmcDataBrlshft1;
-
-	u32 EmcDqsBrlshft0;
-	u32 EmcDqsBrlshft1;
-
-	u32 EmcCmdBrlshft0;
-	u32 EmcCmdBrlshft1;
-	u32 EmcCmdBrlshft2;
-	u32 EmcCmdBrlshft3;
-
-	u32 EmcQuseBrlshft0;
-	u32 EmcQuseBrlshft1;
-	u32 EmcQuseBrlshft2;
-	u32 EmcQuseBrlshft3;
-
-	u32 EmcDllCfg0;
-	u32 EmcDllCfg1;
-
-	u32 EmcPmcScratch1;
-	u32 EmcPmcScratch2;
-	u32 EmcPmcScratch3;
-
-	u32 EmcPmacroPadCfgCtrl;
-
-	u32 EmcPmacroVttgenCtrl0;
-	u32 EmcPmacroVttgenCtrl1;
-	u32 EmcPmacroVttgenCtrl2;
-
-	u32 EmcPmacroBrickCtrlRfu1;
-	u32 EmcPmacroCmdBrickCtrlFdpd;
-	u32 EmcPmacroBrickCtrlRfu2;
-	u32 EmcPmacroDataBrickCtrlFdpd;
-	u32 EmcPmacroBgBiasCtrl0;
-	u32 EmcPmacroDataPadRxCtrl;
-	u32 EmcPmacroCmdPadRxCtrl;
-	u32 EmcPmacroDataRxTermMode;
-	u32 EmcPmacroCmdRxTermMode;
-	u32 EmcPmacroDataPadTxCtrl;
-	u32 EmcPmacroCommonPadTxCtrl;
-	u32 EmcPmacroCmdPadTxCtrl;
-	u32 EmcCfg3;
-
-	u32 EmcPmacroTxPwrd0;
-	u32 EmcPmacroTxPwrd1;
-	u32 EmcPmacroTxPwrd2;
-	u32 EmcPmacroTxPwrd3;
-	u32 EmcPmacroTxPwrd4;
-	u32 EmcPmacroTxPwrd5;
-
-	u32 EmcConfigSampleDelay;
-
-	u32 EmcPmacroBrickMapping0;
-	u32 EmcPmacroBrickMapping1;
-	u32 EmcPmacroBrickMapping2;
-
-	u32 EmcPmacroTxSelClkSrc0;
-	u32 EmcPmacroTxSelClkSrc1;
-	u32 EmcPmacroTxSelClkSrc2;
-	u32 EmcPmacroTxSelClkSrc3;
-	u32 EmcPmacroTxSelClkSrc4;
-	u32 EmcPmacroTxSelClkSrc5;
-
-	u32 EmcPmacroDdllBypass;
-
-	u32 EmcPmacroDdllPwrd0;
-	u32 EmcPmacroDdllPwrd1;
-	u32 EmcPmacroDdllPwrd2;
-
-	u32 EmcPmacroCmdCtrl0;
-	u32 EmcPmacroCmdCtrl1;
-	u32 EmcPmacroCmdCtrl2;
-
-	/* DRAM size information */
-
-	/* Specifies the value for MC_EMEM_ADR_CFG */
-	u32 McEmemAdrCfg;
-	/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
-	u32 McEmemAdrCfgDev0;
-	/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
-	u32 McEmemAdrCfgDev1;
-	u32 McEmemAdrCfgChannelMask;
-
-	/* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */
-	u32 McEmemAdrCfgBankMask0;
-	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
-	u32 McEmemAdrCfgBankMask1;
-	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
-	u32 McEmemAdrCfgBankMask2;
-
-	/*
-	 * Specifies the value for MC_EMEM_CFG which holds the external memory
-	 * size (in KBytes)
-	 */
-	u32 McEmemCfg;
-
-	/* MC arbitration configuration */
-
-	/* Specifies the value for MC_EMEM_ARB_CFG */
-	u32 McEmemArbCfg;
-	/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
-	u32 McEmemArbOutstandingReq;
-
-	u32 McEmemArbRefpbHpCtrl;
-	u32 McEmemArbRefpbBankCtrl;
-
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
-	u32 McEmemArbTimingRcd;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
-	u32 McEmemArbTimingRp;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
-	u32 McEmemArbTimingRc;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
-	u32 McEmemArbTimingRas;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
-	u32 McEmemArbTimingFaw;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
-	u32 McEmemArbTimingRrd;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
-	u32 McEmemArbTimingRap2Pre;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
-	u32 McEmemArbTimingWap2Pre;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
-	u32 McEmemArbTimingR2R;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
-	u32 McEmemArbTimingW2W;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
-	u32 McEmemArbTimingR2W;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
-	u32 McEmemArbTimingW2R;
-
-	u32 McEmemArbTimingRFCPB;
-
-	/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
-	u32 McEmemArbDaTurns;
-	/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
-	u32 McEmemArbDaCovers;
-	/* Specifies the value for MC_EMEM_ARB_MISC0 */
-	u32 McEmemArbMisc0;
-	/* Specifies the value for MC_EMEM_ARB_MISC1 */
-	u32 McEmemArbMisc1;
-	u32 McEmemArbMisc2;
-
-	/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
-	u32 McEmemArbRing1Throttle;
-	/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
-	u32 McEmemArbOverride;
-	/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
-	u32 McEmemArbOverride1;
-	/* Specifies the value for MC_EMEM_ARB_RSV */
-	u32 McEmemArbRsv;
-
-	u32 McDaCfg0;
-	u32 McEmemArbTimingCcdmw;
-
-	/* Specifies the value for MC_CLKEN_OVERRIDE */
-	u32 McClkenOverride;
-
-	/* Specifies the value for MC_STAT_CONTROL */
-	u32 McStatControl;
-
-	/* Specifies the value for MC_VIDEO_PROTECT_BOM */
-	u32 McVideoProtectBom;
-	/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
-	u32 McVideoProtectBomAdrHi;
-	/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
-	u32 McVideoProtectSizeMb;
-	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
-	u32 McVideoProtectVprOverride;
-	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
-	u32 McVideoProtectVprOverride1;
-	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
-	u32 McVideoProtectGpuOverride0;
-	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
-	u32 McVideoProtectGpuOverride1;
-	/* Specifies the value for MC_SEC_CARVEOUT_BOM */
-	u32 McSecCarveoutBom;
-	/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
-	u32 McSecCarveoutAdrHi;
-	/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
-	u32 McSecCarveoutSizeMb;
-	/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.
-	   VIDEO_PROTECT_WRITEAccess */
-	u32 McVideoProtectWriteAccess;
-	/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.
-	   SEC_CARVEOUT_WRITEAccess */
-	u32 McSecCarveoutProtectWriteAccess;
-
-	/* Write-Protect Regions (WPR) */
-	u32 McGeneralizedCarveout1Bom;
-	u32 McGeneralizedCarveout1BomHi;
-	u32 McGeneralizedCarveout1Size128kb;
-	u32 McGeneralizedCarveout1Access0;
-	u32 McGeneralizedCarveout1Access1;
-	u32 McGeneralizedCarveout1Access2;
-	u32 McGeneralizedCarveout1Access3;
-	u32 McGeneralizedCarveout1Access4;
-	u32 McGeneralizedCarveout1ForceInternalAccess0;
-	u32 McGeneralizedCarveout1ForceInternalAccess1;
-	u32 McGeneralizedCarveout1ForceInternalAccess2;
-	u32 McGeneralizedCarveout1ForceInternalAccess3;
-	u32 McGeneralizedCarveout1ForceInternalAccess4;
-	u32 McGeneralizedCarveout1Cfg0;
-
-	u32 McGeneralizedCarveout2Bom;
-	u32 McGeneralizedCarveout2BomHi;
-	u32 McGeneralizedCarveout2Size128kb;
-	u32 McGeneralizedCarveout2Access0;
-	u32 McGeneralizedCarveout2Access1;
-	u32 McGeneralizedCarveout2Access2;
-	u32 McGeneralizedCarveout2Access3;
-	u32 McGeneralizedCarveout2Access4;
-	u32 McGeneralizedCarveout2ForceInternalAccess0;
-	u32 McGeneralizedCarveout2ForceInternalAccess1;
-	u32 McGeneralizedCarveout2ForceInternalAccess2;
-	u32 McGeneralizedCarveout2ForceInternalAccess3;
-	u32 McGeneralizedCarveout2ForceInternalAccess4;
-	u32 McGeneralizedCarveout2Cfg0;
-
-	u32 McGeneralizedCarveout3Bom;
-	u32 McGeneralizedCarveout3BomHi;
-	u32 McGeneralizedCarveout3Size128kb;
-	u32 McGeneralizedCarveout3Access0;
-	u32 McGeneralizedCarveout3Access1;
-	u32 McGeneralizedCarveout3Access2;
-	u32 McGeneralizedCarveout3Access3;
-	u32 McGeneralizedCarveout3Access4;
-	u32 McGeneralizedCarveout3ForceInternalAccess0;
-	u32 McGeneralizedCarveout3ForceInternalAccess1;
-	u32 McGeneralizedCarveout3ForceInternalAccess2;
-	u32 McGeneralizedCarveout3ForceInternalAccess3;
-	u32 McGeneralizedCarveout3ForceInternalAccess4;
-	u32 McGeneralizedCarveout3Cfg0;
-
-	u32 McGeneralizedCarveout4Bom;
-	u32 McGeneralizedCarveout4BomHi;
-	u32 McGeneralizedCarveout4Size128kb;
-	u32 McGeneralizedCarveout4Access0;
-	u32 McGeneralizedCarveout4Access1;
-	u32 McGeneralizedCarveout4Access2;
-	u32 McGeneralizedCarveout4Access3;
-	u32 McGeneralizedCarveout4Access4;
-	u32 McGeneralizedCarveout4ForceInternalAccess0;
-	u32 McGeneralizedCarveout4ForceInternalAccess1;
-	u32 McGeneralizedCarveout4ForceInternalAccess2;
-	u32 McGeneralizedCarveout4ForceInternalAccess3;
-	u32 McGeneralizedCarveout4ForceInternalAccess4;
-	u32 McGeneralizedCarveout4Cfg0;
-
-	u32 McGeneralizedCarveout5Bom;
-	u32 McGeneralizedCarveout5BomHi;
-	u32 McGeneralizedCarveout5Size128kb;
-	u32 McGeneralizedCarveout5Access0;
-	u32 McGeneralizedCarveout5Access1;
-	u32 McGeneralizedCarveout5Access2;
-	u32 McGeneralizedCarveout5Access3;
-	u32 McGeneralizedCarveout5Access4;
-	u32 McGeneralizedCarveout5ForceInternalAccess0;
-	u32 McGeneralizedCarveout5ForceInternalAccess1;
-	u32 McGeneralizedCarveout5ForceInternalAccess2;
-	u32 McGeneralizedCarveout5ForceInternalAccess3;
-	u32 McGeneralizedCarveout5ForceInternalAccess4;
-	u32 McGeneralizedCarveout5Cfg0;
-
-	/* Specifies enable for CA training */
-	u32 EmcCaTrainingEnable;
-
-	/* Set if bit 6 select is greater than bit 7 select; uses aremc.
-	   spec packet SWIZZLE_BIT6_GT_BIT7 */
-	u32 SwizzleRankByteEncode;
-	/* Specifies enable and offset for patched boot ROM write */
-	u32 BootRomPatchControl;
-	/* Specifies data for patched boot ROM write */
-	u32 BootRomPatchData;
-
-	/* Specifies the value for MC_MTS_CARVEOUT_BOM */
-	u32 McMtsCarveoutBom;
-	/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
-	u32 McMtsCarveoutAdrHi;
-	/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
-	u32 McMtsCarveoutSizeMb;
-	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
-	u32 McMtsCarveoutRegCtrl;
-
-	/* End */
-};
-
-#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */
--- a/bdk/mem/sdram_lp0_param_t210b01.h
+++ b/bdk/mem/sdram_lp0_param_t210b01.h
@ -1,990 +0,0 @@
-/*
- * Copyright (c) 2020 CTCaer
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-
-#ifndef __TEGRA210B01_SDRAM_PARAM_H__
-#define __TEGRA210B01_SDRAM_PARAM_H__
-
-#include <utils/types.h>
-
-struct sdram_params_t210b01
-{
-	/* Specifies the type of memory device */
-	u32 memory_type;
-
-	/* MC/EMC clock source configuration */
-
-	/* Specifies the M value for PllM */
-	u32 pllm_input_divider;
-	/* Specifies the N value for PllM */
-	u32 pllm_feedback_divider;
-	/* Specifies the time to wait for PLLM to lock (in microseconds) */
-	u32 pllm_stable_time;
-	/* Specifies misc. control bits */
-	u32 pllm_setup_control;
-	/* Specifies the P value for PLLM */
-	u32 pllm_post_divider;
-	/* Specifies value for Charge Pump Gain Control */
-	u32 pllm_kcp;
-	/* Specifies VCO gain */
-	u32 pllm_kvco;
-	/* Spare BCT param */
-	u32 emc_bct_spare0;
-	/* Spare BCT param */
-	u32 emc_bct_spare1;
-	/* Spare BCT param */
-	u32 emc_bct_spare2;
-	/* Spare BCT param */
-	u32 emc_bct_spare3;
-	/* Spare BCT param */
-	u32 emc_bct_spare4;
-	/* Spare BCT param */
-	u32 emc_bct_spare5;
-	/* Spare BCT param */
-	u32 emc_bct_spare6;
-	/* Spare BCT param */
-	u32 emc_bct_spare7;
-	/* Spare BCT param */
-	u32 emc_bct_spare8;
-	/* Spare BCT param */
-	u32 emc_bct_spare9;
-	/* Spare BCT param */
-	u32 emc_bct_spare10;
-	/* Spare BCT param */
-	u32 emc_bct_spare11;
-	/* Spare BCT param */
-	u32 emc_bct_spare12;
-	/* Spare BCT param */
-	u32 emc_bct_spare13;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure0;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure1;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure2;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure3;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure4;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure5;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure6;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure7;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure8;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure9;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure10;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure11;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure12;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure13;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure14;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure15;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure16;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure17;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure18;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure19;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure20;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure21;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure22;
-	/* Spare BCT param */
-	u32 emc_bct_spare_secure23;
-
-	/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
-	u32 emc_clock_source;
-	u32 emc_clock_source_dll;
-
-	/* Defines possible override for PLLLM_MISC2 */
-	u32 clk_rst_pllm_misc20_override;
-	/* enables override for PLLLM_MISC2 */
-	u32 clk_rst_pllm_misc20_override_enable;
-	/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
-	u32 clear_clock2_mc1;
-
-	/* Auto-calibration of EMC pads */
-
-	/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
-	u32 emc_auto_cal_interval;
-	/*
-	 * Specifies the value for EMC_AUTO_CAL_CONFIG
-	 * Note: Trigger bits are set by the SDRAM code.
-	 */
-	u32 emc_auto_cal_config;
-
-	/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
-	u32 emc_auto_cal_config2;
-
-	/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
-	u32 emc_auto_cal_config3;
-	u32 emc_auto_cal_config4;
-	u32 emc_auto_cal_config5;
-	u32 emc_auto_cal_config6;
-	u32 emc_auto_cal_config7;
-	u32 emc_auto_cal_config8;
-	u32 emc_auto_cal_config9;
-
-	/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
-	u32 emc_auto_cal_vref_sel0;
-	u32 emc_auto_cal_vref_sel1;
-
-	/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
-	u32 emc_auto_cal_channel;
-
-	/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
-	u32 emc_pmacro_auto_cal_cfg0;
-	u32 emc_pmacro_auto_cal_cfg1;
-	u32 emc_pmacro_auto_cal_cfg2;
-
-	u32 emc_pmacro_rx_term;
-	u32 emc_pmacro_dq_tx_drive;
-	u32 emc_pmacro_ca_tx_drive;
-	u32 emc_pmacro_cmd_tx_drive;
-	u32 emc_pmacro_auto_cal_common;
-	u32 emc_pmacro_zcrtl;
-
-	/*
-	 * Specifies the time for the calibration
-	 * to stabilize (in microseconds)
-	 */
-	u32 emc_auto_cal_wait;
-
-	u32 emc_xm2_comp_pad_ctrl;
-	u32 emc_xm2_comp_pad_ctrl2;
-	u32 emc_xm2_comp_pad_ctrl3;
-
-	/*
-	 * DRAM size information
-	 * Specifies the value for EMC_ADR_CFG
-	 */
-	u32 emc_adr_cfg;
-
-	/*
-	 * Specifies the time to wait after asserting pin
-	 * CKE (in microseconds)
-	 */
-	u32 emc_pin_program_wait;
-	/* Specifies the extra delay before/after pin RESET/CKE command */
-	u32 emc_pin_extra_wait;
-
-	u32 emc_pin_gpio_enable;
-	u32 emc_pin_gpio;
-
-	/*
-	 * Specifies the extra delay after the first writing
-	 * of EMC_TIMING_CONTROL
-	 */
-	u32 emc_timing_control_wait;
-
-	/* Timing parameters required for the SDRAM */
-
-	/* Specifies the value for EMC_RC */
-	u32 emc_rc;
-	/* Specifies the value for EMC_RFC */
-	u32 emc_rfc;
-
-	u32 emc_rfc_pb;
-	u32 emc_ref_ctrl2;
-
-	/* Specifies the value for EMC_RFC_SLR */
-	u32 emc_rfc_slr;
-	/* Specifies the value for EMC_RAS */
-	u32 emc_ras;
-	/* Specifies the value for EMC_RP */
-	u32 emc_rp;
-	/* Specifies the value for EMC_R2R */
-	u32 emc_r2r;
-	/* Specifies the value for EMC_W2W */
-	u32 emc_w2w;
-	/* Specifies the value for EMC_R2W */
-	u32 emc_r2w;
-	/* Specifies the value for EMC_W2R */
-	u32 emc_w2r;
-	/* Specifies the value for EMC_R2P */
-	u32 emc_r2p;
-	/* Specifies the value for EMC_W2P */
-	u32 emc_w2p;
-	/* Specifies the value for EMC_RD_RCD */
-
-	u32 emc_tppd;
-	u32 emc_trtm;
-	u32 emc_twtm;
-	u32 emc_tratm;
-	u32 emc_twatm;
-	u32 emc_tr2ref;
-	u32 emc_ccdmw;
-
-	u32 emc_rd_rcd;
-	/* Specifies the value for EMC_WR_RCD */
-	u32 emc_wr_rcd;
-	/* Specifies the value for EMC_RRD */
-	u32 emc_rrd;
-	/* Specifies the value for EMC_REXT */
-	u32 emc_rext;
-	/* Specifies the value for EMC_WEXT */
-	u32 emc_wext;
-	/* Specifies the value for EMC_WDV */
-	u32 emc_wdv;
-
-	u32 emc_wdv_chk;
-	u32 emc_wsv;
-	u32 emc_wev;
-
-	/* Specifies the value for EMC_WDV_MASK */
-	u32 emc_wdv_mask;
-
-	u32 emc_ws_duration;
-	u32 emc_we_duration;
-
-	/* Specifies the value for EMC_QUSE */
-	u32 emc_quse;
-	/* Specifies the value for EMC_QUSE_WIDTH */
-	u32 emc_quse_width;
-	/* Specifies the value for EMC_IBDLY */
-	u32 emc_ibdly;
-
-	u32 emc_obdly;
-
-	/* Specifies the value for EMC_EINPUT */
-	u32 emc_einput;
-	/* Specifies the value for EMC_EINPUT_DURATION */
-	u32 emc_einput_duration;
-	/* Specifies the value for EMC_PUTERM_EXTRA */
-	u32 emc_puterm_extra;
-	/* Specifies the value for EMC_PUTERM_WIDTH */
-	u32 emc_puterm_width;
-
-	u32 emc_qrst;
-	u32 emc_qsafe;
-	u32 emc_rdv;
-	u32 emc_rdv_mask;
-
-	u32 emc_rdv_early;
-	u32 emc_rdv_early_mask;
-
-	/* Specifies the value for EMC_QPOP */
-	u32 emc_qpop;
-
-	/* Specifies the value for EMC_REFRESH */
-	u32 emc_refresh;
-	/* Specifies the value for EMC_BURST_REFRESH_NUM */
-	u32 emc_burst_refresh_num;
-	/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
-	u32 emc_prerefresh_req_cnt;
-	/* Specifies the value for EMC_PDEX2WR */
-	u32 emc_pdex2wr;
-	/* Specifies the value for EMC_PDEX2RD */
-	u32 emc_pdex2rd;
-	/* Specifies the value for EMC_PCHG2PDEN */
-	u32 emc_pchg2pden;
-	/* Specifies the value for EMC_ACT2PDEN */
-	u32 emc_act2pden;
-	/* Specifies the value for EMC_AR2PDEN */
-	u32 emc_ar2pden;
-	/* Specifies the value for EMC_RW2PDEN */
-	u32 emc_rw2pden;
-
-	u32 emc_cke2pden;
-	u32 emc_pdex2che;
-	u32 emc_pdex2mrr;
-
-	/* Specifies the value for EMC_TXSR */
-	u32 emc_txsr;
-	/* Specifies the value for EMC_TXSRDLL */
-	u32 emc_txsr_dll;
-	/* Specifies the value for EMC_TCKE */
-	u32 emc_tcke;
-	/* Specifies the value for EMC_TCKESR */
-	u32 emc_tckesr;
-	/* Specifies the value for EMC_TPD */
-	u32 emc_tpd;
-	/* Specifies the value for EMC_TFAW */
-	u32 emc_tfaw;
-	/* Specifies the value for EMC_TRPAB */
-	u32 emc_trpab;
-	/* Specifies the value for EMC_TCLKSTABLE */
-	u32 emc_tclkstable;
-	/* Specifies the value for EMC_TCLKSTOP */
-	u32 emc_tclkstop;
-	/* Specifies the value for EMC_TREFBW */
-	u32 emc_trefbw;
-
-	/* FBIO configuration values */
-
-	/* Specifies the value for EMC_FBIO_CFG5 */
-	u32 emc_fbio_cfg5;
-	/* Specifies the value for EMC_FBIO_CFG7 */
-	u32 emc_fbio_cfg7;
-	u32 emc_fbio_cfg8;
-
-	/* Command mapping for CMD brick 0 */
-	u32 emc_cmd_mapping_cmd0_0;
-	u32 emc_cmd_mapping_cmd0_1;
-	u32 emc_cmd_mapping_cmd0_2;
-	u32 emc_cmd_mapping_cmd1_0;
-	u32 emc_cmd_mapping_cmd1_1;
-	u32 emc_cmd_mapping_cmd1_2;
-	u32 emc_cmd_mapping_cmd2_0;
-	u32 emc_cmd_mapping_cmd2_1;
-	u32 emc_cmd_mapping_cmd2_2;
-	u32 emc_cmd_mapping_cmd3_0;
-	u32 emc_cmd_mapping_cmd3_1;
-	u32 emc_cmd_mapping_cmd3_2;
-	u32 emc_cmd_mapping_byte;
-
-	/* Specifies the value for EMC_FBIO_SPARE */
-	u32 emc_fbio_spare;
-
-	/* Specifies the value for EMC_CFG_RSV */
-	u32 emc_cfg_rsv;
-
-	/* MRS command values */
-
-	/* Specifies the value for EMC_MRS */
-	u32 emc_mrs;
-	/* Specifies the MP0 command to initialize mode registers */
-	u32 emc_emrs;
-	/* Specifies the MP2 command to initialize mode registers */
-	u32 emc_emrs2;
-	/* Specifies the MP3 command to initialize mode registers */
-	u32 emc_emrs3;
-	/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
-	u32 emc_mrw1;
-	/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
-	u32 emc_mrw2;
-	/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
-	u32 emc_mrw3;
-	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
-	u32 emc_mrw4;
-
-	/* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */
-	u32 emc_mrw6;
-	/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
-	u32 emc_mrw8;
-	/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
-	u32 emc_mrw9;
-	/* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */
-	u32 emc_mrw10;
-	/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
-	u32 emc_mrw12;
-	/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
-	u32 emc_mrw13;
-	/* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */
-	u32 emc_mrw14;
-
-	/*
-	 * Specifies the programming to extra LPDDR2 Mode Register
-	 * at cold boot
-	 */
-	u32 emc_mrw_extra;
-	/*
-	 * Specifies the programming to extra LPDDR2 Mode Register
-	 * at warm boot
-	 */
-	u32 emc_warm_boot_mrw_extra;
-	/*
-	 * Specify the enable of extra Mode Register programming at
-	 * warm boot
-	 */
-	u32 emc_warm_boot_extramode_reg_write_enable;
-	/*
-	 * Specify the enable of extra Mode Register programming at
-	 * cold boot
-	 */
-	u32 emc_extramode_reg_write_enable;
-
-	/* Specifies the EMC_MRW reset command value */
-	u32 emc_mrw_reset_command;
-	/* Specifies the EMC Reset wait time (in microseconds) */
-	u32 emc_mrw_reset_ninit_wait;
-	/* Specifies the value for EMC_MRS_WAIT_CNT */
-	u32 emc_mrs_wait_cnt;
-	/* Specifies the value for EMC_MRS_WAIT_CNT2 */
-	u32 emc_mrs_wait_cnt2;
-
-	/* EMC miscellaneous configurations */
-
-	/* Specifies the value for EMC_CFG */
-	u32 emc_cfg;
-	/* Specifies the value for EMC_CFG_2 */
-	u32 emc_cfg2;
-	/* Specifies the pipe bypass controls */
-	u32 emc_cfg_pipe;
-
-	u32 emc_cfg_pipe_clk;
-	u32 emc_fdpd_ctrl_cmd_no_ramp;
-	u32 emc_cfg_update;
-
-	/* Specifies the value for EMC_DBG */
-	u32 emc_dbg;
-
-	u32 emc_dbg_write_mux;
-
-	/* Specifies the value for EMC_CMDQ */
-	u32 emc_cmd_q;
-	/* Specifies the value for EMC_MC2EMCQ */
-	u32 emc_mc2emc_q;
-	/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
-	u32 emc_dyn_self_ref_control;
-
-	/* Specifies the value for MEM_INIT_DONE */
-	u32 ahb_arbitration_xbar_ctrl_meminit_done;
-
-	/* Specifies the value for EMC_CFG_DIG_DLL */
-	u32 emc_cfg_dig_dll;
-	u32 emc_cfg_dig_dll_1;
-
-	/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
-	u32 emc_cfg_dig_dll_period;
-	/* Specifies the value of *DEV_SELECTN of various EMC registers */
-	u32 emc_dev_select;
-
-	/* Specifies the value for EMC_SEL_DPD_CTRL */
-	u32 emc_sel_dpd_ctrl;
-
-	/* Pads trimmer delays */
-	u32 emc_fdpd_ctrl_dq;
-	u32 emc_fdpd_ctrl_cmd;
-	u32 emc_pmacro_ib_vref_dq_0;
-	u32 emc_pmacro_ib_vref_dq_1;
-	u32 emc_pmacro_ib_vref_dqs_0;
-	u32 emc_pmacro_ib_vref_dqs_1;
-	u32 emc_pmacro_ib_rxrt;
-	u32 emc_cfg_pipe1;
-	u32 emc_cfg_pipe2;
-
-	/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
-	u32 emc_pmacro_quse_ddll_rank0_0;
-	u32 emc_pmacro_quse_ddll_rank0_1;
-	u32 emc_pmacro_quse_ddll_rank0_2;
-	u32 emc_pmacro_quse_ddll_rank0_3;
-	u32 emc_pmacro_quse_ddll_rank0_4;
-	u32 emc_pmacro_quse_ddll_rank0_5;
-	u32 emc_pmacro_quse_ddll_rank1_0;
-	u32 emc_pmacro_quse_ddll_rank1_1;
-	u32 emc_pmacro_quse_ddll_rank1_2;
-	u32 emc_pmacro_quse_ddll_rank1_3;
-	u32 emc_pmacro_quse_ddll_rank1_4;
-	u32 emc_pmacro_quse_ddll_rank1_5;
-
-	u32 emc_pmacro_ob_ddll_long_dq_rank0_0;
-	u32 emc_pmacro_ob_ddll_long_dq_rank0_1;
-	u32 emc_pmacro_ob_ddll_long_dq_rank0_2;
-	u32 emc_pmacro_ob_ddll_long_dq_rank0_3;
-	u32 emc_pmacro_ob_ddll_long_dq_rank0_4;
-	u32 emc_pmacro_ob_ddll_long_dq_rank0_5;
-	u32 emc_pmacro_ob_ddll_long_dq_rank1_0;
-	u32 emc_pmacro_ob_ddll_long_dq_rank1_1;
-	u32 emc_pmacro_ob_ddll_long_dq_rank1_2;
-	u32 emc_pmacro_ob_ddll_long_dq_rank1_3;
-	u32 emc_pmacro_ob_ddll_long_dq_rank1_4;
-	u32 emc_pmacro_ob_ddll_long_dq_rank1_5;
-
-	u32 emc_pmacro_ob_ddll_long_dqs_rank0_0;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank0_1;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank0_2;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank0_3;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank0_4;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank0_5;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank1_0;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank1_1;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank1_2;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank1_3;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank1_4;
-	u32 emc_pmacro_ob_ddll_long_dqs_rank1_5;
-
-	u32 emc_pmacro_ib_ddll_long_dqs_rank0_0;
-	u32 emc_pmacro_ib_ddll_long_dqs_rank0_1;
-	u32 emc_pmacro_ib_ddll_long_dqs_rank0_2;
-	u32 emc_pmacro_ib_ddll_long_dqs_rank0_3;
-	u32 emc_pmacro_ib_ddll_long_dqs_rank1_0;
-	u32 emc_pmacro_ib_ddll_long_dqs_rank1_1;
-	u32 emc_pmacro_ib_ddll_long_dqs_rank1_2;
-	u32 emc_pmacro_ib_ddll_long_dqs_rank1_3;
-
-	u32 emc_pmacro_ddll_long_cmd_0;
-	u32 emc_pmacro_ddll_long_cmd_1;
-	u32 emc_pmacro_ddll_long_cmd_2;
-	u32 emc_pmacro_ddll_long_cmd_3;
-	u32 emc_pmacro_ddll_long_cmd_4;
-	u32 emc_pmacro_ddll_short_cmd_0;
-	u32 emc_pmacro_ddll_short_cmd_1;
-	u32 emc_pmacro_ddll_short_cmd_2;
-
-	u32 emc_pmacro_ddll_periodic_offset;
-
-	/*
-	 * Specifies the delay after asserting CKE pin during a WarmBoot0
-	 * sequence (in microseconds)
-	 */
-	u32 warm_boot_wait;
-
-	/* Specifies the value for EMC_ODT_WRITE */
-	u32 emc_odt_write;
-
-	/* Periodic ZQ calibration */
-
-	/*
-	 * Specifies the value for EMC_ZCAL_INTERVAL
-	 * Value 0 disables ZQ calibration
-	 */
-	u32 emc_zcal_interval;
-	/* Specifies the value for EMC_ZCAL_WAIT_CNT */
-	u32 emc_zcal_wait_cnt;
-	/* Specifies the value for EMC_ZCAL_MRW_CMD */
-	u32 emc_zcal_mrw_cmd;
-
-	/* DRAM initialization sequence flow control */
-
-	/* Specifies the MRS command value for resetting DLL */
-	u32 emc_mrs_reset_dll;
-	/* Specifies the command for ZQ initialization of device 0 */
-	u32 emc_zcal_init_dev0;
-	/* Specifies the command for ZQ initialization of device 1 */
-	u32 emc_zcal_init_dev1;
-	/*
-	 * Specifies the wait time after programming a ZQ initialization
-	 * command (in microseconds)
-	 */
-	u32 emc_zcal_init_wait;
-	/*
-	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
-	 * and warm boot [bit 1]
-	 */
-	u32 emc_zcal_warm_cold_boot_enables;
-
-	/*
-	 * Specifies the MRW command to LPDDR2 for ZQ calibration
-	 * on warmboot
-	 */
-	/* Is issued to both devices separately */
-	u32 emc_mrw_lpddr2zcal_warm_boot;
-	/*
-	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
-	 * Is issued to both devices separately
-	 */
-	u32 emc_zqcal_ddr3_warm_boot;
-
-	u32 emc_zqcal_lpddr4_warm_boot;
-
-	/*
-	 * Specifies the wait time for ZQ calibration on warmboot
-	 * (in microseconds)
-	 */
-	u32 emc_zcal_warm_boot_wait;
-	/*
-	 * Specifies the enable for DRAM Mode Register programming
-	 * at warm boot
-	 */
-	u32 emc_mrs_warm_boot_enable;
-	/*
-	 * Specifies the wait time after sending an MRS DLL reset command
-	 * in microseconds)
-	 */
-	u32 emc_mrs_reset_dll_wait;
-	/* Specifies the extra MRS command to initialize mode registers */
-	u32 emc_mrs_extra;
-	/* Specifies the extra MRS command at warm boot */
-	u32 emc_warm_boot_mrs_extra;
-	/* Specifies the EMRS command to enable the DDR2 DLL */
-	u32 emc_emrs_ddr2_dll_enable;
-	/* Specifies the MRS command to reset the DDR2 DLL */
-	u32 emc_mrs_ddr2_dll_reset;
-	/* Specifies the EMRS command to set OCD calibration */
-	u32 emc_emrs_ddr2_ocd_calib;
-	/*
-	 * Specifies the wait between initializing DDR and setting OCD
-	 * calibration (in microseconds)
-	 */
-	u32 emc_ddr2_wait;
-	/* Specifies the value for EMC_CLKEN_OVERRIDE */
-	u32 emc_clken_override;
-	/*
-	 * Specifies LOG2 of the extra refresh numbers after booting
-	 * Program 0 to disable
-	 */
-	u32 emc_extra_refresh_num;
-	/* Specifies the master override for all EMC clocks */
-	u32 emc_clken_override_allwarm_boot;
-	/* Specifies the master override for all MC clocks */
-	u32 mc_clken_override_allwarm_boot;
-	/* Specifies digital dll period, choosing between 4 to 64 ms */
-	u32 emc_cfg_dig_dll_period_warm_boot;
-
-	/* Pad controls */
-
-	/* Specifies the value for PMC_VDDP_SEL */
-	u32 pmc_vddp_sel;
-	/* Specifies the wait time after programming PMC_VDDP_SEL */
-	u32 pmc_vddp_sel_wait;
-	/* Specifies the value for PMC_DDR_CFG */
-	u32 pmc_ddr_cfg;
-	/* Specifies the value for PMC_IO_DPD3_REQ */
-	u32 pmc_io_dpd3_req;
-	/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
-	u32 pmc_io_dpd3_req_wait;
-
-	u32 pmc_io_dpd4_req_wait;
-
-	/* Specifies the value for PMC_REG_SHORT */
-	u32 pmc_reg_short;
-	/* Specifies the value for PMC_NO_IOPOWER */
-	u32 pmc_no_io_power;
-
-	u32 pmc_ddr_ctrl_wait;
-	u32 pmc_ddr_ctrl;
-
-	/* Specifies the value for EMC_ACPD_CONTROL */
-	u32 emc_acpd_control;
-
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
-	u32 emc_swizzle_rank0_byte0;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
-	u32 emc_swizzle_rank0_byte1;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
-	u32 emc_swizzle_rank0_byte2;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
-	u32 emc_swizzle_rank0_byte3;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
-	u32 emc_swizzle_rank1_byte0;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
-	u32 emc_swizzle_rank1_byte1;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
-	u32 emc_swizzle_rank1_byte2;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
-	u32 emc_swizzle_rank1_byte3;
-
-	/* Specifies the value for EMC_TXDSRVTTGEN */
-	u32 emc_txdsrvttgen;
-
-	/* Specifies the value for EMC_DATA_BRLSHFT_0 */
-	u32 emc_data_brlshft0;
-	u32 emc_data_brlshft1;
-
-	u32 emc_dqs_brlshft0;
-	u32 emc_dqs_brlshft1;
-
-	u32 emc_cmd_brlshft0;
-	u32 emc_cmd_brlshft1;
-	u32 emc_cmd_brlshft2;
-	u32 emc_cmd_brlshft3;
-
-	u32 emc_quse_brlshft0;
-	u32 emc_quse_brlshft1;
-	u32 emc_quse_brlshft2;
-	u32 emc_quse_brlshft3;
-
-	u32 emc_dll_cfg0;
-	u32 emc_dll_cfg1;
-
-	u32 emc_pmc_scratch1;
-	u32 emc_pmc_scratch2;
-	u32 emc_pmc_scratch3;
-
-	u32 emc_pmacro_pad_cfg_ctrl;
-
-	u32 emc_pmacro_vttgen_ctrl0;
-	u32 emc_pmacro_vttgen_ctrl1;
-	u32 emc_pmacro_vttgen_ctrl2;
-	u32 emc_pmacro_dsr_vttgen_ctrl0;
-	u32 emc_pmacro_brick_ctrl_rfu1;
-	u32 emc_pmacro_cmd_brick_ctrl_fdpd;
-	u32 emc_pmacro_brick_ctrl_rfu2;
-	u32 emc_pmacro_data_brick_ctrl_fdpd;
-	u32 emc_pmacro_bg_bias_ctrl0;
-	u32 emc_pmacro_data_pad_rx_ctrl;
-	u32 emc_pmacro_cmd_pad_rx_ctrl;
-	u32 emc_pmacro_data_rx_term_mode;
-	u32 emc_pmacro_cmd_rx_term_mode;
-	u32 emc_pmacro_data_pad_tx_ctrl;
-	u32 emc_pmacro_cmd_pad_tx_ctrl;
-	u32 emc_cfg3;
-
-	u32 emc_pmacro_tx_pwrd0;
-	u32 emc_pmacro_tx_pwrd1;
-	u32 emc_pmacro_tx_pwrd2;
-	u32 emc_pmacro_tx_pwrd3;
-	u32 emc_pmacro_tx_pwrd4;
-	u32 emc_pmacro_tx_pwrd5;
-
-	u32 emc_config_sample_delay;
-
-	u32 emc_pmacro_brick_mapping0;
-	u32 emc_pmacro_brick_mapping1;
-	u32 emc_pmacro_brick_mapping2;
-
-	u32 emc_pmacro_tx_sel_clk_src0;
-	u32 emc_pmacro_tx_sel_clk_src1;
-	u32 emc_pmacro_tx_sel_clk_src2;
-	u32 emc_pmacro_tx_sel_clk_src3;
-	u32 emc_pmacro_tx_sel_clk_src4;
-	u32 emc_pmacro_tx_sel_clk_src5;
-
-	u32 emc_pmacro_perbit_fgcg_ctrl0;
-	u32 emc_pmacro_perbit_fgcg_ctrl1;
-	u32 emc_pmacro_perbit_fgcg_ctrl2;
-	u32 emc_pmacro_perbit_fgcg_ctrl3;
-	u32 emc_pmacro_perbit_fgcg_ctrl4;
-	u32 emc_pmacro_perbit_fgcg_ctrl5;
-	u32 emc_pmacro_perbit_rfu_ctrl0;
-	u32 emc_pmacro_perbit_rfu_ctrl1;
-	u32 emc_pmacro_perbit_rfu_ctrl2;
-	u32 emc_pmacro_perbit_rfu_ctrl3;
-	u32 emc_pmacro_perbit_rfu_ctrl4;
-	u32 emc_pmacro_perbit_rfu_ctrl5;
-	u32 emc_pmacro_perbit_rfu1_ctrl0;
-	u32 emc_pmacro_perbit_rfu1_ctrl1;
-	u32 emc_pmacro_perbit_rfu1_ctrl2;
-	u32 emc_pmacro_perbit_rfu1_ctrl3;
-	u32 emc_pmacro_perbit_rfu1_ctrl4;
-	u32 emc_pmacro_perbit_rfu1_ctrl5;
-
-	u32 emc_pmacro_data_pi_ctrl;
-	u32 emc_pmacro_cmd_pi_ctrl;
-
-	u32 emc_pmacro_ddll_bypass;
-
-	u32 emc_pmacro_ddll_pwrd0;
-	u32 emc_pmacro_ddll_pwrd1;
-	u32 emc_pmacro_ddll_pwrd2;
-
-	u32 emc_pmacro_cmd_ctrl0;
-	u32 emc_pmacro_cmd_ctrl1;
-	u32 emc_pmacro_cmd_ctrl2;
-
-	/* DRAM size information */
-
-	/* Specifies the value for MC_EMEM_ADR_CFG */
-	u32 mc_emem_adr_cfg;
-	/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
-	u32 mc_emem_adr_cfg_dev0;
-	/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
-	u32 mc_emem_adr_cfg_dev1;
-
-	u32 mc_emem_adr_cfg_channel_mask;
-
-	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
-	u32 mc_emem_adr_cfg_bank_mask0;
-	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
-	u32 mc_emem_adr_cfg_bank_mask1;
-	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
-	u32 mc_emem_adr_cfg_bank_mask2;
-
-	/*
-	 * Specifies the value for MC_EMEM_CFG which holds the external memory
-	 * size (in KBytes)
-	 */
-	u32 mc_emem_cfg;
-
-	/* MC arbitration configuration */
-
-	/* Specifies the value for MC_EMEM_ARB_CFG */
-	u32 mc_emem_arb_cfg;
-	/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
-	u32 mc_emem_arb_outstanding_req;
-
-	u32 emc_emem_arb_refpb_hp_ctrl;
-	u32 emc_emem_arb_refpb_bank_ctrl;
-
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
-	u32 mc_emem_arb_timing_rcd;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
-	u32 mc_emem_arb_timing_rp;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
-	u32 mc_emem_arb_timing_rc;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
-	u32 mc_emem_arb_timing_ras;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
-	u32 mc_emem_arb_timing_faw;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
-	u32 mc_emem_arb_timing_rrd;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
-	u32 mc_emem_arb_timing_rap2pre;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
-	u32 mc_emem_arb_timing_wap2pre;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
-	u32 mc_emem_arb_timing_r2r;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
-	u32 mc_emem_arb_timing_w2w;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
-	u32 mc_emem_arb_timing_r2w;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
-	u32 mc_emem_arb_timing_w2r;
-
-	u32 mc_emem_arb_timing_rfcpb;
-
-	/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
-	u32 mc_emem_arb_da_turns;
-	/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
-	u32 mc_emem_arb_da_covers;
-	/* Specifies the value for MC_EMEM_ARB_MISC0 */
-	u32 mc_emem_arb_misc0;
-	/* Specifies the value for MC_EMEM_ARB_MISC1 */
-	u32 mc_emem_arb_misc1;
-	u32 mc_emem_arb_misc2;
-
-	/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
-	u32 mc_emem_arb_ring1_throttle;
-	/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
-	u32 mc_emem_arb_override;
-	/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
-	u32 mc_emem_arb_override1;
-	/* Specifies the value for MC_EMEM_ARB_RSV */
-	u32 mc_emem_arb_rsv;
-
-	u32 mc_da_cfg0;
-	u32 mc_emem_arb_timing_ccdmw;
-
-	/* Specifies the value for MC_CLKEN_OVERRIDE */
-	u32 mc_clken_override;
-
-	/* Specifies the value for MC_STAT_CONTROL */
-	u32 mc_stat_control;
-	/* Specifies the value for MC_VIDEO_PROTECT_BOM */
-	u32 mc_video_protect_bom;
-	/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
-	u32 mc_video_protect_bom_adr_hi;
-	/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
-	u32 mc_video_protect_size_mb;
-	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
-	u32 mc_video_protect_vpr_override;
-	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
-	u32 mc_video_protect_vpr_override1;
-	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
-	u32 mc_video_protect_gpu_override0;
-	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
-	u32 mc_video_protect_gpu_override1;
-	/* Specifies the value for MC_SEC_CARVEOUT_BOM */
-	u32 mc_sec_carveout_bom;
-	/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
-	u32 mc_sec_carveout_adr_hi;
-	/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
-	u32 mc_sec_carveout_size_mb;
-	/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */
-	u32 mc_video_protect_write_access;
-	/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */
-	u32 mc_sec_carveout_protect_write_access;
-
-	u32 mc_generalized_carveout1_bom;
-	u32 mc_generalized_carveout1_bom_hi;
-	u32 mc_generalized_carveout1_size_128kb;
-	u32 mc_generalized_carveout1_access0;
-	u32 mc_generalized_carveout1_access1;
-	u32 mc_generalized_carveout1_access2;
-	u32 mc_generalized_carveout1_access3;
-	u32 mc_generalized_carveout1_access4;
-	u32 mc_generalized_carveout1_force_internal_access0;
-	u32 mc_generalized_carveout1_force_internal_access1;
-	u32 mc_generalized_carveout1_force_internal_access2;
-	u32 mc_generalized_carveout1_force_internal_access3;
-	u32 mc_generalized_carveout1_force_internal_access4;
-	u32 mc_generalized_carveout1_cfg0;
-
-	u32 mc_generalized_carveout2_bom;
-	u32 mc_generalized_carveout2_bom_hi;
-	u32 mc_generalized_carveout2_size_128kb;
-	u32 mc_generalized_carveout2_access0;
-	u32 mc_generalized_carveout2_access1;
-	u32 mc_generalized_carveout2_access2;
-	u32 mc_generalized_carveout2_access3;
-	u32 mc_generalized_carveout2_access4;
-	u32 mc_generalized_carveout2_force_internal_access0;
-	u32 mc_generalized_carveout2_force_internal_access1;
-	u32 mc_generalized_carveout2_force_internal_access2;
-	u32 mc_generalized_carveout2_force_internal_access3;
-	u32 mc_generalized_carveout2_force_internal_access4;
-	u32 mc_generalized_carveout2_cfg0;
-
-	u32 mc_generalized_carveout3_bom;
-	u32 mc_generalized_carveout3_bom_hi;
-	u32 mc_generalized_carveout3_size_128kb;
-	u32 mc_generalized_carveout3_access0;
-	u32 mc_generalized_carveout3_access1;
-	u32 mc_generalized_carveout3_access2;
-	u32 mc_generalized_carveout3_access3;
-	u32 mc_generalized_carveout3_access4;
-	u32 mc_generalized_carveout3_force_internal_access0;
-	u32 mc_generalized_carveout3_force_internal_access1;
-	u32 mc_generalized_carveout3_force_internal_access2;
-	u32 mc_generalized_carveout3_force_internal_access3;
-	u32 mc_generalized_carveout3_force_internal_access4;
-	u32 mc_generalized_carveout3_cfg0;
-
-	u32 mc_generalized_carveout4_bom;
-	u32 mc_generalized_carveout4_bom_hi;
-	u32 mc_generalized_carveout4_size_128kb;
-	u32 mc_generalized_carveout4_access0;
-	u32 mc_generalized_carveout4_access1;
-	u32 mc_generalized_carveout4_access2;
-	u32 mc_generalized_carveout4_access3;
-	u32 mc_generalized_carveout4_access4;
-	u32 mc_generalized_carveout4_force_internal_access0;
-	u32 mc_generalized_carveout4_force_internal_access1;
-	u32 mc_generalized_carveout4_force_internal_access2;
-	u32 mc_generalized_carveout4_force_internal_access3;
-	u32 mc_generalized_carveout4_force_internal_access4;
-	u32 mc_generalized_carveout4_cfg0;
-
-	u32 mc_generalized_carveout5_bom;
-	u32 mc_generalized_carveout5_bom_hi;
-	u32 mc_generalized_carveout5_size_128kb;
-	u32 mc_generalized_carveout5_access0;
-	u32 mc_generalized_carveout5_access1;
-	u32 mc_generalized_carveout5_access2;
-	u32 mc_generalized_carveout5_access3;
-	u32 mc_generalized_carveout5_access4;
-	u32 mc_generalized_carveout5_force_internal_access0;
-	u32 mc_generalized_carveout5_force_internal_access1;
-	u32 mc_generalized_carveout5_force_internal_access2;
-	u32 mc_generalized_carveout5_force_internal_access3;
-	u32 mc_generalized_carveout5_force_internal_access4;
-	u32 mc_generalized_carveout5_cfg0;
-
-	/* Specifies enable for CA training */
-	u32 emc_ca_training_enable;
-	/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
-	u32 swizzle_rank_byte_encode;
-	/* Specifies enable and offset for patched boot rom write */
-	u32 boot_rom_patch_control;
-	/* Specifies data for patched boot rom write */
-	u32 boot_rom_patch_data;
-
-	/* Specifies the value for MC_MTS_CARVEOUT_BOM */
-	u32 mc_mts_carveout_bom;
-	/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
-	u32 mc_mts_carveout_adr_hi;
-	/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
-	u32 mc_mts_carveout_size_mb;
-	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
-	u32 mc_mts_carveout_reg_ctrl;
-
-	u32 mc_untranslated_region_check;
-
-	/* Just a place holder for special usage when there is no BCT for certain registers */
-	u32 bct_na;
-};
-
-#endif
--- a/bdk/mem/sdram_param_t210b01.h
+++ b/bdk/mem/sdram_param_t210b01.h
@ -225,7 +225,6 @@ typedef struct _sdram_params_t210b01_t
 	u32 emc_r2p;
 	/* Specifies the value for EMC_W2P */
 	u32 emc_w2p;
-	/* Specifies the value for EMC_RD_RCD */

 	u32 emc_tppd;
 	u32 emc_trtm;
@ -235,6 +234,7 @@ typedef struct _sdram_params_t210b01_t
 	u32 emc_tr2ref;
 	u32 emc_ccdmw;

+	/* Specifies the value for EMC_RD_RCD */
 	u32 emc_rd_rcd;
 	/* Specifies the value for EMC_WR_RCD */
 	u32 emc_wr_rcd;
--- a/bdk/power/max7762x.c
+++ b/bdk/power/max7762x.c
@ -75,7 +75,7 @@ typedef struct _max77620_regulator_t

 static const max77620_regulator_t _pmic_regulators[] = {
 	{  "sd0",  12500, 600000,  625000, 1400000,  REGULATOR_SD,  MAX77620_REG_SD0,      MAX77620_REG_SD0_CFG,    MAX77620_SD0_VOLT_MASK,  {{ MAX77620_REG_FPS_SD0,  1, 7, 1 }} },
-	{  "sd1",  12500, 600000, 1125000, 1175000,  REGULATOR_SD,  MAX77620_REG_SD1,      MAX77620_REG_SD1_CFG,    MAX77620_SD1_VOLT_MASK,  {{ MAX77620_REG_FPS_SD1,  0, 1, 5 }} },
+	{  "sd1",  12500, 600000, 1125000, 1237500,  REGULATOR_SD,  MAX77620_REG_SD1,      MAX77620_REG_SD1_CFG,    MAX77620_SD1_VOLT_MASK,  {{ MAX77620_REG_FPS_SD1,  0, 1, 5 }} },
 	{  "sd2",  12500, 600000, 1325000, 1350000,  REGULATOR_SD,  MAX77620_REG_SD2,      MAX77620_REG_SD2_CFG,    MAX77620_SDX_VOLT_MASK,  {{ MAX77620_REG_FPS_SD2,  1, 5, 2 }} },
 	{  "sd3",  12500, 600000, 1800000, 1800000,  REGULATOR_SD,  MAX77620_REG_SD3,      MAX77620_REG_SD3_CFG,    MAX77620_SDX_VOLT_MASK,  {{ MAX77620_REG_FPS_SD3,  0, 3, 3 }} },
 	{ "ldo0",  25000, 800000, 1200000, 1200000,  REGULATOR_LDO, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO0, 3, 7, 0 }} },
--- a/bdk/sec/se.c
+++ b/bdk/sec/se.c
@ -281,6 +281,14 @@ void se_aes_iv_clear(u32 ks)
 	}
 }

+void se_aes_iv_updated_clear(u32 ks)
+{
+	for (u32 i = 0; i < (SE_AES_IV_SIZE / 4); i++)
+	{
+		SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_QUAD(UPDATED_IV) | SE_KEYTABLE_PKT(i);
+		SE(SE_CRYPTO_KEYTABLE_DATA_REG) = 0;
+	}
+}

 int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input)
 {
@ -292,6 +300,26 @@ int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input)
 	return _se_execute_oneshot(SE_OP_START, NULL, 0, input, SE_KEY_128_SIZE);
 }

+int se_aes_crypt_hash(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size)
+{
+	if (enc)
+	{
+		SE(SE_CONFIG_REG)        = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
+		SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks)          | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) |
+								   SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_XOR_POS(XOR_TOP) |
+								   SE_CRYPTO_HASH(HASH_ENABLE);
+	}
+	else
+	{
+		SE(SE_CONFIG_REG)        = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
+		SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks)          | SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVMEM) |
+								   SE_CRYPTO_CORE_SEL(CORE_DECRYPT) | SE_CRYPTO_XOR_POS(XOR_BOTTOM) |
+								   SE_CRYPTO_HASH(HASH_ENABLE);
+	}
+	SE(SE_CRYPTO_BLOCK_COUNT_REG) = (src_size >> 4) - 1;
+	return _se_execute_oneshot(SE_OP_START, dst, dst_size, src, src_size);
+}
+
 int se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size)
 {
 	if (enc)
@ -459,6 +487,23 @@ int se_aes_xts_crypt(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst, vo
 	return 1;
 }

+static void se_calc_sha256_get_hash(void *hash, u32 *msg_left)
+{
+	u32 hash32[SE_SHA_256_SIZE / 4];
+
+	// Backup message left.
+	if (msg_left)
+	{
+		msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG);
+		msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG);
+	}
+
+	// Copy output hash.
+	for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++)
+		hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG + (i * 4)));
+	memcpy(hash, hash32, SE_SHA_256_SIZE);
+}
+
 int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64 total_size, u32 sha_cfg, bool is_oneshot)
 {
 	int res;
@ -468,6 +513,17 @@ int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64
 	if (src_size > 0xFFFFFF || !hash) // Max 16MB - 1 chunks and aligned x4 hash buffer.
 		return 0;

+	// Src size of 0 is not supported, so return null string sha256.
+	// if (!src_size)
+	// {
+	// 	const u8 null_hash[SE_SHA_256_SIZE] = {
+	// 		0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14, 0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
+	// 		0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C, 0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55
+	// 	};
+	// 	memcpy(hash, null_hash, SE_SHA_256_SIZE);
+	// 	return 1;
+	// }
+
 	// Setup config for SHA256.
 	SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_SHA256) | SE_CONFIG_ENC_ALG(ALG_SHA) | SE_CONFIG_DST(DST_HASHREG);
 	SE(SE_SHA_CONFIG_REG) = sha_cfg;
@ -506,19 +562,7 @@ int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64
 	res = _se_execute(SE_OP_START, NULL, 0, src, src_size, is_oneshot);

 	if (is_oneshot)
-	{
-		// Backup message left.
-		if (msg_left)
-		{
-			msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG);
-			msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG);
-		}
-
-		// Copy output hash.
-		for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++)
-			hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG + (i * 4)));
-		memcpy(hash, hash32, SE_SHA_256_SIZE);
-	}
+		se_calc_sha256_get_hash(hash, msg_left);

 	return res;
 }
@ -530,20 +574,9 @@ int se_calc_sha256_oneshot(void *hash, const void *src, u32 src_size)

 int se_calc_sha256_finalize(void *hash, u32 *msg_left)
 {
-	u32 hash32[SE_SHA_256_SIZE / 4];
 	int res = _se_execute_finalize();

-	// Backup message left.
-	if (msg_left)
-	{
-		msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG);
-		msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG);
-	}
-
-	// Copy output hash.
-	for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++)
-		hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG + (i * 4)));
-	memcpy(hash, hash32, SE_SHA_256_SIZE);
+	se_calc_sha256_get_hash(hash, msg_left);

 	return res;
 }
@ -620,3 +653,62 @@ void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize)
 	se_aes_crypt_cbc(3, DECRYPT, keys, SE_AES_KEYSLOT_COUNT * keysize, keys, SE_AES_KEYSLOT_COUNT * keysize);
 	se_aes_key_clear(3);
 }
+
+int se_aes_cmac_128(u32 ks, void *dst, const void *src, u32 src_size)
+{
+	int res = 0;
+	u8 *key = (u8 *)calloc(1, SE_KEY_128_SIZE);
+	u8 *last_block = (u8 *)calloc(1, SE_AES_BLOCK_SIZE);
+
+	se_aes_iv_clear(ks);
+	se_aes_iv_updated_clear(ks);
+
+	// Generate sub key
+	if (!se_aes_crypt_hash(ks, ENCRYPT, key, SE_KEY_128_SIZE, key, SE_KEY_128_SIZE))
+		goto out;
+
+	_gf256_mul_x(key);
+	if (src_size & 0xF)
+		_gf256_mul_x(key);
+
+	SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_HASHREG);
+	SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_INPUT_SEL(INPUT_MEMORY) |
+		SE_CRYPTO_XOR_POS(XOR_TOP) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) | SE_CRYPTO_HASH(HASH_ENABLE) |
+		SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
+	se_aes_iv_clear(ks);
+	se_aes_iv_updated_clear(ks);
+
+	u32 num_blocks = (src_size + 0xf) >> 4;
+	if (num_blocks > 1)
+	{
+		SE(SE_CRYPTO_BLOCK_COUNT_REG) = num_blocks - 2;
+		if (!_se_execute_oneshot(SE_OP_START, NULL, 0, src, src_size))
+			goto out;
+		SE(SE_CRYPTO_CONFIG_REG) |= SE_CRYPTO_IV_SEL(IV_UPDATED);
+	}
+
+	if (src_size & 0xf)
+	{
+		memcpy(last_block, src + (src_size & ~0xf), src_size & 0xf);
+		last_block[src_size & 0xf] = 0x80;
+	}
+	else if (src_size >= SE_AES_BLOCK_SIZE)
+	{
+		memcpy(last_block, src + src_size - SE_AES_BLOCK_SIZE, SE_AES_BLOCK_SIZE);
+	}
+
+	for (u32 i = 0; i < SE_KEY_128_SIZE; i++)
+		last_block[i] ^= key[i];
+
+	SE(SE_CRYPTO_BLOCK_COUNT_REG) = 0;
+	res = _se_execute_oneshot(SE_OP_START, NULL, 0, last_block, SE_AES_BLOCK_SIZE);
+
+	u32 *dst32 = (u32 *)dst;
+	for (u32 i = 0; i < (SE_KEY_128_SIZE / 4); i++)
+		dst32[i] = SE(SE_HASH_RESULT_REG + (i * 4));
+
+out:;
+	free(key);
+	free(last_block);
+	return res;
+}
--- a/bdk/sec/se.h
+++ b/bdk/sec/se.h
@ -30,7 +30,9 @@ void se_aes_iv_set(u32 ks, void *iv);
 void se_aes_key_get(u32 ks, void *key, u32 size);
 void se_aes_key_clear(u32 ks);
 void se_aes_iv_clear(u32 ks);
+void se_aes_iv_updated_clear(u32 ks);
 int  se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input);
+int  se_aes_crypt_hash(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
 int  se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
 int  se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
 int  se_aes_crypt_block_ecb(u32 ks, u32 enc, void *dst, const void *src);
@ -42,5 +44,6 @@ int  se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u6
 int  se_calc_sha256_oneshot(void *hash, const void *src, u32 src_size);
 int  se_calc_sha256_finalize(void *hash, u32 *msg_left);
 int  se_gen_prng128(void *dst);
+int  se_aes_cmac_128(u32 ks, void *dst, const void *src, u32 src_size);

 #endif
--- a/bdk/soc/actmon.c
+++ b/bdk/soc/actmon.c
@ -76,7 +76,9 @@
 #define ACTMON_HISTOGRAM_DATA_BASE 0x380
 #define  ACTMON_HISTOGRAM_DATA_NUM 32

-#define ACTMON_FREQ 19200000
+#define ACTMON_FREQ      19200000
+#define ACTMON_PERIOD_MS 20
+#define DEV_COUNT_WEIGHT 5

 typedef struct _actmon_dev_reg_t
 {
@ -91,11 +93,9 @@ typedef struct _actmon_dev_reg_t
 	vu32 avg_count;
 	vu32 intr_status;
 	vu32 ctrl2;
-	vu32 unk[5];
+	vu32 rsvd[5];
 } actmon_dev_reg_t;

-u32 sample_period = 0;
-
 void actmon_hist_enable(actmon_hist_src_t src)
 {
 	ACTMON(ACTMON_HISTOGRAM_CONFIG) = ACTMON_HIST_CFG_SOURCE(src) | ACTMON_HIST_CFG_ACTIVE;
@ -120,10 +120,10 @@ void actmon_dev_enable(actmon_dev_t dev)
 {
 	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));

-	regs->init_avg = 0;
-	regs->count_weight = 5;
+	regs->init_avg = ACTMON_FREQ * ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT / 100;
+	regs->count_weight = DEV_COUNT_WEIGHT;

-	regs->ctrl = ACTMON_DEV_CTRL_ENB | ACTMON_DEV_CTRL_ENB_PERIODIC;
+	regs->ctrl = ACTMON_DEV_CTRL_ENB | ACTMON_DEV_CTRL_ENB_PERIODIC | ACTMON_DEV_CTRL_K_VAL(7); // 128 samples average.
 }

 void actmon_dev_disable(actmon_dev_t dev)
@ -138,7 +138,7 @@ u32 actmon_dev_get_load(actmon_dev_t dev)
 	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));

 	// Get load-based sampling. 1 decimal point precision.
-	u32 load = regs->count / (ACTMON_FREQ / 1000);
+	u32 load = regs->count * 100 / (ACTMON_FREQ / (ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT));

 	return load;
 }
@ -148,7 +148,7 @@ u32 actmon_dev_get_load_avg(actmon_dev_t dev)
 	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));

 	// Get load-based sampling. 1 decimal point precision.
-	u32 avg_load = regs->avg_count / (ACTMON_FREQ / 1000);
+	u32 avg_load = regs->avg_count * 100 / (ACTMON_FREQ / (ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT));

 	return avg_load;
 }
@ -162,9 +162,8 @@ void actmon_init()
 {
 	clock_enable_actmon();

-	// Set period to 200ms.
-	ACTMON(ACTMON_GLB_PERIOD_CTRL) &= ~ACTMON_GLB_PERIOD_USEC;
-	ACTMON(ACTMON_GLB_PERIOD_CTRL) |= ACTMON_GLB_PERIOD_SAMPLE(200);
+	// Set period.
+	ACTMON(ACTMON_GLB_PERIOD_CTRL) = ACTMON_GLB_PERIOD_SAMPLE(ACTMON_PERIOD_MS);
 }

 void actmon_end()
--- a/bdk/soc/fuse.c
+++ b/bdk/soc/fuse.c
@ -167,11 +167,8 @@ int fuse_set_sbk()

 void fuse_wait_idle()
 {
-	u32 ctrl;
-	do
-	{
-		ctrl = FUSE(FUSE_CTRL);
-	} while (((ctrl >> 16) & 0x1f) != 4);
+	while (((FUSE(FUSE_CTRL) >> 16) & 0x1F) != FUSE_STATUS_IDLE)
+		;
 }

 u32 fuse_read(u32 addr)
--- a/bdk/soc/fuse.h
+++ b/bdk/soc/fuse.h
@ -255,11 +255,32 @@
 #define FUSE_SPARE_BIT_31                     0x3FC

 /*! Fuse commands. */
+#define FUSE_IDLE     0x0
 #define FUSE_READ     0x1
 #define FUSE_WRITE    0x2
 #define FUSE_SENSE    0x3
 #define FUSE_CMD_MASK 0x3

+/*! Fuse status. */
+#define  FUSE_STATUS_RESET                   0
+#define  FUSE_STATUS_POST_RESET              1
+#define  FUSE_STATUS_LOAD_ROW0               2
+#define  FUSE_STATUS_LOAD_ROW1               3
+#define  FUSE_STATUS_IDLE                    4
+#define  FUSE_STATUS_READ_SETUP              5
+#define  FUSE_STATUS_READ_STROBE             6
+#define  FUSE_STATUS_SAMPLE_FUSES            7
+#define  FUSE_STATUS_READ_HOLD               8
+#define  FUSE_STATUS_FUSE_SRC_SETUP          9
+#define  FUSE_STATUS_WRITE_SETUP             10
+#define  FUSE_STATUS_WRITE_ADDR_SETUP        11
+#define  FUSE_STATUS_WRITE_PROGRAM           12
+#define  FUSE_STATUS_WRITE_ADDR_HOLD         13
+#define  FUSE_STATUS_FUSE_SRC_HOLD           14
+#define  FUSE_STATUS_LOAD_RIR                15
+#define  FUSE_STATUS_READ_BEFORE_WRITE_SETUP 16
+#define  FUSE_STATUS_READ_DEASSERT_PD        17
+
 /*! Fuse cache registers. */
 #define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x))

--- a/bdk/soc/hw_init.c
+++ b/bdk/soc/hw_init.c
@ -277,12 +277,12 @@ static void _config_regulators(bool tegra_t210)
 	// Disable low battery shutdown monitor.
 	max77620_low_battery_monitor_config(false);

-	// Disable SDMMC1 IO power.
-	gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_LOW);
+	// Disable SDMMC1 IO/Core power.
 	max7762x_regulator_enable(REGULATOR_LDO2, false);
+	gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_LOW);
 	sd_power_cycle_time_start = get_tmr_ms();

-	// Disable LCD DVDD.
+	// Disable LCD DVDD to make sure it's in a reset state.
 	max7762x_regulator_enable(REGULATOR_LDO0, false);

 	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
--- a/bdk/soc/irq.h
+++ b/bdk/soc/irq.h
@ -180,6 +180,7 @@
 #define IRQ_EVENT_GPIO_A 162
 #define IRQ_EVENT_GPIO_B 163
 #define IRQ_EVENT_GPIO_C 164
+#define IRQ_EVENT_GPIO_D_T210B01 165
 #define IRQ_FLOW_RSM_CPU 168
 #define IRQ_FLOW_RSM_COP 169
 #define IRQ_TMR_SHARED 170
--- a/bdk/soc/pmc.h
+++ b/bdk/soc/pmc.h
@ -132,6 +132,9 @@
 #define  PMC_CNTRL2_SYSCLK_ORRIDE          BIT(10)
 #define  PMC_CNTRL2_HOLD_CKE_LOW_EN        BIT(12)
 #define  PMC_CNTRL2_ALLOW_PULSE_WAKE       BIT(14)
+#define APBDEV_PMC_FUSE_CONTROL      0x450
+#define  PMC_FUSE_CONTROL_PS18_LATCH_SET   BIT(8)
+#define  PMC_FUSE_CONTROL_PS18_LATCH_CLR   BIT(9)
 #define APBDEV_PMC_IO_DPD3_REQ       0x45C
 #define APBDEV_PMC_IO_DPD4_REQ       0x464
 #define APBDEV_PMC_UTMIP_PAD_CFG1    0x4C4
@ -177,6 +180,12 @@
 #define  PMC_LED_BREATHING_COUNTER_HZ               32768
 #define APBDEV_PMC_LED_BREATHING_STATUS       0xB5C
 #define  PMC_LED_BREATHING_FSM_STATUS_MASK          0x7
+#define  PMC_LED_BREATHING_FSM_STS_IDLE             0
+#define  PMC_LED_BREATHING_FSM_STS_UP_RAMP          1
+#define  PMC_LED_BREATHING_FSM_STS_PLATEAU          2
+#define  PMC_LED_BREATHING_FSM_STS_DOWN_RAMP        3
+#define  PMC_LED_BREATHING_FSM_STS_SHORT_LOW_PERIOD 4
+#define  PMC_LED_BREATHING_FSM_STS_LONG_LOW_PERIOD  5
 #define APBDEV_PMC_TZRAM_PWR_CNTRL            0xBE8
 #define  PMC_TZRAM_PWR_CNTRL_SD                     BIT(0)
 #define APBDEV_PMC_TZRAM_SEC_DISABLE          0xBEC
--- a/bdk/storage/sdmmc.c
+++ b/bdk/storage/sdmmc.c
@ -1292,21 +1292,36 @@ static int _sd_storage_set_card_bus_speed(sdmmc_storage_t *storage, u32 hs_type,
 	return 0;
 }

-static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u8 *buf)
+int sd_storage_get_fmodes(sdmmc_storage_t *storage, u8 *buf, sd_func_modes_t *fmodes)
 {
-	if (sdmmc_get_bus_width(storage->sdmmc) != SDMMC_BUS_WIDTH_4)
-		return 0;
+	if (!buf)
+		buf = (u8 *)SDMMC_UPPER_BUFFER;

 	if (!_sd_storage_switch_get(storage, buf))
 		return 0;

-	u8  access_mode = buf[13];
-	u16 power_limit = buf[7]  | (buf[6]  << 8);
+	fmodes->access_mode     = buf[13] | (buf[12] << 8);
+	fmodes->cmd_system      = buf[11] | (buf[10] << 8);
+	fmodes->driver_strength = buf[9]  | (buf[8]  << 8);
+	fmodes->power_limit     = buf[7]  | (buf[6]  << 8);
+
+	return 1;
+}
+
+static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u8 *buf)
+{
+	sd_func_modes_t fmodes;
+
+	if (sdmmc_get_bus_width(storage->sdmmc) != SDMMC_BUS_WIDTH_4)
+		return 0;
+
+	if (!sd_storage_get_fmodes(storage, buf, &fmodes))
+		return 0;
+
 #ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
-	u16 cmd_system  = buf[11] | (buf[10] << 8);
-	DPRINTF("[SD] access: %02X, power: %02X, cmd: %02X\n", access_mode, power_limit, cmd_system);
+	DPRINTF("[SD] access: %02X, power: %02X, cmd: %02X\n", fmodes.access_mode, fmodes.power_limit, fmodes.cmd_system);
 #else
-	DPRINTF("[SD] access: %02X, power: %02X\n", access_mode, power_limit);
+	DPRINTF("[SD] access: %02X, power: %02X\n", fmodes.access_mode, fmodes.power_limit);
 #endif

 	u32 hs_type = 0;
@ -1315,11 +1330,11 @@ static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u
 #ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
 	case SDHCI_TIMING_UHS_DDR200:
 		// Fall through if DDR200 is not supported.
-		if (cmd_system & SD_MODE_UHS_DDR200)
+		if (fmodes.cmd_system & SD_MODE_UHS_DDR200)
 		{
 			DPRINTF("[SD] setting bus speed to DDR200\n");
 			storage->csd.busspeed = 200;
-			_sd_storage_set_power_limit(storage, power_limit, buf);
+			_sd_storage_set_power_limit(storage, fmodes.power_limit, buf);
 			return _sd_storage_enable_DDR200(storage, buf);
 		}
 #endif
@ -1327,7 +1342,7 @@ static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u
 	case SDHCI_TIMING_UHS_SDR104:
 	case SDHCI_TIMING_UHS_SDR82:
 		// Fall through if not supported.
-		if (access_mode & SD_MODE_UHS_SDR104)
+		if (fmodes.access_mode & SD_MODE_UHS_SDR104)
 		{
 			type    = SDHCI_TIMING_UHS_SDR104;
 			hs_type = UHS_SDR104_BUS_SPEED;
@ -1345,7 +1360,7 @@ static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u
 		}

 	case SDHCI_TIMING_UHS_SDR50:
-		if (access_mode & SD_MODE_UHS_SDR50)
+		if (fmodes.access_mode & SD_MODE_UHS_SDR50)
 		{
 			type    = SDHCI_TIMING_UHS_SDR50;
 			hs_type = UHS_SDR50_BUS_SPEED;
@ -1355,7 +1370,7 @@ static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u
 		}
 /*
 	case SDHCI_TIMING_UHS_DDR50:
-		if (access_mode & SD_MODE_UHS_DDR50)
+		if (fmodes.access_mode & SD_MODE_UHS_DDR50)
 		{
 			type    = SDHCI_TIMING_UHS_DDR50;
 			hs_type = UHS_DDR50_BUS_SPEED;
@ -1365,7 +1380,7 @@ static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u
 		}
 */
 	case SDHCI_TIMING_UHS_SDR25:
-		if (access_mode & SD_MODE_UHS_SDR25)
+		if (fmodes.access_mode & SD_MODE_UHS_SDR25)
 		{
 			type = SDHCI_TIMING_UHS_SDR25;
 			hs_type = UHS_SDR25_BUS_SPEED;
@ -1382,7 +1397,7 @@ static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u

 	// Try to raise the power limit to let the card perform better.
 	if (hs_type != UHS_SDR25_BUS_SPEED)
-		_sd_storage_set_power_limit(storage, power_limit, buf);
+		_sd_storage_set_power_limit(storage, fmodes.power_limit, buf);

 	// Setup and set selected card and bus speed.
 	if (!_sd_storage_set_card_bus_speed(storage, hs_type, buf))
@ -1402,17 +1417,17 @@ static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u

 static int _sd_storage_enable_hs_high_volt(sdmmc_storage_t *storage, u8 *buf)
 {
-	if (!_sd_storage_switch_get(storage, buf))
+	sd_func_modes_t fmodes;
+
+	if (!sd_storage_get_fmodes(storage, buf, &fmodes))
 		return 0;

-	u8  access_mode = buf[13];
-	u16 power_limit = buf[7] | buf[6] << 8;
-	DPRINTF("[SD] access: %02X, power: %02X\n", access_mode, power_limit);
+	DPRINTF("[SD] access: %02X, power: %02X\n", fmodes.access_mode, fmodes.power_limit);

 	// Try to raise the power limit to let the card perform better.
-	_sd_storage_set_power_limit(storage, power_limit, buf);
+	_sd_storage_set_power_limit(storage, fmodes.power_limit, buf);

-	if (!(access_mode & SD_MODE_HIGH_SPEED))
+	if (!(fmodes.access_mode & SD_MODE_HIGH_SPEED))
 		return 1;

 	if (!_sd_storage_set_card_bus_speed(storage, HIGH_SPEED_BUS_SPEED, buf))
--- a/bdk/storage/sdmmc.h
+++ b/bdk/storage/sdmmc.h
@ -19,6 +19,7 @@
 #define _SDMMC_H_

 #include <utils/types.h>
+#include <storage/sd_def.h>
 #include <storage/sdmmc_driver.h>

 extern u32 sd_power_cycle_time_start;
@ -195,6 +196,14 @@ typedef struct _sdmmc_storage_t
 	sd_ssr_t      ssr;
 } sdmmc_storage_t;

+typedef struct _sd_func_modes_t
+{
+	u16 access_mode;
+	u16 cmd_system;
+	u16 driver_strength;
+	u16 power_limit;
+} sd_func_modes_t;
+
 int  sdmmc_storage_end(sdmmc_storage_t *storage);
 int  sdmmc_storage_read(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf);
 int  sdmmc_storage_write(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf);
@ -209,6 +218,7 @@ int  sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf);

 int  mmc_storage_get_ext_csd(sdmmc_storage_t *storage, void *buf);

+int  sd_storage_get_fmodes(sdmmc_storage_t *storage, u8 *buf, sd_func_modes_t *functions);
 int  sd_storage_get_scr(sdmmc_storage_t *storage, u8 *buf);
 int  sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf);
 u32  sd_storage_get_ssr_au(sdmmc_storage_t *storage);
--- a/bdk/usb/usb_gadget_hid.c
+++ b/bdk/usb/usb_gadget_hid.c
@ -56,16 +56,19 @@ typedef struct _gamepad_report_t

 typedef struct _jc_cal_t
 {
-	bool cl_done;
-	bool cr_done;
-	u16  clx_max;
-	u16  clx_min;
-	u16  cly_max;
-	u16  cly_min;
-	u16  crx_max;
-	u16  crx_min;
-	u16  cry_max;
-	u16  cry_min;
+// 15ms * JC_CAL_MAX_STEPS = 240 ms.
+#define JC_CAL_MAX_STEPS 16
+	u32 cl_step;
+	u32 cr_step;
+
+	u16 clx_max;
+	u16 clx_min;
+	u16 cly_max;
+	u16 cly_min;
+	u16 crx_max;
+	u16 crx_min;
+	u16 cry_max;
+	u16 cry_min;
 } jc_cal_t;

 static jc_cal_t jc_cal_ctx;
@ -74,34 +77,40 @@ static usb_ops_t usb_ops;
 static bool _jc_calibration(jc_gamepad_rpt_t *jc_pad)
 {
 	// Calibrate left stick.
-	if (!jc_cal_ctx.cl_done)
+	if (jc_cal_ctx.cl_step != JC_CAL_MAX_STEPS)
 	{
 		if (jc_pad->conn_l
 			&& jc_pad->lstick_x > 0x400 && jc_pad->lstick_y > 0x400
 			&& jc_pad->lstick_x < 0xC00 && jc_pad->lstick_y < 0xC00)
 		{
+			jc_cal_ctx.cl_step++;
 			jc_cal_ctx.clx_max = jc_pad->lstick_x + 0x72;
 			jc_cal_ctx.clx_min = jc_pad->lstick_x - 0x72;
 			jc_cal_ctx.cly_max = jc_pad->lstick_y + 0x72;
 			jc_cal_ctx.cly_min = jc_pad->lstick_y - 0x72;
-			jc_cal_ctx.cl_done = true;
+
+			if (jc_cal_ctx.cl_step != JC_CAL_MAX_STEPS)
+				return false;
 		}
 		else
 			return false;
 	}

 	// Calibrate right stick.
-	if (!jc_cal_ctx.cr_done)
+	if (jc_cal_ctx.cr_step != JC_CAL_MAX_STEPS)
 	{
 		if (jc_pad->conn_r
 			&& jc_pad->rstick_x > 0x400 && jc_pad->rstick_y > 0x400
 			&& jc_pad->rstick_x < 0xC00 && jc_pad->rstick_y < 0xC00)
 		{
+			jc_cal_ctx.cr_step++;
 			jc_cal_ctx.crx_max = jc_pad->rstick_x + 0x72;
 			jc_cal_ctx.crx_min = jc_pad->rstick_x - 0x72;
 			jc_cal_ctx.cry_max = jc_pad->rstick_y + 0x72;
 			jc_cal_ctx.cry_min = jc_pad->rstick_y - 0x72;
-			jc_cal_ctx.cr_done = true;
+
+			if (jc_cal_ctx.cr_step != JC_CAL_MAX_STEPS)
+				return false;
 		}
 		else
 			return false;
@ -122,7 +131,7 @@ static bool _jc_poll(gamepad_report_t *rpt)
 	if (jc_pad->l3 && jc_pad->home)
 		return true;

-	if (!jc_cal_ctx.cl_done || !jc_cal_ctx.cr_done)
+	if (jc_cal_ctx.cl_step != JC_CAL_MAX_STEPS || jc_cal_ctx.cr_step != JC_CAL_MAX_STEPS)
 	{
 		if (!_jc_calibration(jc_pad))
 			return false;
@ -130,9 +139,9 @@ static bool _jc_poll(gamepad_report_t *rpt)

 	// Re-calibrate on disconnection.
 	if (!jc_pad->conn_l)
-		jc_cal_ctx.cl_done = false;
+		jc_cal_ctx.cl_step = 0;
 	if (!jc_pad->conn_r)
-		jc_cal_ctx.cr_done = false;
+		jc_cal_ctx.cr_step = 0;

 	// Calculate left analog stick.
 	if (jc_pad->lstick_x <= jc_cal_ctx.clx_max && jc_pad->lstick_x >= jc_cal_ctx.clx_min)
--- a/bdk/utils/sprintf.c
+++ b/bdk/utils/sprintf.c
@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
-* Copyright (c) 2019-2022 CTCaer
+* Copyright (c) 2019-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -39,7 +39,7 @@ static void _s_putn(u32 v, int base, char fill, int fcnt)
 	static const char digits[] = "0123456789ABCDEF";

 	char *p;
-	char buf[65];
+	char buf[65]; // Number char size + leftover for padding.
 	int c = fcnt;
 	bool negative = false;

@ -93,44 +93,66 @@ void s_printf(char *out_buf, const char *fmt, ...)
 			fmt++;
 			fill = 0;
 			fcnt = 0;
+
+			// Check for padding. Number or space based.
 			if ((*fmt >= '0' && *fmt <= '9') || *fmt == ' ')
 			{
-				fcnt = *fmt;
+				fcnt = *fmt; // Padding size or padding type.
 				fmt++;
+
 				if (*fmt >= '0' && *fmt <= '9')
 				{
+					// Padding size exists. Previous char was type.
 					fill = fcnt;
 					fcnt = *fmt - '0';
 					fmt++;
+parse_padding_dec:
+					// Parse padding size extra digits.
+					if (*fmt >= '0' && *fmt <= '9')
+					{
+						fcnt = fcnt * 10 + *fmt - '0';
+						fmt++;
+						goto parse_padding_dec;
+					}
 				}
 				else
 				{
+					// No padding type, use space. (Max padding size is 9).
 					fill = ' ';
 					fcnt -= '0';
 				}
 			}
+
 			switch (*fmt)
 			{
 			case 'c':
-				_s_putc(va_arg(ap, u32));
+				char c = va_arg(ap, u32);
+				if (c != '\0')
+					_s_putc(c);
 				break;
+
 			case 's':
 				_s_puts(va_arg(ap, char *));
 				break;
+
 			case 'd':
 				_s_putn(va_arg(ap, u32), 10, fill, fcnt);
 				break;
+
 			case 'p':
 			case 'P':
 			case 'x':
 			case 'X':
 				_s_putn(va_arg(ap, u32), 16, fill, fcnt);
 				break;
+
 			case '%':
 				_s_putc('%');
 				break;
+
 			case '\0':
 				goto out;
+
 			default:
 				_s_putc('%');
 				_s_putc(*fmt);
@ -160,44 +182,66 @@ void s_vprintf(char *out_buf, const char *fmt, va_list ap)
 			fmt++;
 			fill = 0;
 			fcnt = 0;
+
+			// Check for padding. Number or space based.
 			if ((*fmt >= '0' && *fmt <= '9') || *fmt == ' ')
 			{
-				fcnt = *fmt;
+				fcnt = *fmt; // Padding size or padding type.
 				fmt++;
+
 				if (*fmt >= '0' && *fmt <= '9')
 				{
+					// Padding size exists. Previous char was type.
 					fill = fcnt;
 					fcnt = *fmt - '0';
 					fmt++;
+parse_padding_dec:
+					// Parse padding size extra digits.
+					if (*fmt >= '0' && *fmt <= '9')
+					{
+						fcnt = fcnt * 10 + *fmt - '0';
+						fmt++;
+						goto parse_padding_dec;
+					}
 				}
 				else
 				{
+					// No padding type, use space. (Max padding size is 9).
 					fill = ' ';
 					fcnt -= '0';
 				}
 			}
-			switch(*fmt)
+
+			switch (*fmt)
 			{
 			case 'c':
-				_s_putc(va_arg(ap, u32));
+				char c = va_arg(ap, u32);
+				if (c != '\0')
+					_s_putc(c);
 				break;
+
 			case 's':
 				_s_puts(va_arg(ap, char *));
 				break;
+
 			case 'd':
 				_s_putn(va_arg(ap, u32), 10, fill, fcnt);
 				break;
+
 			case 'p':
 			case 'P':
 			case 'x':
 			case 'X':
 				_s_putn(va_arg(ap, u32), 16, fill, fcnt);
 				break;
+
 			case '%':
 				_s_putc('%');
 				break;
+
 			case '\0':
 				goto out;
+
 			default:
 				_s_putc('%');
 				_s_putc(*fmt);
--- a/bdk/utils/util.c
+++ b/bdk/utils/util.c
@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
-* Copyright (c) 2018-2022 CTCaer
+* Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -102,8 +102,9 @@ u64 sqrt64(u64 num)
 	return square_root;
 }

-#define	TLONG_MAX	((long)(((unsigned long)(~0L)) >> 1))
-#define	TLONG_MIN	((long)(~TLONG_MAX))
+#define	TULONG_MAX  ((unsigned long)((unsigned long)(~0L)))
+#define	TLONG_MAX   ((long)(((unsigned long)(~0L)) >> 1))
+#define	TLONG_MIN   ((long)(~TLONG_MAX))
 #define ISSPACE(ch) ((ch >= '\t' && ch <= '\r') || (ch == ' '))
 #define ISDIGIT(ch) ( ch >= '0'  && ch <= '9' )
 #define ISALPHA(ch) ((ch >= 'a'  && ch <= 'z')  || (ch >= 'A' && ch <= 'Z'))
@ -162,7 +163,7 @@ long strtol(const char *nptr, char **endptr, register int base)
 	 * Set any if any `digits' consumed; make it negative to indicate
 	 * overflow.
 	 */
-	cutoff = neg ? -(unsigned long)TLONG_MIN : TLONG_MAX;
+	cutoff = neg ? -(unsigned long)TLONG_MIN : (base == 16 ? TULONG_MAX : TLONG_MAX);
 	cutlim = cutoff % (unsigned long)base;
 	cutoff /= (unsigned long)base;
 	for (acc = 0, any = 0;; c = *s++) {
--- a/bootloader/l4t/l4t.c
+++ b/bootloader/l4t/l4t.c
@ -1,7 +1,7 @@
 /*
 * L4T Loader for Tegra X1
 *
- * Copyright (c) 2020-2023 CTCaer
+ * Copyright (c) 2020-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -34,8 +34,8 @@
 * 2: Arachne Register Cell v1.
 * 3: Arachne Register Cell v2. PTSA Rework support.
 */
-#define L4T_LOADER_API_REV 3
-#define L4T_FIRMWARE_REV   0x33524556 // REV3.
+#define L4T_LOADER_API_REV 4
+#define L4T_FIRMWARE_REV   0x34524556 // REV4.

 #ifdef DEBUG_UART_PORT
 #include <soc/uart.h>
@ -109,13 +109,11 @@
 #define BPMPFW_B01_DTB_EMC_ENABLE_OFF        0x20
 #define BPMPFW_B01_DTB_EMC_VALUES_OFF        0x4C
 #define BPMPFW_B01_DTB_EMC_FREQ_VAL          0x8C
-#define BPMPFW_B01_DTB_EMC_SCC_OFF           0x108C
-#define BPMPFW_B01_DTB_EMC_PLLM_DIVM_VAL     0x10A4
-#define BPMPFW_B01_DTB_EMC_PLLM_DIVN_VAL     0x10A8
-#define BPMPFW_B01_DTB_EMC_PLLM_DIVP_VAL     0x10AC
+#define BPMPFW_B01_DTB_EMC_OPT_VAL           0xEDC
 #define BPMPFW_B01_DTB_EMC_TBL_START(idx)             (BPMPFW_B01_DTB_EMC_TBL_OFF + BPMPFW_B01_DTB_EMC_TBL_SZ * (idx))
 #define BPMPFW_B01_DTB_EMC_TBL_SET_VAL(idx, off, val) (*(u32 *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + (off)) = (val))
 #define BPMPFW_B01_DTB_EMC_TBL_SET_FREQ(idx, freq)    (*(u32 *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_FREQ_VAL) = (freq))
+#define BPMPFW_B01_DTB_EMC_TBL_SET_OPTC(idx, opt)     (*(u32 *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_OPT_VAL) = (opt))
 #define BPMPFW_B01_DTB_EMC_TBL_SET_NAME(idx, name)    (strcpy((char *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_NAME_VAL), (name)))
 #define BPMPFW_B01_DTB_EMC_TBL_ENABLE(idx)            (*(char *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_ENABLE_OFF) = 'n')
 #define BPMPFW_B01_DTB_EMC_TBL_OFFSET(idx)            ((void *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_VALUES_OFF))
@ -258,6 +256,7 @@ typedef struct _l4t_ctxt_t
 	int   ram_oc_freq;
 	int   ram_oc_vdd2;
 	int   ram_oc_vddq;
+	int   ram_oc_opt;

 	u32   serial_port;
 	u32   sc7entry_size;
@ -265,10 +264,11 @@ typedef struct _l4t_ctxt_t
 	emc_table_t *mtc_table;
 } l4t_ctxt_t;

-#define DRAM_VDD2_OC_MIN_VOLTAGE  1050
-#define DRAM_VDD2_OC_MAX_VOLTAGE  1175
-#define DRAM_VDDQ_OC_MIN_VOLTAGE  550
-#define DRAM_VDDQ_OC_MAX_VOLTAGE  650
+#define DRAM_VDD2_OC_MIN_VOLTAGE   1050
+#define DRAM_VDD2_OC_MAX_VOLTAGE   1175
+#define DRAM_VDD2Q_OC_MAX_VOLTAGE  1237
+#define DRAM_VDDQ_OC_MIN_VOLTAGE   550
+#define DRAM_VDDQ_OC_MAX_VOLTAGE   650
 #define DRAM_T210B01_TBL_MAX_FREQ 1600000

 //! TODO: Update on dram config changes.
@ -362,8 +362,6 @@ static void _l4t_sdram_lp0_save_params(bool t210b01)
 	} else {
 		s(MC_VIDEO_PROTECT_REG_CTRL, 1:0, secure_scratch14, 31:30);
 	}
-	s32(MC_VIDEO_PROTECT_GPU_OVERRIDE_0, secure_scratch12);
-	s(MC_VIDEO_PROTECT_GPU_OVERRIDE_1, 15:0, secure_scratch49, 15:0);

 	// TZD.
 	s(MC_SEC_CARVEOUT_BOM,     31:20, secure_scratch53, 23:12);
@ -471,14 +469,6 @@ static void _l4t_mc_config_carveout(bool t210b01)
 	// Disabled VPR carveout. DT decides if enabled or not.
 	MC(MC_VIDEO_PROTECT_BOM) = 0xFFF00000;
 	MC(MC_VIDEO_PROTECT_SIZE_MB) = 0;
-	if (!t210b01)
-	{
-		// For T210 force the following values for Falcon to configure WPR access.
-		// For T210B01 use default, already set from dram config.
-		// HOS forces 1 and 0.
-		MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 0x2A800000;
-		MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 2;
-	}
 	MC(MC_VIDEO_PROTECT_REG_CTRL) = VPR_CTRL_TZ_SECURE | VPR_CTRL_LOCKED;

 	// Temporarily disable TZDRAM carveout. For launching coldboot TZ.
@ -486,11 +476,6 @@ static void _l4t_mc_config_carveout(bool t210b01)
 	MC(MC_SEC_CARVEOUT_SIZE_MB)  = 0;
 	MC(MC_SEC_CARVEOUT_REG_CTRL) = 0;

-	// Disable MTS carveout. Only CCPLEX has access.
-	MC(MC_SEC_CARVEOUT_BOM)      = 0xFFF00000;
-	MC(MC_SEC_CARVEOUT_SIZE_MB)  = 0;
-	MC(MC_SEC_CARVEOUT_REG_CTRL) = 0;
-
 	// Print real one, not temp disabled.
 	UPRINTF("TZD: TZDRAM Carveout: %08X - %08X\n", TZDRAM_BASE, TZDRAM_BASE - 1 + TZDRAM_SIZE);

@ -657,18 +642,7 @@ static void _l4t_mc_config_carveout(bool t210b01)
 	 */
 	carveout_base -= CARVEOUT_NVDEC_TSEC_ENABLE ? ALIGN(CARVEOUT_TSEC_SIZE, SZ_1M) : 0;
 	MC(MC_SECURITY_CARVEOUT4_BOM)        = CARVEOUT_NVDEC_TSEC_ENABLE ? carveout_base : 0;
-	MC(MC_SECURITY_CARVEOUT4_BOM_HI)     = 0x0;
 	MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) = CARVEOUT_NVDEC_TSEC_ENABLE ? CARVEOUT_TSEC_SIZE / SZ_128K : 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_TSEC  | SEC_CARVEOUT_CA2_W_TSEC;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = SEC_CARVEOUT_CA4_R_TSECB | SEC_CARVEOUT_CA4_W_TSECB;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
 	MC(MC_SECURITY_CARVEOUT4_CFG0) = SEC_CARVEOUT_CFG_LOCKED         |
 									 SEC_CARVEOUT_CFG_RD_FALCON_HS   |
 									 SEC_CARVEOUT_CFG_WR_FALCON_HS   |
@ -681,18 +655,7 @@ static void _l4t_mc_config_carveout(bool t210b01)
 	// Set TSECA carveout. Only for NVDEC bl/prod and TSEC. Otherwise disabled.
 	carveout_base -= CARVEOUT_NVDEC_TSEC_ENABLE ? ALIGN(CARVEOUT_TSEC_SIZE, SZ_1M) : 0;
 	MC(MC_SECURITY_CARVEOUT5_BOM)        = CARVEOUT_NVDEC_TSEC_ENABLE ? carveout_base : 0;
-	MC(MC_SECURITY_CARVEOUT5_BOM_HI)     = 0;
 	MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) = CARVEOUT_NVDEC_TSEC_ENABLE ? CARVEOUT_TSEC_SIZE / SZ_128K : 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_TSEC  | SEC_CARVEOUT_CA2_W_TSEC;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
 	MC(MC_SECURITY_CARVEOUT5_CFG0) = SEC_CARVEOUT_CFG_LOCKED         |
 									 SEC_CARVEOUT_CFG_RD_FALCON_HS   |
 									 SEC_CARVEOUT_CFG_WR_FALCON_HS   |
@ -757,6 +720,7 @@ static void _l4t_bpmpfw_b01_config(l4t_ctxt_t *ctxt)
 {
 	char *ram_oc_txt  = ctxt->ram_oc_txt;
 	u32   ram_oc_freq = ctxt->ram_oc_freq;
+	u32   ram_oc_opt  = ctxt->ram_oc_opt;
 	u32   ram_id      = fuse_read_dramid(true);

 	// Set default parameters.
@ -815,11 +779,12 @@ static void _l4t_bpmpfw_b01_config(l4t_ctxt_t *ctxt)

 		BPMPFW_B01_DTB_EMC_TBL_SET_NAME(tbl_idx, ram_oc_txt);
 		BPMPFW_B01_DTB_EMC_TBL_SET_FREQ(tbl_idx, ram_oc_freq);
+		BPMPFW_B01_DTB_EMC_TBL_SET_OPTC(tbl_idx, ram_oc_opt);

 		// Enable table.
 		BPMPFW_B01_DTB_EMC_TBL_ENABLE(tbl_idx);

-		UPRINTF("RAM Frequency set to: %d KHz. Voltage: %d mV\n", ram_oc_freq, ram_oc_volt);
+		UPRINTF("RAM Frequency set to: %d KHz. Voltage: %d mV\n", ram_oc_freq, ctxt->ram_oc_vdd2);
 	}

 	// Save BPMP-FW entrypoint for TZ.
@ -876,7 +841,7 @@ static void _l4t_bl33_cfg_set_key(char *env, char *key, char *val)
 	strcat(env, "\n");
 }

-static void _l4t_set_config(l4t_ctxt_t *ctxt, const ini_sec_t *ini_sec, int entry_idx, int is_list)
+static void _l4t_set_config(l4t_ctxt_t *ctxt, const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b01)
 {
 	char *bl33_env = (char *)BL33_ENV_BASE;
 	bl33_env[0] = '\0';
@ -895,10 +860,13 @@ static void _l4t_set_config(l4t_ctxt_t *ctxt, const ini_sec_t *ini_sec, int entr
 		else if (!strcmp("ram_oc_vdd2", kv->key))
 		{
 			ctxt->ram_oc_vdd2 = atoi(kv->val);
-			if (ctxt->ram_oc_vdd2 > DRAM_VDD2_OC_MAX_VOLTAGE)
+
+			if (t210b01 && ctxt->ram_oc_vdd2 > DRAM_VDD2_OC_MAX_VOLTAGE)
 				ctxt->ram_oc_vdd2 = DRAM_VDD2_OC_MAX_VOLTAGE;
+			else if (!t210b01 && ctxt->ram_oc_vdd2 > DRAM_VDD2Q_OC_MAX_VOLTAGE)
+				ctxt->ram_oc_vdd2 = DRAM_VDD2Q_OC_MAX_VOLTAGE;
 			else if (ctxt->ram_oc_vdd2 < DRAM_VDD2_OC_MIN_VOLTAGE)
-				ctxt->ram_oc_vdd2 = 0;
+				ctxt->ram_oc_vdd2 = DRAM_VDD2_OC_MIN_VOLTAGE;
 		}
 		else if (!strcmp("ram_oc_vddq", kv->key))
 		{
@ -908,6 +876,8 @@ static void _l4t_set_config(l4t_ctxt_t *ctxt, const ini_sec_t *ini_sec, int entr
 			else if (ctxt->ram_oc_vddq < DRAM_VDDQ_OC_MIN_VOLTAGE)
 				ctxt->ram_oc_vddq = 0;
 		}
+		else if (!strcmp("ram_oc_opt",  kv->key))
+			ctxt->ram_oc_opt = atoi(kv->val);
 		else if (!strcmp("uart_port",   kv->key))
 			ctxt->serial_port = atoi(kv->val);

@ -958,7 +928,7 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
 	gfx_con_setpos(0, 0);

 	// Parse config.
-	_l4t_set_config(&ctxt, ini_sec, entry_idx, is_list);
+	_l4t_set_config(&ctxt, ini_sec, entry_idx, is_list, t210b01);

 	if (!ctxt.path)
 	{
@ -974,13 +944,6 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
 		return;
 	}

-	// U-BOOT does not support exfat.
-	if (sd_fs.fs_type == FS_EXFAT)
-	{
-		_l4t_crit_error("exFAT not supported", false);
-		return;
-	}
-
 	// Load BL31 (ATF/TrustZone fw).
 	if (!_l4t_sd_load(BL31_FW))
 	{
@ -1146,7 +1109,7 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
 			max7762x_regulator_set_voltage(REGULATOR_SD1, ctxt.ram_oc_vdd2 * 1000);

 		// Train the rest of the table, apply FSP WAR, set RAM to 800 MHz.
-		minerva_prep_boot_l4t(ctxt.ram_oc_freq);
+		minerva_prep_boot_l4t(ctxt.ram_oc_freq, ctxt.ram_oc_opt);

 		// Set emc table parameters and copy it.
 		int table_entries = minerva_get_mtc_table_entries();
--- a/bootloader/libs/fatfs/ffconf.h
+++ b/bootloader/libs/fatfs/ffconf.h
@ -256,7 +256,7 @@
 #define FF_FS_NORTC		1
 #define FF_NORTC_MON	1
 #define FF_NORTC_MDAY	1
-#define FF_NORTC_YEAR	2023
+#define FF_NORTC_YEAR	2024
 /* The option FF_FS_NORTC switches timestamp function. If the system does not have
 /  any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
 /  the timestamp function. Every object modified by FatFs will have a fixed timestamp
--- a/bootloader/main.c
+++ b/bootloader/main.c
@ -665,7 +665,7 @@ static void _nyx_load_run()

 		gfx_con_setpos(0, 0);
 		WPRINTF("Old Nyx GUI found! There will be dragons!\n");
-		WPRINTF("\nUpdate the bootloader folder!\n\n");
+		WPRINTF("\nUpdate bootloader folder!\n\n");
 		WPRINTF("Press any key...");

 		msleep(1000);
@ -1478,7 +1478,7 @@ ment_t ment_top[] = {
 	MDEF_END()
 };

-menu_t menu_top = { ment_top, "hekate v6.0.7", 0, 0 };
+menu_t menu_top = { ment_top, "hekate v6.1.0", 0, 0 };

 extern void pivot_stack(u32 stack_top);

--- a/modules/hekate_libsys_minerva/sys_sdrammtc.c
+++ b/modules/hekate_libsys_minerva/sys_sdrammtc.c
@ -91,9 +91,9 @@ static pllm_clk_config_t pllm_clk_config_table[] =
 	{38400, 2099200, 164, 3, 0}, // Custom. Normalized 2100 MHz.
 	{38400, 2131200, 111, 2, 0}, // JEDEC Standard. (T210B01 official max).
 	{38400, 2163200, 169, 3, 0}, // Custom. Normalized 2166 MHz.
-	{38400, 2188800,  57, 1, 0}, // Custom. Normalized 2200 MHz.
-	{38400, 2227200,  58, 1, 0}, // Custom. Normalized 2233 MHz.
-	{38400, 2265600,  59, 1, 0}, // Custom. Normalized 2266 MHz.
+	{38400, 2188800, 114, 2, 0}, // Custom. Normalized 2200 MHz.
+	{38400, 2227200, 116, 2, 0}, // Custom. Normalized 2233 MHz.
+	{38400, 2265600, 118, 2, 0}, // Custom. Normalized 2266 MHz.
 	{38400, 2291200, 179, 3, 0}, // Custom. Normalized 2300 MHz.
 	{38400, 2329600, 182, 3, 0}, // Custom. Normalized 2333 MHz.
 	{38400, 2361600, 123, 2, 0}, // Custom. Normalized 2366 MHz.
@ -1168,7 +1168,7 @@ static u32 _get_dram_temperature()
 	if (channel1_enabled)
 	{
 		_request_mmr_data(0x40040000, EMC_CHANNEL1);
-		mr4_1 = EMC(EMC_MRR);
+		mr4_1 = EMC(EMC_MRR) & 0xFFFF;

 		if (mr4_1 < 0xF001)
 			mr4_1 &= 0x7;
@ -1549,21 +1549,25 @@ static u32 _minerva_update_clock_tree_delay(emc_table_t *src_emc_entry, emc_tabl
 	if (upd_type_bits & 0x5400)
 	{
 		_request_mmr_data(0x80130000, channel1_enabled); // Dev0 MRR 19.
-		temp_ch0_0 = (EMC(EMC_MRR) & 0xFF) << 8;
-		temp_ch0_1 = EMC(EMC_MRR) & 0xFF00;
+		u32 mrr = EMC(EMC_MRR);
+		temp_ch0_0 = (mrr & 0xFF) << 8;
+		temp_ch0_1 = mrr & 0xFF00;
 		if (channel1_enabled)
 		{
-			temp_ch1_0 = (EMC_CH1(EMC_MRR) & 0xFF) << 8;
-			temp_ch1_1 = EMC_CH1(EMC_MRR) & 0xFF00;
+			mrr = EMC_CH1(EMC_MRR);
+			temp_ch1_0 = (mrr & 0xFF) << 8;
+			temp_ch1_1 = mrr & 0xFF00;
 		}

 		_request_mmr_data(0x80120000, channel1_enabled); // Dev0 MRR 18.
-		temp_ch0_0 |= EMC(EMC_MRR) & 0xFF;
-		temp_ch0_1 |= (EMC(EMC_MRR) & 0xFF00) >> 8;
+		mrr = EMC(EMC_MRR);
+		temp_ch0_0 |= mrr & 0xFF;
+		temp_ch0_1 |= (mrr & 0xFF00) >> 8;
 		if (channel1_enabled)
 		{
-			temp_ch1_0 |= EMC_CH1(EMC_MRR) & 0xFF;
-			temp_ch1_1 |= (EMC_CH1(EMC_MRR) & 0xFF00) >> 8;
+			mrr = EMC_CH1(EMC_MRR);
+			temp_ch1_0 |= mrr & 0xFF;
+			temp_ch1_1 |= (mrr & 0xFF00) >> 8;
 		}
 	}

@ -1723,21 +1727,25 @@ calc_dev2:
 	if (update_type <= PERIODIC_TRAINING_UPDATE && upd_type_bits & 0x5400)
 	{
 		_request_mmr_data(0x40130000, channel1_enabled); // Dev1 MRR 19.
-		temp_ch0_0 = (EMC(EMC_MRR) & 0xFF) << 8;
-		temp_ch0_1 = EMC(EMC_MRR) & 0xFF00;
+		u32 mrr = EMC(EMC_MRR);
+		temp_ch0_0 = (mrr& 0xFF) << 8;
+		temp_ch0_1 = mrr & 0xFF00;
 		if (channel1_enabled)
 		{
-			temp_ch1_0 = (EMC_CH1(EMC_MRR) & 0xFF) << 8;
-			temp_ch1_1 = EMC_CH1(EMC_MRR) & 0xFF00;
+			mrr = EMC_CH1(EMC_MRR);
+			temp_ch1_0 = (mrr & 0xFF) << 8;
+			temp_ch1_1 = mrr & 0xFF00;
 		}

 		_request_mmr_data(0x40120000, channel1_enabled); // Dev1 MRR 18
-		temp_ch0_0 |= EMC(EMC_MRR) & 0xFF;
-		temp_ch0_1 |= ((EMC(EMC_MRR) & 0xFF00) >> 8);
+		mrr = EMC(EMC_MRR);
+		temp_ch0_0 |= mrr & 0xFF;
+		temp_ch0_1 |= ((mrr & 0xFF00) >> 8);
 		if (channel1_enabled)
 		{
-			temp_ch1_0 |= EMC_CH1(EMC_MRR) & 0xFF;
-			temp_ch1_1 |= (EMC_CH1(EMC_MRR) & 0xFF00) >> 8;
+			mrr = EMC_CH1(EMC_MRR);
+			temp_ch1_0 |= mrr & 0xFF;
+			temp_ch1_1 |= (mrr & 0xFF00) >> 8;
 		}
 	}

@ -3280,7 +3288,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
 		if (needs_wr_training)
 			training_command |= (1 << 3);  // WR: Initiates WR Training.
 		if (needs_wr_vref_training)
-			training_command |= (1 << 6);  // WR_VREF: Initiates OB (wrire) DRAM_VREF Training.
+			training_command |= (1 << 6);  // WR_VREF: Initiates OB (write) DRAM_VREF Training.
 		if (needs_rd_training)
 			training_command |= (1 << 2);  // RD: Initiates RD Training.
 		if (needs_rd_vref_training)
@ -3614,9 +3622,9 @@ void _minerva_do_over_temp_compensation(mtc_config_t *mtc_cfg)
 	if (dram_type != DRAM_TYPE_LPDDR4)
 		return;

-	u32 dram_temp = _get_dram_temperature();
+	s32 dram_temp = _get_dram_temperature();

-	if (mtc_cfg->prev_temp == dram_temp || dram_temp == (u32)-1)
+	if (dram_temp < 0 || mtc_cfg->prev_temp == (u32)dram_temp)
 		return;

 	u32 refr = mtc_cfg->current_emc_table->burst_regs.emc_refresh;
@ -3632,7 +3640,7 @@ void _minerva_do_over_temp_compensation(mtc_config_t *mtc_cfg)
 	case 3:
 		if (mtc_cfg->prev_temp < 4)
 		{
-			mtc_cfg->prev_temp = dram_temp;
+			mtc_cfg->prev_temp = (u32)dram_temp;
 			return;
 		}
 		break;
--- a/nyx/nyx_gui/frontend/gui.c
+++ b/nyx/nyx_gui/frontend/gui.c
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2023 CTCaer
+ * Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -65,7 +65,9 @@ char *text_color;
 typedef struct _jc_lv_driver_t
 {
 	lv_indev_t *indev;
-	bool centering_done;
+// LV_INDEV_READ_PERIOD * JC_CAL_MAX_STEPS = 264 ms.
+#define JC_CAL_MAX_STEPS 8
+	u32 calibration_step;
 	u16 cx_max;
 	u16 cx_min;
 	u16 cy_max;
@ -412,7 +414,7 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data)
 	}

 	// Calibrate left stick.
-	if (!jc_drv_ctx.centering_done)
+	if (jc_drv_ctx.calibration_step != JC_CAL_MAX_STEPS)
 	{
 		if (n_cfg.jc_force_right)
 		{
@ -420,11 +422,11 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data)
 				&& jc_pad->rstick_x > 0x400 && jc_pad->rstick_y > 0x400
 				&& jc_pad->rstick_x < 0xC00 && jc_pad->rstick_y < 0xC00)
 			{
+				jc_drv_ctx.calibration_step++;
 				jc_drv_ctx.cx_max = jc_pad->rstick_x + 0x96;
 				jc_drv_ctx.cx_min = jc_pad->rstick_x - 0x96;
 				jc_drv_ctx.cy_max = jc_pad->rstick_y + 0x96;
 				jc_drv_ctx.cy_min = jc_pad->rstick_y - 0x96;
-				jc_drv_ctx.centering_done = true;
 				jc_drv_ctx.cursor_timeout = 0;
 			}
 		}
@ -432,14 +434,15 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data)
 			     && jc_pad->lstick_x > 0x400 && jc_pad->lstick_y > 0x400
 			     && jc_pad->lstick_x < 0xC00 && jc_pad->lstick_y < 0xC00)
 		{
+			jc_drv_ctx.calibration_step++;
 			jc_drv_ctx.cx_max = jc_pad->lstick_x + 0x96;
 			jc_drv_ctx.cx_min = jc_pad->lstick_x - 0x96;
 			jc_drv_ctx.cy_max = jc_pad->lstick_y + 0x96;
 			jc_drv_ctx.cy_min = jc_pad->lstick_y - 0x96;
-			jc_drv_ctx.centering_done = true;
 			jc_drv_ctx.cursor_timeout = 0;
 		}
-		else
+
+		if (jc_drv_ctx.calibration_step != JC_CAL_MAX_STEPS)
 		{
 			data->state = LV_INDEV_STATE_REL;
 			return false;
@ -447,13 +450,10 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data)
 	}

 	// Re-calibrate on disconnection.
-	if (n_cfg.jc_force_right)
-	{
-		if (!jc_pad->conn_r)
-			jc_drv_ctx.centering_done = 0;
-	}
-	else if (!jc_pad->conn_l)
-		jc_drv_ctx.centering_done = 0;
+	if (n_cfg.jc_force_right && !jc_pad->conn_r)
+		jc_drv_ctx.calibration_step = 0;
+	else if (!n_cfg.jc_force_right && !jc_pad->conn_l)
+		jc_drv_ctx.calibration_step = 0;

 	// Set button presses.
 	if (jc_pad->a || jc_pad->zl || jc_pad->zr)
@ -1330,11 +1330,13 @@ static void _update_status_bar(void *params)
 	max17050_get_property(MAX17050_VCELL, &batt_volt);
 	max17050_get_property(MAX17050_Current, &batt_curr);

-	// Enable fan if more than 46 oC.
+	// Enable fan if more than 41 oC.
 	u32 soc_temp_dec = (soc_temp >> 8);
 	if (soc_temp_dec > 51)
 		set_fan_duty(102);
 	else if (soc_temp_dec > 46)
+		set_fan_duty(76);
+	else if (soc_temp_dec > 41)
 		set_fan_duty(51);
 	else if (soc_temp_dec < 40)
 		set_fan_duty(0);
--- a/nyx/nyx_gui/frontend/gui_info.c
+++ b/nyx/nyx_gui/frontend/gui_info.c
@ -405,7 +405,7 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)

 	// Decode fuses.
 	char *sku;
-	char dram_man[32];
+	char dram_man[64];
 	char fuses_hos_version[64];
 	u8 dram_id = fuse_read_dramid(true);

@ -440,7 +440,7 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 		case LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE:
 			strcpy(dram_man, "Hynix H9HCNNNBPUMLHR-NLE 4GB");
 			break;
-		case LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT:
+		case LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WTC:
 			strcpy(dram_man, "Micron MT53B512M32D2NP-062 WT:C");
 			break;
 		case LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH:
@ -502,19 +502,15 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 		case LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE: // Replaced from Copper.
 			strcpy(dram_man, "Hynix H9HCNNNBKMMLXR-NEE 4GB");
 			break;
-
-		case LPDDR4X_UNK0_4GB_HYNIX_H9HCNNNBKMMLXR_NEI:
-		case LPDDR4X_UNK1_4GB_HYNIX_H9HCNNNBKMMLXR_NEI:
-		case LPDDR4X_UNK2_4GB_HYNIX_H9HCNNNBKMMLXR_NEI:
-			//strcpy(dram_man, "Hynix H9HCNNNBKMMLXR-NEI 4GB");
-			strcpy(dram_man, "Hynix 1a 4GB #FF8000 Contact me!#");
+		case LPDDR4X_IOWA_4GB_HYNIX_H54G46CYRBX267:
+		case LPDDR4X_HOAG_4GB_HYNIX_H54G46CYRBX267:
+		case LPDDR4X_AULA_4GB_HYNIX_H54G46CYRBX267:
+			strcpy(dram_man, "Hynix H54G46CYRBX267 4GB");
 			break;
-
-		case LPDDR4X_UNK0_4GB_MICRON_MT53E512M32D1NP_046_WTB:
-		case LPDDR4X_UNK1_4GB_MICRON_MT53E512M32D1NP_046_WTB:
-		case LPDDR4X_UNK2_4GB_MICRON_MT53E512M32D1NP_046_WTB:
-			//strcpy(dram_man, "Micron MT53E512M32D1NP-046 WT:B");
-			strcpy(dram_man, "Micron 1a 4GB #FF8000 Contact me!#");
+		case LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D1NP_046_WTB:
+		case LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D1NP_046_WTB:
+		case LPDDR4X_AULA_4GB_MICRON_MT53E512M32D1NP_046_WTB:
+			strcpy(dram_man, "Micron MT53E512M32D1NP-046 WT:B");
 			break;

 		default:
@ -616,9 +612,9 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 	// Parse fuses and display them.
 	s_printf(txt_buf,
 		"%X - %s - %s\n%02d: %s\n%d - %d (HOS: %s)\n%08X %08X %08X\n%08X%08X%08X%08X\n%08X\n%08X%08X%08X%08X\n%08X%08X%08X%08X\n%d\n"
-		"%s\n%d.%02d (0x%X)\n%d.%02d (0x%X)\n%d\n%d\n%d\n%d\n0x%X\n%d\n%d\n%d\n%d\n"
+		"%s\n%d.%02d (0x%X)\n%d.%02d (0x%X)\n%d\n%d\n%d\n%d\n0x%X\n%d\n%d (%d)\n%d (%d)\n%d (%d)\n"
 		"%d\n%d\n%d (0x%X)\n%d\n%d\n%d\n"
-		"ID: %02X, Major: A%02d, Minor: %d",
+		"ID: %02X, Major: %d, Minor: A%02d",
 		FUSE(FUSE_SKU_INFO), sku, fuse_read_hw_state() ? "Dev" : "Retail",
 		dram_id, dram_man, burnt_fuses_7, burnt_fuses_6, fuses_hos_version,
 		fuse_read_odm(4), fuse_read_odm(6), fuse_read_odm(7),
@ -635,7 +631,9 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 		(FUSE(FUSE_OPT_CP_REV)  >> 5) & 0x3F, FUSE(FUSE_OPT_CP_REV) & 0x1F, FUSE(FUSE_OPT_CP_REV),
 		FUSE(FUSE_CPU_SPEEDO_0_CALIB), FUSE(FUSE_CPU_SPEEDO_1_CALIB), FUSE(FUSE_CPU_SPEEDO_2_CALIB),
 		FUSE(FUSE_SOC_SPEEDO_0_CALIB), FUSE(FUSE_SOC_SPEEDO_1_CALIB), FUSE(FUSE_SOC_SPEEDO_2_CALIB),
-		FUSE(FUSE_CPU_IDDQ_CALIB), FUSE(FUSE_SOC_IDDQ_CALIB), FUSE(FUSE_GPU_IDDQ_CALIB),
+		FUSE(FUSE_CPU_IDDQ_CALIB), FUSE(FUSE_CPU_IDDQ_CALIB) * 4,
+		FUSE(FUSE_SOC_IDDQ_CALIB), FUSE(FUSE_SOC_IDDQ_CALIB) * 4,
+		FUSE(FUSE_GPU_IDDQ_CALIB), FUSE(FUSE_GPU_IDDQ_CALIB) * 5,
 		FUSE(FUSE_OPT_VENDOR_CODE), FUSE(FUSE_OPT_FAB_CODE), lot_bin, FUSE(FUSE_OPT_LOT_CODE_0),
 		FUSE(FUSE_OPT_WAFER_ID), FUSE(FUSE_OPT_X_COORDINATE), FUSE(FUSE_OPT_Y_COORDINATE),
 		(chip_id >> 8) & 0xFF, (chip_id >> 4) & 0xF, (chip_id >> 16) & 0xF);
@ -657,11 +655,11 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 	emc_mr_data_t ram_rev0    = sdram_read_mrx(MR6_REV_ID1);
 	emc_mr_data_t ram_rev1    = sdram_read_mrx(MR7_REV_ID2);
 	emc_mr_data_t ram_density = sdram_read_mrx(MR8_DENSITY);
-	u32 ranks = EMC(EMC_ADR_CFG) + 1;
+	u32 ranks    = EMC(EMC_ADR_CFG) + 1;
 	u32 channels = (EMC(EMC_FBIO_CFG7) >> 1) & 3;
 	channels = (channels & 1) + ((channels & 2) >> 1);
 	s_printf(txt_buf, "#00DDFF %s SDRAM ##FF8000 (Ch 0 | Ch 1):#\n#FF8000 Vendor:# ", h_cfg.t210b01 ? "LPDDR4X" : "LPDDR4");
-	switch (ram_vendor.rank0_ch0)
+	switch (ram_vendor.chip0.rank0_ch0)
 	{
 	case 1:
 		strcat(txt_buf, "Samsung");
@ -681,12 +679,24 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 	case 9:
 		strcat(txt_buf, "ESMT");
 		break;
+	case 19:
+		strcat(txt_buf, "CXMT");
+		break;
 	case 26:
-		strcat(txt_buf, "Xi'an UniIC Semiconductors Co., Ltd");
+		strcat(txt_buf, "Xi'an UniIC");
+		break;
+	case 27:
+		strcat(txt_buf, "ISSI");
 		break;
 	case 28:
 		strcat(txt_buf, "JSC");
 		break;
+	case 197:
+		strcat(txt_buf, "SINKER");
+		break;
+	case 229:
+		strcat(txt_buf, "Dosilicon");
+		break;
 	case 248:
 		strcat(txt_buf, "Fidelix");
 		break;
@ -701,11 +711,11 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 		strcat(txt_buf, "Micron");
 		break;
 	default:
-		s_printf(txt_buf + strlen(txt_buf), "#FF8000 Unknown# (%d)", ram_vendor.rank0_ch0);
+		s_printf(txt_buf + strlen(txt_buf), "#FF8000 Unknown# (%d)", ram_vendor.chip0.rank0_ch0);
 		break;
 	}
 	strcat(txt_buf, " #FF8000 |# ");
-	switch (ram_vendor.rank0_ch1)
+	switch (ram_vendor.chip1.rank0_ch0)
 	{
 	case 1:
 		strcat(txt_buf, "Samsung");
@ -717,12 +727,12 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 		strcat(txt_buf, "Micron");
 		break;
 	default:
-		s_printf(txt_buf + strlen(txt_buf), "#FF8000 Unknown# (%d)", ram_vendor.rank0_ch1);
+		s_printf(txt_buf + strlen(txt_buf), "#FF8000 Unknown# (%d)", ram_vendor.chip1.rank0_ch0);
 		break;
 	}
 	s_printf(txt_buf + strlen(txt_buf), "\n#FF8000 Rev ID:#  %X.%02X #FF8000 |# %X.%02X\n#FF8000 Density:# %d",
-		ram_rev0.rank0_ch0, ram_rev1.rank0_ch0, ram_rev0.rank0_ch1, ram_rev1.rank0_ch1, ranks * channels);
-	switch ((ram_density.rank0_ch0 & 0x3C) >> 2)
+		ram_rev0.chip0.rank0_ch0, ram_rev1.chip0.rank0_ch0, ram_rev0.chip1.rank0_ch0, ram_rev1.chip1.rank0_ch0, ranks * channels);
+	switch ((ram_density.chip0.rank0_ch0 & 0x3C) >> 2)
 	{
 	case 2:
 		strcat(txt_buf, " x 512MB");
@ -740,11 +750,11 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 		strcat(txt_buf, " x 2GB");
 		break;
 	default:
-		s_printf(txt_buf + strlen(txt_buf), " x Unk (%d)", (ram_density.rank0_ch0 & 0x3C) >> 2);
+		s_printf(txt_buf + strlen(txt_buf), " x Unk (%d)", (ram_density.chip0.rank0_ch0 & 0x3C) >> 2);
 		break;
 	}
 	s_printf(txt_buf + strlen(txt_buf), " #FF8000 |# %d", ranks * channels);
-	switch ((ram_density.rank0_ch1 & 0x3C) >> 2)
+	switch ((ram_density.chip1.rank0_ch0 & 0x3C) >> 2)
 	{
 	case 2:
 		strcat(txt_buf, " x 512MB");
@ -762,7 +772,7 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 		strcat(txt_buf, " x 2GB");
 		break;
 	default:
-		s_printf(txt_buf + strlen(txt_buf), " x Unk (%d)", (ram_density.rank0_ch1 & 0x3C) >> 2);
+		s_printf(txt_buf + strlen(txt_buf), " x Unk (%d)", (ram_density.chip1.rank0_ch0 & 0x3C) >> 2);
 		break;
 	}
 	strcat(txt_buf, "\n\n");
@ -800,6 +810,9 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 		case 0x98:
 			strcat(txt_buf, "-???");
 			break;
+		case 0x99:
+			strcat(txt_buf, "-???");
+			break;
 		default:
 			strcat(txt_buf, " #FFDD00 Contact me!#");
 			break;
@ -819,13 +832,13 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 			strcat(txt_buf, "02");
 			break;
 		case 0x96:
-			strcat(txt_buf, "XX");
+			strcat(txt_buf, "??");
 			break;
 		case 0x97:
-			strcat(txt_buf, "XX");
+			strcat(txt_buf, "??");
 			break;
 		case 0x98:
-			strcat(txt_buf, "XX");
+			strcat(txt_buf, "??");
 			break;
 		default:
 			strcat(txt_buf, " #FFDD00 Contact me!#");
@ -845,6 +858,12 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 	case PANEL_SAM_AMS699VC01:
 		strcat(txt_buf, "Samsung AMS699VC01");
 		break;
+	case PANEL_OEM_CLONE_5_5:
+		strcat(txt_buf, "#FFDD00 OEM Clone 5.5\"#");
+		break;
+	case PANEL_OEM_CLONE:
+		strcat(txt_buf, "#FFDD00 OEM Clone#");
+		break;
 	case 0xCCCC:
 		strcat(txt_buf, "#FFDD00 Failed to get info!#");
 		break;
@ -1605,7 +1624,7 @@ static lv_res_t _create_window_emmc_info_status(lv_obj_t *btn)
 	s_printf(txt_buf + strlen(txt_buf), "(%02X)\n%c%c%c%c%c%c\n%d.%d\n%04X\n%02d/%04d\n\n",
 		emmc_storage.cid.manfid,
 		emmc_storage.cid.prod_name[0], emmc_storage.cid.prod_name[1], emmc_storage.cid.prod_name[2],
-		emmc_storage.cid.prod_name[3], emmc_storage.cid.prod_name[4],	emmc_storage.cid.prod_name[5],
+		emmc_storage.cid.prod_name[3], emmc_storage.cid.prod_name[4], emmc_storage.cid.prod_name[5],
 		emmc_storage.cid.prv & 0xF, emmc_storage.cid.prv >> 4,
 		emmc_storage.cid.serial, emmc_storage.cid.month, emmc_storage.cid.year);

@ -1997,9 +2016,8 @@ static lv_res_t _create_window_sdcard_info_status(lv_obj_t *btn)
 		"Bus Width:\n"
 		"Current Rate:\n"
 		"Speed Class:\n"
-		"UHS Grade:\n"
-		"Video Class:\n"
-		"App perf class:\n"
+		"UHS Classes:\n"
+		"Max Bus Speed:\n\n"
 		"Write Protect:"
 	);
 	lv_obj_set_width(lb_desc2, lv_obj_get_width(desc2));
@ -2033,14 +2051,32 @@ static lv_res_t _create_window_sdcard_info_status(lv_obj_t *btn)
 		uhs_au_size /= 1024;
 	}

+	sd_func_modes_t fmodes = { 0 };
+	sd_storage_get_fmodes(&sd_storage, NULL, &fmodes);
+
+	char *bus_speed;
+	if      (fmodes.cmd_system & SD_MODE_UHS_DDR200)
+		bus_speed = "DDR200";
+	else if (fmodes.access_mode & SD_MODE_UHS_SDR104)
+		bus_speed = "SDR104";
+	else if (fmodes.access_mode & SD_MODE_UHS_SDR50)
+		bus_speed = "SDR50";
+	else if (fmodes.access_mode & SD_MODE_UHS_DDR50)
+		bus_speed = "DDR50";
+	else if (fmodes.access_mode & SD_MODE_UHS_SDR25)
+		bus_speed = "SDR25";
+	else
+		bus_speed = "SDR12";
+
 	s_printf(txt_buf,
-		"#00DDFF v%d.0#\n%02X\n%d MiB\n%X (CP %X)\n%d\n%d MB/s (%d MHz)\n%d (AU: %d %s\nU%d\nV%d\nA%d\n%s",
+		"#00DDFF v%d.0#\n%02X\n%d MiB\n%X (CP %X)\n%d\n%d MB/s (%d MHz)\n%d (AU: %d %s\nU%d V%d A%d\n%s\n\n%s",
 		sd_storage.csd.structure + 1, sd_storage.csd.cmdclass,
 		sd_storage.sec_cnt >> 11, sd_storage.sec_cnt, sd_storage.ssr.protected_size >> 9,
 		sd_storage.ssr.bus_width, sd_storage.csd.busspeed,
 		(sd_storage.csd.busspeed > 10) ? (sd_storage.csd.busspeed * 2) : 50,
-		sd_storage.ssr.speed_class, uhs_au_size, uhs_au_mb ? "MiB)" : "KiB)", sd_storage.ssr.uhs_grade,
-		sd_storage.ssr.video_class, sd_storage.ssr.app_class, wp_info);
+		sd_storage.ssr.speed_class, uhs_au_size, uhs_au_mb ? "MiB)" : "KiB)",
+		sd_storage.ssr.uhs_grade, sd_storage.ssr.video_class, sd_storage.ssr.app_class,
+		bus_speed, wp_info);

 	lv_label_set_text(lb_val2, txt_buf);

--- a/nyx/nyx_gui/frontend/gui_options.c
+++ b/nyx/nyx_gui/frontend/gui_options.c
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2022 CTCaer
+ * Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@ -24,9 +24,9 @@
 #include <libs/lvgl/lv_themes/lv_theme_hekate.h>
 #include <libs/lvgl/lvgl.h>

-#define CLOCK_MIN_YEAR 2023
+#define CLOCK_MIN_YEAR 2024
 #define CLOCK_MAX_YEAR (CLOCK_MIN_YEAR + 10)
-#define CLOCK_YEARLIST "2023\n2024\n2025\n2026\n2027\n2028\n2029\n2030\n2031\n2032\n2033"
+#define CLOCK_YEARLIST "2024\n2025\n2026\n2027\n2028\n2029\n2030\n2031\n2032\n2033\n2034"

 extern hekate_config h_cfg;
 extern nyx_config n_cfg;
@ -841,7 +841,7 @@ void first_time_clock_edit(void *param)
 static lv_res_t _joycon_info_dump_action(lv_obj_t * btn)
 {
 	FIL fp;
-	int error;
+	int error = 0;
 	bool is_l_hos = false;
 	bool is_r_hos = false;
 	bool nx_hoag = fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG;
@ -850,18 +850,17 @@ static lv_res_t _joycon_info_dump_action(lv_obj_t * btn)
 	char *data = (char *)malloc(SZ_16K);
 	char *txt_buf = (char *)malloc(SZ_4K);

-	if (nx_hoag)
-	{
-		error = hos_dump_cal0();
-		if (!error)
-			goto save_data;
-	}
-
-	if (!jc_pad || nx_hoag)
-	{
+	if (!nx_hoag && !jc_pad)
 		error = 255;
-		goto disabled;
-	}
+
+	if (!error)
+		error = hos_dump_cal0();
+
+	if (error)
+		goto disabled_or_cal0_issue;
+
+	if (nx_hoag)
+		goto save_data;

 	// Count valid joycon.
 	u32 joycon_found = jc_pad->bt_conn_l.type ? 1 : 0;
@ -873,18 +872,21 @@ static lv_res_t _joycon_info_dump_action(lv_obj_t * btn)
 	jc_pad->bt_conn_r.type = is_r_hos ? jc_pad->bt_conn_r.type : 0;

 save_data:
-	error = !sd_mount();
+	error = !sd_mount() ? 5 : 0;

 	if (!error)
 	{
+		nx_emmc_cal0_t *cal0 = (nx_emmc_cal0_t *)cal0_buf;
+
+		f_mkdir("switchroot");
+
 		if (!nx_hoag)
 		{
 			// Save binary dump.
 			memcpy(data, &jc_pad->bt_conn_l, sizeof(jc_bt_conn_t));
 			memcpy(data + sizeof(jc_bt_conn_t), &jc_pad->bt_conn_r, sizeof(jc_bt_conn_t));

-			f_mkdir("switchroot");
-			error = sd_save_to_file((u8 *)data, sizeof(jc_bt_conn_t) * 2, "switchroot/joycon_mac.bin");
+			error = sd_save_to_file((u8 *)data, sizeof(jc_bt_conn_t) * 2, "switchroot/joycon_mac.bin") ? 4 : 0;

 			// Save readable dump.
 			jc_bt_conn_t *bt = &jc_pad->bt_conn_l;
@ -907,38 +909,18 @@ save_data:
 				bt->ltk[8], bt->ltk[9], bt->ltk[10], bt->ltk[11], bt->ltk[12], bt->ltk[13], bt->ltk[14], bt->ltk[15]);

 			if (!error)
-				error = f_open(&fp, "switchroot/joycon_mac.ini", FA_WRITE | FA_CREATE_ALWAYS);
+				error = f_open(&fp, "switchroot/joycon_mac.ini", FA_WRITE | FA_CREATE_ALWAYS) ? 4 : 0;
 			if (!error)
 			{
 				f_puts(data, &fp);
 				f_close(&fp);
 			}
-		}
-		else
-		{
-			nx_emmc_cal0_t *cal0 = (nx_emmc_cal0_t *)cal0_buf;
-			jc_calib_t *stick_cal_l = (jc_calib_t *)cal0->analog_stick_cal_l;
-			jc_calib_t *stick_cal_r = (jc_calib_t *)cal0->analog_stick_cal_r;

 			f_mkdir("switchroot");

-			// Save Lite Gamepad Calibration data.
-			// Actual max/min are right/left and up/down offsets.
+			// Save IMU Calibration data.
 			s_printf(data,
-				"lite_cal_lx_lof=0x%X\n"
-				"lite_cal_lx_cnt=0x%X\n"
-				"lite_cal_lx_rof=0x%X\n"
-				"lite_cal_ly_dof=0x%X\n"
-				"lite_cal_ly_cnt=0x%X\n"
-				"lite_cal_ly_uof=0x%X\n\n"
-
-				"lite_cal_rx_lof=0x%X\n"
-				"lite_cal_rx_cnt=0x%X\n"
-				"lite_cal_rx_rof=0x%X\n"
-				"lite_cal_ry_dof=0x%X\n"
-				"lite_cal_ry_cnt=0x%X\n"
-				"lite_cal_ry_uof=0x%X\n\n"
-
+				"imu_type=%d\n\n"
 				"acc_cal_off_x=0x%X\n"
 				"acc_cal_off_y=0x%X\n"
 				"acc_cal_off_z=0x%X\n"
@ -954,18 +936,74 @@ save_data:
 				"gyr_cal_scl_z=0x%X\n\n"

 				"device_bt_mac=%02X:%02X:%02X:%02X:%02X:%02X\n",
-				stick_cal_l->x_min, stick_cal_l->x_center, stick_cal_l->x_max,
-				stick_cal_l->y_min, stick_cal_l->y_center, stick_cal_l->y_max,
-				stick_cal_r->x_min, stick_cal_r->x_center, stick_cal_r->x_max,
-				stick_cal_r->y_min, stick_cal_r->y_center, stick_cal_r->y_max,
+				cal0->console_6axis_sensor_type,
 				cal0->acc_offset[0],  cal0->acc_offset[1],  cal0->acc_offset[2],
 				cal0->acc_scale[0],   cal0->acc_scale[1],   cal0->acc_scale[2],
 				cal0->gyro_offset[0], cal0->gyro_offset[1], cal0->gyro_offset[2],
 				cal0->gyro_scale[0],  cal0->gyro_scale[1],  cal0->gyro_scale[2],
 				cal0->bd_mac[0], cal0->bd_mac[1], cal0->bd_mac[2], cal0->bd_mac[3], cal0->bd_mac[4], cal0->bd_mac[5]);
-
 			if (!error)
-				error = f_open(&fp, "switchroot/switch.cal", FA_WRITE | FA_CREATE_ALWAYS);
+				error = f_open(&fp, "switchroot/switch.cal", FA_WRITE | FA_CREATE_ALWAYS) ? 4 : 0;
+			if (!error)
+			{
+				f_puts(data, &fp);
+				f_close(&fp);
+			}
+		}
+		else
+		{
+			jc_calib_t *stick_cal_l = (jc_calib_t *)cal0->analog_stick_cal_l;
+			jc_calib_t *stick_cal_r = (jc_calib_t *)cal0->analog_stick_cal_r;
+
+			// Save Lite Gamepad and IMU Calibration data.
+			// Actual max/min are right/left and up/down offsets.
+			s_printf(data,
+				"lite_cal_l_type=0x%X\n"
+				"lite_cal_lx_lof=0x%X\n"
+				"lite_cal_lx_cnt=0x%X\n"
+				"lite_cal_lx_rof=0x%X\n"
+				"lite_cal_ly_dof=0x%X\n"
+				"lite_cal_ly_cnt=0x%X\n"
+				"lite_cal_ly_uof=0x%X\n\n"
+
+				"lite_cal_r_type=0x%X\n"
+				"lite_cal_rx_lof=0x%X\n"
+				"lite_cal_rx_cnt=0x%X\n"
+				"lite_cal_rx_rof=0x%X\n"
+				"lite_cal_ry_dof=0x%X\n"
+				"lite_cal_ry_cnt=0x%X\n"
+				"lite_cal_ry_uof=0x%X\n\n"
+
+				"imu_type=%d\n\n"
+				"acc_cal_off_x=0x%X\n"
+				"acc_cal_off_y=0x%X\n"
+				"acc_cal_off_z=0x%X\n"
+				"acc_cal_scl_x=0x%X\n"
+				"acc_cal_scl_y=0x%X\n"
+				"acc_cal_scl_z=0x%X\n\n"
+
+				"gyr_cal_off_x=0x%X\n"
+				"gyr_cal_off_y=0x%X\n"
+				"gyr_cal_off_z=0x%X\n"
+				"gyr_cal_scl_x=0x%X\n"
+				"gyr_cal_scl_y=0x%X\n"
+				"gyr_cal_scl_z=0x%X\n\n"
+
+				"device_bt_mac=%02X:%02X:%02X:%02X:%02X:%02X\n",
+				cal0->analog_stick_type_l,
+				stick_cal_l->x_min, stick_cal_l->x_center, stick_cal_l->x_max,
+				stick_cal_l->y_min, stick_cal_l->y_center, stick_cal_l->y_max,
+				cal0->analog_stick_type_r,
+				stick_cal_r->x_min, stick_cal_r->x_center, stick_cal_r->x_max,
+				stick_cal_r->y_min, stick_cal_r->y_center, stick_cal_r->y_max,
+				cal0->console_6axis_sensor_type,
+				cal0->acc_offset[0],  cal0->acc_offset[1],  cal0->acc_offset[2],
+				cal0->acc_scale[0],   cal0->acc_scale[1],   cal0->acc_scale[2],
+				cal0->gyro_offset[0], cal0->gyro_offset[1], cal0->gyro_offset[2],
+				cal0->gyro_scale[0],  cal0->gyro_scale[1],  cal0->gyro_scale[2],
+				cal0->bd_mac[0], cal0->bd_mac[1], cal0->bd_mac[2], cal0->bd_mac[3], cal0->bd_mac[4], cal0->bd_mac[5]);
+			if (!error)
+				error = f_open(&fp, "switchroot/switch.cal", FA_WRITE | FA_CREATE_ALWAYS) ? 4 : 0;
 			if (!error)
 			{
 				f_puts(data, &fp);
@ -976,7 +1014,7 @@ save_data:
 		sd_unmount();
 	}

-disabled:;
+disabled_or_cal0_issue:;
 	lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL);
 	lv_obj_set_style(dark_bg, &mbox_darken);
 	lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES);
@ -1042,7 +1080,7 @@ disabled:;
 		if (!nx_hoag)
 			s_printf(txt_buf, "#FFDD00 Failed to dump Joy-Con pairing info!#\n#FFDD00 Error: %d#", error);
 		else
-			s_printf(txt_buf, "#FFDD00 Failed to get Lite Gamepad info!#\n");
+			s_printf(txt_buf, "#FFDD00 Failed to get Lite Gamepad info!#\n#FFDD00 Error: %d#", error);
 	}

 	lv_mbox_set_text(mbox, txt_buf);
--- a/nyx/nyx_gui/frontend/gui_tools_partition_manager.c
+++ b/nyx/nyx_gui/frontend/gui_tools_partition_manager.c
@ -30,7 +30,7 @@
 #define SECTORS_PER_GB   0x200000

 #define HOS_MIN_SIZE_MB        2048
-#define ANDROID_SYSTEM_SIZE_MB 4096 // 4 GB which is > 3888 MB of the actual size.
+#define ANDROID_SYSTEM_SIZE_MB 6144 // 6 GB. Fits both Legacy (4912MB) and Dynamic (6144MB) partition schemes.

 extern volatile boot_cfg_t *b_cfg;
 extern volatile nyx_storage_t *nyx_str;
@ -49,6 +49,8 @@ typedef struct _partition_ctxt_t
 	bool emu_double;
 	bool emmc_is_64gb;

+	bool and_dynamic;
+
 	mbr_t mbr_old;

 	lv_obj_t *bar_hos;
@ -387,37 +389,66 @@ static void _prepare_and_flash_mbr_gpt()
 		if (part_info.l4t_size)
 			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, part_info.l4t_size << 11, (char[]) { 'l', 0, '4', 0, 't', 0 }, 6);

-		// Android Vendor partition. 1GB
-		_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x200000, (char[]) { 'v', 0, 'e', 0, 'n', 0, 'd', 0, 'o', 0, 'r', 0 }, 12);
+		if (part_info.and_dynamic)
+		{
+			// Android Linux Kernel partition. 64MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,  0x20000, (char[]) { 'b', 0, 'o', 0, 'o', 0, 't', 0 }, 8);

-		// Android System partition. 2GB.
-		_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x400000, (char[]) { 'A', 0, 'P', 0, 'P', 0 }, 6);
+			// Android Recovery partition. 64MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,  0x20000, (char[]) { 'r', 0, 'e', 0, 'c', 0, 'o', 0, 'v', 0, 'e', 0, 'r', 0, 'y', 0 }, 16);

-		// Android Linux Kernel partition. 32MB.
-		_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,  0x10000, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6);
+			// Android Device Tree Reference partition. 1MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,    0x800, (char[]) { 'd', 0, 't', 0, 'b', 0 }, 6);

-		// Android Recovery partition. 64MB.
-		_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,  0x20000, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6);
+			// Android Misc partition. 3MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,   0x1800, (char[]) { 'm', 0, 'i', 0, 's', 0, 'c', 0 }, 8);

-		// Android Device Tree Reference partition. 1MB.
-		_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,    0x800, (char[]) { 'D', 0, 'T', 0, 'B', 0 }, 6);
+			// Android Cache partition. 60MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,  0x1E000, (char[]) { 'c', 0, 'a', 0, 'c', 0, 'h', 0, 'e', 0 }, 10);

-		// Android Encryption partition. 16MB.
-		// Note: 16MB size is for aligning UDA. If any other tiny partition must be added, it should split the MDA one.
-		sdmmc_storage_write(&sd_storage, curr_part_lba, 0x8000, (void *)SDMMC_UPPER_BUFFER); // Clear the whole of it.
-		_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,   0x8000, (char[]) { 'M', 0, 'D', 0, 'A', 0 }, 6);
+			// Android Super dynamic partition. 5922MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0xB91000, (char[]) { 's', 0, 'u', 0, 'p', 0, 'e', 0, 'r', 0 }, 10);

-		// Android Cache partition. 700MB.
-		_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x15E000, (char[]) { 'C', 0, 'A', 0, 'C', 0 }, 6);
+			// Android Userdata partition.
+			u32 uda_size = (part_info.and_size << 11) - 0xC00000; // Subtract the other partitions (6144MB).
+			if (!part_info.emu_size)
+				uda_size -= 0x800; // Reserve 1MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, uda_size, (char[]) { 'u', 0, 's', 0, 'e', 0, 'r', 0, 'd', 0, 'a', 0, 't', 0, 'a', 0 }, 16);
+		}
+		else
+		{
+			// Android Vendor partition. 1GB
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x200000, (char[]) { 'v', 0, 'e', 0, 'n', 0, 'd', 0, 'o', 0, 'r', 0 }, 12);

-		// Android Misc partition. 3MB.
-		_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,   0x1800, (char[]) { 'M', 0, 'S', 0, 'C', 0 }, 6);
+			// Android System partition. 3GB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x600000, (char[]) { 'A', 0, 'P', 0, 'P', 0 }, 6);

-		// Android Userdata partition.
-		u32 uda_size = (part_info.and_size << 11) - 0x798000; // Subtract the other partitions (3888MB).
-		if (!part_info.emu_size)
-			uda_size -= 0x800; // Reserve 1MB.
-		_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, uda_size, (char[]) { 'U', 0, 'D', 0, 'A', 0 }, 6);
+			// Android Linux Kernel partition. 32MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,  0x10000, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6);
+
+			// Android Recovery partition. 64MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,  0x20000, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6);
+
+			// Android Device Tree Reference partition. 1MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,    0x800, (char[]) { 'D', 0, 'T', 0, 'B', 0 }, 6);
+
+			// Android Encryption partition. 16MB.
+			// Note: 16MB size is for aligning UDA. If any other tiny partition must be added, it should split the MDA one.
+			sdmmc_storage_write(&sd_storage, curr_part_lba, 0x8000, (void *)SDMMC_UPPER_BUFFER); // Clear the whole of it.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,   0x8000, (char[]) { 'M', 0, 'D', 0, 'A', 0 }, 6);
+
+			// Android Cache partition. 700MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x15E000, (char[]) { 'C', 0, 'A', 0, 'C', 0 }, 6);
+
+			// Android Misc partition. 3MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba,   0x1800, (char[]) { 'M', 0, 'S', 0, 'C', 0 }, 6);
+
+			// Android Userdata partition.
+			u32 uda_size = (part_info.and_size << 11) - 0x998000; // Subtract the other partitions (4912MB).
+			if (!part_info.emu_size)
+				uda_size -= 0x800; // Reserve 1MB.
+			_create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, uda_size, (char[]) { 'U', 0, 'D', 0, 'A', 0 }, 6);
+		}

 		// Handle emuMMC partitions manually.
 		if (part_info.emu_size)
@ -796,7 +827,7 @@ static bool _get_available_android_partition()
 	// Find kernel partition.
 	for (u32 i = 0; i < gpt->header.num_part_ents; i++)
 	{
-		if (gpt->entries[i].lba_start && !memcmp(gpt->entries[i].name, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6))
+		if (gpt->entries[i].lba_start && (!memcmp(gpt->entries[i].name, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6) || !memcmp(gpt->entries[i].name, (char[]) { 'b', 0, 'o', 0, 'o', 0, 't', 0 }, 8)))
 		{
 			free(gpt);

@ -1026,7 +1057,7 @@ static lv_res_t _action_flash_android_data(lv_obj_t * btns, const char * txt)
 	// Find Kernel partition.
 	for (u32 i = 0; i < gpt->header.num_part_ents; i++)
 	{
-		if (!memcmp(gpt->entries[i].name, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6))
+		if (!memcmp(gpt->entries[i].name, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6) || !memcmp(gpt->entries[i].name, (char[]) { 'b', 0, 'o', 0, 'o', 0, 't', 0 }, 8))
 		{
 			offset_sct = gpt->entries[i].lba_start;
 			size_sct = (gpt->entries[i].lba_end + 1) - gpt->entries[i].lba_start;
@ -1090,7 +1121,7 @@ boot_img_not_found:
 	// Find Recovery partition.
 	for (u32 i = 0; i < gpt->header.num_part_ents; i++)
 	{
-		if (!memcmp(gpt->entries[i].name, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6))
+		if (!memcmp(gpt->entries[i].name, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6) || !memcmp(gpt->entries[i].name, (char[]) { 'r', 0, 'e', 0, 'c', 0, 'o', 0, 'v', 0, 'e', 0, 'r', 0, 'y', 0 }, 16))
 		{
 			offset_sct = gpt->entries[i].lba_start;
 			size_sct = (gpt->entries[i].lba_end + 1) - gpt->entries[i].lba_start;
@ -1152,7 +1183,7 @@ recovery_not_found:
 	// Find Device Tree partition.
 	for (u32 i = 0; i < gpt->header.num_part_ents; i++)
 	{
-		if (!memcmp(gpt->entries[i].name, (char[]) { 'D', 0, 'T', 0, 'B', 0 }, 6))
+		if (!memcmp(gpt->entries[i].name, (char[]) { 'D', 0, 'T', 0, 'B', 0 }, 6) || !memcmp(gpt->entries[i].name, (char[]) { 'd', 0, 't', 0, 'b', 0 }, 6))
 		{
 			offset_sct = gpt->entries[i].lba_start;
 			size_sct = (gpt->entries[i].lba_end + 1) - gpt->entries[i].lba_start;
@ -1198,7 +1229,7 @@ dtb_not_found:
 	// Check if Recovery is flashed unconditionally.
 	for (u32 i = 0; i < gpt->header.num_part_ents; i++)
 	{
-		if (!memcmp(gpt->entries[i].name, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6))
+		if (!memcmp(gpt->entries[i].name, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6) || !memcmp(gpt->entries[i].name, (char[]) { 'r', 0, 'e', 0, 'c', 0, 'o', 0, 'v', 0, 'e', 0, 'r', 0, 'y', 0 }, 16))
 		{
 			u8 *buf = malloc(512);
 			sdmmc_storage_read(&sd_storage, gpt->entries[i].lba_start, 1, buf);
@ -1679,7 +1710,7 @@ static lv_res_t _create_mbox_partitioning_option1(lv_obj_t *btns, const char *tx
 	return LV_RES_OK;
 }

-static lv_res_t _create_mbox_partitioning_next(lv_obj_t *btn)
+static lv_res_t _create_mbox_partitioning_warn(lv_obj_t *btn)
 {
 	lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL);
 	lv_obj_set_style(dark_bg, &mbox_darken);
@ -1726,6 +1757,53 @@ static lv_res_t _create_mbox_partitioning_next(lv_obj_t *btn)
 	return LV_RES_OK;
 }

+static lv_res_t _create_mbox_partitioning_android(lv_obj_t *btns, const char *txt)
+{
+	int btn_idx = lv_btnm_get_pressed(btns);
+
+	mbox_action(btns, txt);
+
+	part_info.and_dynamic = !btn_idx;
+	_create_mbox_partitioning_warn(NULL);
+
+	return LV_RES_INV;
+}
+
+static lv_res_t _create_mbox_partitioning_andr_part(lv_obj_t *btn)
+{
+	lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL);
+	lv_obj_set_style(dark_bg, &mbox_darken);
+	lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES);
+
+	static const char *mbox_btn_map[] = { "\222Dynamic", "\222Legacy", "" };
+	lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL);
+	lv_mbox_set_recolor_text(mbox, true);
+
+	lv_obj_set_width(mbox, LV_HOR_RES / 10 * 5);
+	lv_mbox_set_text(mbox, "#FF8000 Android Partitioning#");
+
+	lv_obj_t *lbl_status = lv_label_create(mbox, NULL);
+	lv_label_set_recolor(lbl_status, true);
+
+	lv_label_set_text(lbl_status,
+		"Please select a partition scheme:\n\n"
+		"#C7EA46 Dynamic:# Android 13+\n"
+		"#C7EA46 Legacy:# Android 10-11\n");
+
+	lv_mbox_add_btns(mbox, mbox_btn_map, _create_mbox_partitioning_android);
+	lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0);
+	lv_obj_set_top(mbox, true);
+
+	return LV_RES_OK;
+}
+
+static lv_res_t _create_mbox_partitioning_next(lv_obj_t *btn) {
+	if (part_info.and_size)
+		return _create_mbox_partitioning_andr_part(NULL);
+	else
+		return _create_mbox_partitioning_warn(NULL);
+}
+
 static void _update_partition_bar()
 {
 	lv_obj_t *h1 = lv_obj_get_parent(part_info.bar_hos);
--- a/nyx/nyx_gui/libs/fatfs/ffconf.h
+++ b/nyx/nyx_gui/libs/fatfs/ffconf.h
@ -257,7 +257,7 @@
 #define FF_FS_NORTC		0
 #define FF_NORTC_MON	1
 #define FF_NORTC_MDAY	1
-#define FF_NORTC_YEAR	2023
+#define FF_NORTC_YEAR	2024
 /* The option FF_FS_NORTC switches timestamp function. If the system does not have
 /  any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
 /  the timestamp function. Every object modified by FatFs will have a fixed timestamp
Author	SHA1	Message	Date
CTCaer	29d1e4a809	Bump hekate to v6.1.0 and Nyx to v1.6.0	2024-02-22 11:45:19 +02:00
CTCaer	2ff2a5df2f	nyx: add error code info on lite gamepad dumping	2024-02-22 11:44:43 +02:00
CTCaer	4131ff12d7	bdk: sdram: adjust sdmmc1 la for l4t	2024-02-21 10:50:15 +02:00
CTCaer	5f8814311e	nyx: info: add panel clone info	2024-02-21 10:42:28 +02:00
CTCaer	9ea847578e	bdk: display: add another oem clone	2024-02-21 10:40:46 +02:00
Thomas Makin	f37ae083ae	nyx: add android dynamic partition support Will be used in Android >=13 for larger capacity and future-proofing. New full system size: 6 GiB. Partitions: - boot - recovery - dtb - misc - cache - super - userdata	2024-02-16 17:17:12 +02:00
CTCaer	feb5b11f66	minerva: do not reread mrr for channel b Just in case the mrr fifo is not empty.	2024-02-16 16:34:30 +02:00
CTCaer	e96e74c72a	nyx: finer control of fan when temp is high	2024-02-16 16:07:27 +02:00
CTCaer	6e6f5f8eed	hekate: reduce binary size By using the same message everywhere.	2024-02-16 16:05:42 +02:00
CTCaer	35c36908a1	hekate/nyx: change fs/clock year to 2024	2024-02-16 16:03:54 +02:00
CTCaer	6d69ef3cf6	bdk: sprintf: allow padding > 9	2024-02-16 16:01:54 +02:00
CTCaer	abeafb9a67	l4t: allow exFAT as boot drive Allow exFAT support of boot partition. For newer bl33 (U-Boot >= 2024-NX02). Old ones will just fail to load the boot script in such cases.	2024-02-16 15:59:30 +02:00
CTCaer	be3297ae1f	l4t: raise T210 vdd2 limit to 1237.5mV	2024-02-16 15:57:22 +02:00
CTCaer	f05563579e	bdk: max77620: raise sd1 max voltage For T210.	2024-02-16 15:55:40 +02:00
CTCaer	644747230c	bdk: dram: add FPGA code for 3rd gen micron	2024-02-16 15:54:22 +02:00
CTCaer	05f4c42a2d	l4t: add custom options That's a special flag config that controls ARC.	2024-02-16 15:53:04 +02:00
CTCaer	1f30b8deb7	bdk: minerva: add custom option in table	2024-02-16 15:51:02 +02:00
CTCaer	6c518435ec	nyx: add info about 3rd gen micron lpddr4x	2024-02-14 02:18:01 +02:00
CTCaer	25e48472c8	nyx: add info about oem 5.5" panel	2024-02-14 02:17:45 +02:00
CTCaer	bfc6069b2d	bdk: display: add OEM panel id	2024-02-14 00:08:06 +02:00
CTCaer	38a792e564	nyx: add penel rev and change some labels	2024-02-12 04:14:14 +02:00
CTCaer	8c5fdf52d4	nyx: correct dram info Parse per module info on channel A, rank 0. It was channel info on chip 0, rank0 before.	2024-02-12 04:13:39 +02:00
CTCaer	4576ed81ef	sdram: acquire per chip mrr info	2024-02-12 04:08:39 +02:00
CTCaer	e9d2bdb124	l4t: remove more redundant carveout cfg	2024-01-07 12:40:28 +02:00
CTCaer	b37430dc1d	bdk: update copyright year	2024-01-07 12:38:10 +02:00
CTCaer	75543875e2	bdk: mc: remove some redundant carveout cfg	2024-01-07 12:33:29 +02:00
CTCaer	cc50ed2051	l4t: remove redundant wpr cfg It's now done in dram cfg.	2024-01-06 22:09:18 +02:00
CTCaer	d1bae553ec	nyx: info: use the updated define for micron wtc	2024-01-06 22:06:21 +02:00
CTCaer	30c320d6e7	bdk: sdram: update all ram info comments	2024-01-06 22:05:24 +02:00
CTCaer	eff27d92f2	bdk: sdram: update default wpr overrides Since it's only used in L4T set them to the correct latest reg tool values. HOS overrides them anyway.	2024-01-06 22:03:54 +02:00
CTCaer	3874840d77	bdk: sdram: update cfg for 8GB erista	2024-01-06 21:59:18 +02:00
CTCaer	74e252aaf2	bdk: sdram: update latest reg tool vpr overrides Set them to default config and remove them from patching.	2024-01-06 21:58:51 +02:00
CTCaer	c7333e710c	bdk: strtol: support unsigned 32bit hex If base is 16 and input is not negative allow unsigned 32bit parsing. This allows parsing numbers of up to 4294967295 in that case.	2024-01-06 21:55:21 +02:00
CTCaer	dab5eb9aa0	bdk: sprintf: do not accept null chars Skip NULL chars on putc since they break the resulted string.	2024-01-06 21:52:48 +02:00
CTCaer	92093ff08e	bdk: se: deduplicate sha hash extraction	2023-12-27 21:07:52 +02:00
CTCaer	2cc6cd45d9	bdk: dram: small refactor	2023-12-27 21:06:09 +02:00
CTCaer	a6ec41744b	bdk: sdram: refactor patching offsets	2023-12-27 21:04:04 +02:00
CTCaer	bb6e4deb4c	bdk: remove unused lp0 cfg from bdk	2023-12-27 21:02:33 +02:00
CTCaer	1522f1ee92	nyx: info: add max bus speed info for sd	2023-12-27 15:02:00 +02:00
CTCaer	41d3565353	bdk: sdmmc: deduplicate function modes get And parse the whole info	2023-12-27 15:01:20 +02:00
CTCaer	e23d469f06	nyx: revamp jc/sio cal info dumping Hoag: - Add stick types - Add imu type All the rest: - Add imu calibration info - Add BT mac	2023-12-25 04:17:59 +02:00
CTCaer	bd1733c4fa	minerva: use min 2 divm Adhere to software based imposed limits for T210.	2023-12-25 04:11:55 +02:00
CTCaer	db214f2865	l4t: correct debug print	2023-12-25 04:09:46 +02:00
CTCaer	b584a3f53a	bdk: add several defines	2023-12-25 04:08:34 +02:00
CTCaer	7f98fb736a	bdk: hwinit: reorder sdmmc1 reg disable	2023-12-25 04:07:26 +02:00
CTCaer	87c50732c0	bdk: fuse: simplify idle wait	2023-12-25 03:47:26 +02:00
CTCaer	504659a39b	bdk: actmon: switch to averaged sampling	2023-12-25 03:46:05 +02:00
CTCaer	e47a819948	bdk: se: add more useful functions - aes cmac 128bit - aes hashing - option to clear updated aes iv	2023-12-25 03:44:52 +02:00
CTCaer	39abeb9a28	nyx: improve fuses info Correct the Chip ID Revision and also add actual (derived) iddq values.	2023-12-25 03:33:37 +02:00
CTCaer	80a32304cb	nyx: rename 3rd gen hynix ram chips	2023-12-25 03:21:17 +02:00
CTCaer	913cdee8e8	bdk: sdram: rename 3rd gen t210b01 hynix ram Confirmed to be a Hynix H54G46CYRBX267 and not a H9HCNNNBKMMLXR-NEI	2023-12-25 03:02:11 +02:00
CTCaer	eff55ff378	bdk: touch: rename samsung touch panel BH2109 is the board model and not the touch panel.	2023-12-25 02:41:42 +02:00
CTCaer	09dfcfc57d	bdk: display: deduplicate interrupt code	2023-12-25 02:40:38 +02:00
CTCaer	239c48c790	bdk: usb: hid: improve stick calibration Wait a bit before calibrating stick centers, in order to avoid bad values.	2023-12-25 02:37:40 +02:00
CTCaer	2e1a773a08	nyx: relax joycon calibration init Wait a bit before actually doing stick calibration in order to avoid bad values.	2023-12-25 02:36:27 +02:00