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Code Issues Projects Releases Packages Wiki Activity
1552 commits 2 branches 75 tags 6.9 MiB
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403 commits

Author SHA1 Message Date
CTCaer
9ea847578e bdk: display: add another oem clone 2024-02-21 10:40:46 +02:00
CTCaer
6d69ef3cf6 bdk: sprintf: allow padding > 9 2024-02-16 16:01:54 +02:00
CTCaer
f05563579e bdk: max77620: raise sd1 max voltage 
For T210.
 2024-02-16 15:55:40 +02:00
CTCaer
644747230c bdk: dram: add FPGA code for 3rd gen micron 2024-02-16 15:54:22 +02:00
CTCaer
1f30b8deb7 bdk: minerva: add custom option in table 2024-02-16 15:51:02 +02:00
CTCaer
bfc6069b2d bdk: display: add OEM panel id 2024-02-14 00:08:06 +02:00
CTCaer
4576ed81ef sdram: acquire per chip mrr info 2024-02-12 04:08:39 +02:00
CTCaer
b37430dc1d bdk: update copyright year 2024-01-07 12:38:10 +02:00
CTCaer
75543875e2 bdk: mc: remove some redundant carveout cfg 2024-01-07 12:33:29 +02:00
CTCaer
30c320d6e7 bdk: sdram: update all ram info comments 2024-01-06 22:05:24 +02:00
CTCaer
eff27d92f2 bdk: sdram: update default wpr overrides 
Since it's only used in L4T set them to the correct latest reg tool values.

HOS overrides them anyway.
 2024-01-06 22:03:54 +02:00
CTCaer
3874840d77 bdk: sdram: update cfg for 8GB erista 2024-01-06 21:59:18 +02:00
CTCaer
74e252aaf2 bdk: sdram: update latest reg tool vpr overrides 
Set them to default config and remove them from patching.
 2024-01-06 21:58:51 +02:00
CTCaer
c7333e710c bdk: strtol: support unsigned 32bit hex 
If base is 16 and input is not negative allow unsigned 32bit parsing.

This allows parsing numbers of up to 4294967295 in that case.
 2024-01-06 21:55:21 +02:00
CTCaer
dab5eb9aa0 bdk: sprintf: do not accept null chars 
Skip NULL chars on putc since they break the resulted string.
 2024-01-06 21:52:48 +02:00
CTCaer
92093ff08e bdk: se: deduplicate sha hash extraction 2023-12-27 21:07:52 +02:00
CTCaer
2cc6cd45d9 bdk: dram: small refactor 2023-12-27 21:06:09 +02:00
CTCaer
a6ec41744b bdk: sdram: refactor patching offsets 2023-12-27 21:04:04 +02:00
CTCaer
bb6e4deb4c bdk: remove unused lp0 cfg from bdk 2023-12-27 21:02:33 +02:00
CTCaer
41d3565353 bdk: sdmmc: deduplicate function modes get 
And parse the whole info
 2023-12-27 15:01:20 +02:00
CTCaer
b584a3f53a bdk: add several defines 2023-12-25 04:08:34 +02:00
CTCaer
7f98fb736a bdk: hwinit: reorder sdmmc1 reg disable 2023-12-25 04:07:26 +02:00
CTCaer
87c50732c0 bdk: fuse: simplify idle wait 2023-12-25 03:47:26 +02:00
CTCaer
504659a39b bdk: actmon: switch to averaged sampling 2023-12-25 03:46:05 +02:00
CTCaer
e47a819948 bdk: se: add more useful functions 
- aes cmac 128bit
- aes hashing
- option to clear updated aes iv
 2023-12-25 03:44:52 +02:00
CTCaer
913cdee8e8 bdk: sdram: rename 3rd gen t210b01 hynix ram 
Confirmed to be a Hynix H54G46CYRBX267 and not a H9HCNNNBKMMLXR-NEI
 2023-12-25 03:02:11 +02:00
CTCaer
eff55ff378 bdk: touch: rename samsung touch panel 
BH2109 is the board model and not the touch panel.
 2023-12-25 02:41:42 +02:00
CTCaer
09dfcfc57d bdk: display: deduplicate interrupt code 2023-12-25 02:40:38 +02:00
CTCaer
239c48c790 bdk: usb: hid: improve stick calibration 
Wait a bit before calibrating stick centers, in order to avoid bad values.
 2023-12-25 02:37:40 +02:00
CTCaer
ce137852b7 bdk: change some defines and comments 2023-10-12 06:59:15 +03:00
CTCaer
ce42e27f45 bdk: minerva: do not handle oc freq 
Arachne already handles it.
 2023-08-22 16:44:41 +03:00
CTCaer
d73a3fdd7c bdk: sdram: name 1a micron ram chips 
Again, as with 3rd gen samsung and hynix, that's an educated guess.
 2023-08-22 14:44:27 +03:00
CTCaer
fdf0dcc636 bdk: joycon: add info about sio imu report 2023-08-22 14:36:23 +03:00
CTCaer
f2bdc3f47c bdk: i2c: fix stack buffer overflow 2023-08-07 21:02:20 +03:00
CTCaer
1cc97ebc51 bdk: update various comments 2023-07-31 17:03:15 +03:00
CTCaer
1e28320e5a bdk: t210: add more mmio addresses 
And simplify relevant drivers that hardcoded them.
 2023-07-31 16:59:15 +03:00
CTCaer
f291a5cfa7 bdk: max17050: add reg dumping 2023-07-28 03:34:11 +03:00
CTCaer
9187fa7a8c bdk: fuse: add all t210b01 fuses 
And use B01 to distinguish the ones only on that SoC.
 2023-07-22 07:10:12 +03:00
CTCaer
b9bc35a22e bdk: dram: correct old comments 2023-07-21 18:39:46 +03:00
CTCaer
d7ad9b874b bdk: use the typedefs on jc calib 2023-06-11 13:27:48 +03:00
CTCaer
820e6d5a6e bdk: update cal0 struct 2023-06-10 23:48:45 +03:00
CTCaer
93ed4d0899 bdk: emc: add temp and feature reporting defines 2023-06-09 10:38:24 +03:00
CTCaer
01afd2de56 bdk: sdmmc: properly report comp pad status 
The reporting of the resistor being shorted or open was swapped. Fix that so it's immediately known what's the issue.
 2023-06-09 10:37:47 +03:00
CTCaer
d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer
b674624ad0 bdk: timer: add instruction sleep 
usage:
`isleep(ILOOP(instructions))`

Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
 2023-06-09 10:33:11 +03:00
CTCaer
191a0533d9 bdk: clock: add more known pto ids 2023-06-09 10:29:47 +03:00
CTCaer
8502731fbd bdk: tsec: refactor some register names 2023-06-09 10:28:28 +03:00
CTCaer
18f3a1b70c bdk: max77620: reduce max DRAM VDDIO/Q 
Reduce allowed VDDIO/VDDQfor T210B01 and VDDIO for T210B01.
 2023-06-09 10:24:55 +03:00
CTCaer
c2ee6be2f5 bdk: sdram: add Samsung 8GB RAM support for T210 
And remove Copper support completely.
 2023-06-08 04:16:51 +03:00
CTCaer
73a133556d bdk: sdram: correct sku related info 
Validated so rename accordingly.
 2023-06-08 02:57:30 +03:00