Commit graph

8 commits

Author SHA1 Message Date
CTCaer 9c1238f99d Update Warnings flags in makefiles 2022-10-11 07:25:21 +03:00
CTCaer 46fa330bdd Add proper make prints for modules 2020-07-18 01:36:16 +03:00
CTCaer 6e256d29c7 Utilize hekate's BDK for hekate main and Nyx 2020-06-14 16:45:45 +03:00
CTCaer 27926b0d55 Allow automatic inlining for modules 2020-06-13 18:40:09 +03:00
CTCaer 8ce6bf82a9 Minimize make info noise during building 2020-06-13 18:39:17 +03:00
CTCaer a52af1bf41 Fix building on make 4.3 2020-03-04 01:34:35 +02:00
Kostas Missos 7c42f72b8a refactor: Remove all unwanted whitespace 2019-10-18 18:02:06 +03:00
Kostas Missos cae9044c17 Minerva our DRAM trainer
Supports up to 1600MHz and periodic training.

For more check here: https://github.com/CTCaer/minerva_tc
2018-11-04 03:15:32 +02:00