From fdd94ffd2b190962571bcbdc0928f75dbb088304 Mon Sep 17 00:00:00 2001 From: Kostas Missos Date: Tue, 18 Sep 2018 23:38:54 +0300 Subject: [PATCH] General bugfixes + hardcoded name replacement --- bootloader/config/config.c | 10 +++--- bootloader/config/ini.c | 3 +- bootloader/gfx/di.c | 4 +-- bootloader/gfx/gfx.c | 11 ++---- bootloader/gfx/tui.c | 6 ++-- bootloader/hos/hos.c | 4 +-- bootloader/ianos/ianos.c | 7 +++- bootloader/main.c | 70 ++++++++++++++++++++----------------- bootloader/mem/heap.c | 2 +- bootloader/mem/sdram.c | 4 +-- bootloader/power/max77620.h | 2 ++ bootloader/power/max7762x.c | 21 +++++------ bootloader/power/max7762x.h | 45 ++++++++++++++++++++++++ bootloader/sec/se.c | 2 ++ bootloader/soc/clock.c | 20 +++++++++-- bootloader/soc/clock.h | 8 ++++- bootloader/soc/cluster.c | 27 +++++++------- bootloader/soc/i2c.c | 38 ++++++++++---------- bootloader/soc/i2c.h | 11 ++++++ bootloader/soc/t210.h | 9 +++-- bootloader/utils/btn.c | 3 +- 21 files changed, 200 insertions(+), 107 deletions(-) diff --git a/bootloader/config/config.c b/bootloader/config/config.c index 9ae7cdd..1ac16be 100644 --- a/bootloader/config/config.c +++ b/bootloader/config/config.c @@ -173,7 +173,7 @@ void _config_autoboot_list() else boot_text[(i - 1) * 512] = '*'; - memcpy(boot_text + (i - 1) * 512 + 1, ini_sec->name, strlen(ini_sec->name)); + memcpy(boot_text + (i - 1) * 512 + 1, ini_sec->name, strlen(ini_sec->name) + 1); boot_text[strlen(ini_sec->name) + (i - 1) * 512 + 1] = 0; ments[i].caption = &boot_text[(i - 1) * 512]; } @@ -295,7 +295,7 @@ void config_autoboot() else boot_text[(i - 4) * 512] = '*'; - memcpy(boot_text + (i - 4) * 512 + 1, ini_sec->name, strlen(ini_sec->name)); + memcpy(boot_text + (i - 4) * 512 + 1, ini_sec->name, strlen(ini_sec->name) + 1); boot_text[strlen(ini_sec->name) + (i - 4) * 512 + 1] = 0; ments[i].caption = &boot_text[(i - 4) * 512]; } @@ -501,9 +501,9 @@ void config_verification() ments[1].type = MENT_CHGLINE; - memcpy(vr_text, " Disable", 9); - memcpy(vr_text + 64, " Sparse (Fast - Not reliable)", 31); - memcpy(vr_text + 128, " Full (Slow - 100% reliable)", 31); + memcpy(vr_text, " Disable (Fastest)", 19); + memcpy(vr_text + 64, " Sparse (Fast - Not reliable)", 32); + memcpy(vr_text + 128, " Full (Slow - 100% reliable)", 32); for (u32 i = 0; i < 3; i++) { diff --git a/bootloader/config/ini.c b/bootloader/config/ini.c index 7017937..b569f26 100644 --- a/bootloader/config/ini.c +++ b/bootloader/config/ini.c @@ -192,11 +192,10 @@ void ini_free(link_t *dst) { free(kv->key); free(kv->val); - free(kv); + //free(kv); } } free(ini_sec->name); - //TODO: Free section structs. //free(ini_sec); } diff --git a/bootloader/gfx/di.c b/bootloader/gfx/di.c index 346b359..dd50cb1 100644 --- a/bootloader/gfx/di.c +++ b/bootloader/gfx/di.c @@ -42,8 +42,8 @@ static void _display_dsi_wait(u32 timeout, u32 off, u32 mask) void display_init() { // Power on. - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_LDO0_CFG, 0xD0); // Configure to 1.2V. - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_GPIO7, 0x09); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_LDO0_CFG, 0xD0); // Configure to 1.2V. + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO7, 0x09); // Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x1010000; diff --git a/bootloader/gfx/gfx.c b/bootloader/gfx/gfx.c index 8a0b810..68aee79 100644 --- a/bootloader/gfx/gfx.c +++ b/bootloader/gfx/gfx.c @@ -508,15 +508,10 @@ void gfx_set_rect_rgb(gfx_ctxt_t *ctxt, const u8 *buf, u32 size_x, u32 size_y, u void gfx_set_rect_argb(gfx_ctxt_t *ctxt, const u32 *buf, u32 size_x, u32 size_y, u32 pos_x, u32 pos_y) { - u32 pos = 0; + u32 *ptr = (u32 *)buf; for (u32 y = pos_y; y < (pos_y + size_y); y++) - { for (u32 x = pos_x; x < (pos_x + size_x); x++) - { - ctxt->fb[x + y*ctxt->stride] = buf[pos]; - pos+=1; - } - } + ctxt->fb[x + y * ctxt->stride] = *ptr++; } void gfx_render_bmp_argb(gfx_ctxt_t *ctxt, const u32 *buf, u32 size_x, u32 size_y, u32 pos_x, u32 pos_y) @@ -524,6 +519,6 @@ void gfx_render_bmp_argb(gfx_ctxt_t *ctxt, const u32 *buf, u32 size_x, u32 size_ for (u32 y = pos_y; y < (pos_y + size_y); y++) { for (u32 x = pos_x; x < (pos_x + size_x); x++) - ctxt->fb[x + y*ctxt->stride] = buf[(size_y + pos_y - 1 - y ) * size_x + x - pos_x]; + ctxt->fb[x + y * ctxt->stride] = buf[(size_y + pos_y - 1 - y ) * size_x + x - pos_x]; } } diff --git a/bootloader/gfx/tui.c b/bootloader/gfx/tui.c index 0d503ae..105d987 100644 --- a/bootloader/gfx/tui.c +++ b/bootloader/gfx/tui.c @@ -60,10 +60,10 @@ void tui_sbar(gfx_con_t *con, bool force_update) max17050_get_property(MAX17050_AvgCurrent, &battVoltCurr); if (battVoltCurr >= 0) - gfx_printf(con, " %k+%d mA %k%K\n", + gfx_printf(con, " %k+%d mA%k%K\n", 0xFF008800, battVoltCurr / 1000, 0xFFCCCCCC, 0xFF1B1B1B); else - gfx_printf(con, " %k-%d mA %k%K\n", + gfx_printf(con, " %k-%d mA%k%K\n", 0xFF880000, (~battVoltCurr) / 1000, 0xFFCCCCCC, 0xFF1B1B1B); con->fntsz = prevFontSize; gfx_con_setpos(con, cx, cy); @@ -107,7 +107,7 @@ void *tui_do_menu(gfx_con_t *con, menu_t *menu) X_MENU_LOGO, Y_MENU_LOGO, X_POS_MENU_LOGO, Y_POS_MENU_LOGO); #endif //MENU_LOGO_ENABLE - while (1) + while (true) { gfx_con_setcol(con, 0xFFCCCCCC, 1, 0xFF1B1B1B); gfx_con_setpos(con, menu->x, menu->y); diff --git a/bootloader/hos/hos.c b/bootloader/hos/hos.c index f135e7e..ac89178 100644 --- a/bootloader/hos/hos.c +++ b/bootloader/hos/hos.c @@ -131,7 +131,7 @@ static void _se_lock() SE(SE_KEY_TABLE_ACCESS_LOCK_OFFSET) = 0; // Make all key access regs secure only. SE(SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET) = 0; // Make all RSA access regs secure only. SE(SE_SECURITY_0) &= 0xFFFFFFFB; // Make access lock regs secure only. - memset((void *) IPATCH_BASE, 0, 13); + memset((void *)IPATCH_BASE, 0, 13); SB(SB_CSR) = 0x10; // Protected IROM enable. // This is useful for documenting the bits in the SE config registers, so we can keep it around. @@ -685,7 +685,7 @@ int hos_launch(ini_sec_t *cfg) // Wait for secmon to get ready. cluster_boot_cpu0(ctxt.pkg1_id->secmon_base); while (!*mb_out) - usleep(1); // This only works when in IRAM or with a trained DRAM. + usleep(1); // This only works when in IRAM or with a trained DRAM. //TODO: pkg1.1 locks PMC scratches, we can do that too at some point. /*PMC(0x4) = 0x7FFFF3; diff --git a/bootloader/ianos/ianos.c b/bootloader/ianos/ianos.c index b39cae1..ea65a4f 100644 --- a/bootloader/ianos/ianos.c +++ b/bootloader/ianos/ianos.c @@ -95,8 +95,13 @@ int ianos_loader(bool sdmount, char *path, elfType_t type, void *moduleConfig) int res = 0; if (sdmount) + { if (!sd_mount()) - goto elfLoadFinalOut; + { + res = 0xFFFF; + goto elfLoadFinalOut; + } + } fileBuf = sd_file_read(path); diff --git a/bootloader/main.c b/bootloader/main.c index d3cafff..10f623b 100644 --- a/bootloader/main.c +++ b/bootloader/main.c @@ -351,7 +351,7 @@ void config_hw() clock_enable_se(); // Enable fuse clock. - clock_enable_fuse(1); + clock_enable_fuse(true); // Disable fuse programming. fuse_disable_program(); @@ -369,33 +369,30 @@ void config_hw() clock_enable_i2c(I2C_1); clock_enable_i2c(I2C_5); - static const clock_t clock_unk1 = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, 0x42C, 0x1F, 0, 0 }; - static const clock_t clock_unk2 = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, 0, 0x1E, 0, 0 }; - clock_enable(&clock_unk1); - clock_enable(&clock_unk2); + clock_enable_unk2(); i2c_init(I2C_1); i2c_init(I2C_5); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_CNFGBBC, 0x40); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_ONOFFCNFG1, 0x78); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, 0x40); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, 0x78); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_CFG0, 0x38); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_CFG1, 0x3A); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_CFG2, 0x38); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_LDO4, 0xF); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_LDO8, 0xC7); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_SD0, 0x4F); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_SD1, 0x29); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_SD3, 0x1B); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0, 0x38); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1, 0x3A); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2, 0x38); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_LDO4, 0xF); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_LDO8, 0xC7); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_SD0, 0x4F); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_SD1, 0x29); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_SD3, 0x1B); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_SD0, 42); //42 = (1125000 - 600000) / 12500 -> 1.125V + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD0, 42); //42 = (1125000 - 600000) / 12500 -> 1.125V - config_pmc_scratch(); + config_pmc_scratch(); // Missing from 4.x+ CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; - mc_config_carveout(); + mc_config_carveout(); // Missing from 4.x+ sdram_init(); } @@ -1754,9 +1751,9 @@ void (*ext_payload_ptr)() = (void *)EXT_PAYLOAD_ADDR; void reloc_patcher(u32 payload_size) { - const u32 START_OFF = 0x7C; - const u32 PAYLOAD_END_OFF = 0x84; - const u32 IPL_START_OFF = 0x88; + static const u32 START_OFF = 0x7C; + static const u32 PAYLOAD_END_OFF = 0x84; + static const u32 IPL_START_OFF = 0x88; memcpy((u8 *)EXT_PAYLOAD_ADDR, (u8 *)IPL_START, PATCHED_RELOC_SZ); @@ -1807,7 +1804,12 @@ int launch_payload(char *path, bool update) } f_close(&fp); - free(path); + if (!update) + { + free(path); + path = NULL; + } + if (update) { @@ -1834,14 +1836,14 @@ int launch_payload(char *path, bool update) { if (!update) reloc_patcher(ALIGN(size, 0x10)); - reconfig_hw_workaround(0); + reconfig_hw_workaround(false); } else { reloc_patcher(0x7000); if (*(vu32 *)CBFS_SDRAM_EN_ADDR != 0x4452414D) return 1; - reconfig_hw_workaround(1); + reconfig_hw_workaround(true); } // Launch our payload. @@ -1958,7 +1960,10 @@ void launch_tools(u8 type) if (!type) { if (launch_payload(dir, false)) + { EPRINTF("Failed to launch payload."); + free(dir); + } } else ianos_loader(true, dir, DRAM_LIB, NULL); @@ -2145,8 +2150,8 @@ void launch_firmware() if (!cfg_sec) { - gfx_printf(&gfx_con, "\nUsing default launch configuration...\n\n"); - gfx_puts(&gfx_con, "Press POWER to Continue.\nPress VOL to go to the menu.\n\n\n"); + gfx_puts(&gfx_con, "\nPress POWER to Continue.\nPress VOL to go to the menu.\n\n"); + gfx_printf(&gfx_con, "\nUsing default launch configuration...\n\n\n"); u32 btn = btn_wait(); if (!(btn & BTN_POWER)) @@ -2261,7 +2266,6 @@ void auto_launch_firmware() if (h_cfg.autoboot_list) { ini_free(&ini_sections); - list_init(&ini_sections); ini_free_section(cfg_sec); boot_entry_id = 1; bootlogoCustomEntry = NULL; @@ -3052,6 +3056,7 @@ ment_t ment_cinfo[] = { MDEF_BACK(), MDEF_CHGLINE(), MDEF_CAPTION("---- SoC Info ----", 0xFF0AB9E6), + MDEF_HANDLER("Ipatches & bootrom info", bootrom_ipatches_info), MDEF_HANDLER("Print fuse info", print_fuseinfo), MDEF_HANDLER("Print kfuse info", print_kfuseinfo), MDEF_HANDLER("Print TSEC keys", print_tsec_key), @@ -3117,7 +3122,6 @@ ment_t ment_tools[] = { MDEF_HANDLER("Fix battery de-sync", fix_battery_desync), MDEF_HANDLER("Unset archive bit (switch folder)", fix_sd_switch_attr), MDEF_HANDLER("Unset archive bit (all sd files)", fix_sd_all_attr), - MDEF_HANDLER("Ipatches & bootrom info", bootrom_ipatches_info), //MDEF_HANDLER("Fix fuel gauge configuration", fix_fuel_gauge_configuration), //MDEF_HANDLER("Reset all battery cfg", reset_pmic_fuel_gauge_charger_config), MDEF_CHGLINE(), @@ -3155,7 +3159,7 @@ extern void pivot_stack(u32 stack_top); void ipl_main() { // Skip config if we just updated the bootloader. - if (*(u32 *)BOOTLOADER_UPDATED_MAGIC_ADDR != BOOTLOADER_UPDATED_MAGIC) + if (*(vu32 *)BOOTLOADER_UPDATED_MAGIC_ADDR != BOOTLOADER_UPDATED_MAGIC) config_hw(); //Pivot the stack so we have enough space. @@ -3167,6 +3171,9 @@ void ipl_main() //uart_send(UART_C, (u8 *)0x40000000, 0x10000); //uart_wait_idle(UART_C, UART_TX_IDLE); + // Set bootloader's default configuration. + set_default_configuration(); + // Save sdram lp0 config. ianos_loader(true, "bootloader/sys/libsys_lp0.bso", DRAM_LIB, (void *)sdram_get_params()); @@ -3185,13 +3192,12 @@ void ipl_main() // Enable backlight after initializing gfx //display_backlight(true); - set_default_configuration(); // Load saved configuration and auto boot if enabled. auto_launch_firmware(); - while (1) + while (true) tui_do_menu(&gfx_con, &menu_top); - while (1) + while (true) ; } diff --git a/bootloader/mem/heap.c b/bootloader/mem/heap.c index d61755c..b2b03dc 100644 --- a/bootloader/mem/heap.c +++ b/bootloader/mem/heap.c @@ -124,6 +124,6 @@ void *calloc(u32 num, u32 size) void free(void *buf) { - if (buf != NULL) + if ((buf != NULL) || ((u32)buf > (_heap.start - 1))) _heap_free(&_heap, (u32)buf); } diff --git a/bootloader/mem/sdram.c b/bootloader/mem/sdram.c index 3a84c1e..f6ff3be 100644 --- a/bootloader/mem/sdram.c +++ b/bootloader/mem/sdram.c @@ -507,8 +507,8 @@ void sdram_init() //TODO: sdram_id should be in [0,4]. const sdram_params_t *params = (const sdram_params_t *)sdram_get_params(); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_SD_CFG2, 0x05); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_SD1, 40); //40 = (1000 * 1100 - 600000) / 12500 -> 1.1V + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, 0x05); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD1, 40); //40 = (1000 * 1100 - 600000) / 12500 -> 1.1V PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel; usleep(params->pmc_vddp_sel_wait); diff --git a/bootloader/power/max77620.h b/bootloader/power/max77620.h index 1c0d25e..77b2c4b 100644 --- a/bootloader/power/max77620.h +++ b/bootloader/power/max77620.h @@ -11,6 +11,8 @@ #ifndef _MFD_MAX77620_H_ #define _MFD_MAX77620_H_ +#define MAX77620_I2C_ADDR 0x3C + /* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */ #define MAX77620_REG_CNFGGLBL1 0x00 #define MAX77620_REG_CNFGGLBL2 0x01 diff --git a/bootloader/power/max7762x.c b/bootloader/power/max7762x.c index fc7db66..f7809ee 100644 --- a/bootloader/power/max7762x.c +++ b/bootloader/power/max7762x.c @@ -68,8 +68,8 @@ int max77620_regulator_get_status(u32 id) const max77620_regulator_t *reg = &_pmic_regulators[id]; if (reg->type == REGULATOR_SD) - return (i2c_recv_byte(I2C_5, 0x3C, MAX77620_REG_STATSD) & reg->status_mask) ? 0 : 1; - return (i2c_recv_byte(I2C_5, 0x3C, reg->cfg_addr) & 8) ? 1 : 0; + return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_STATSD) & reg->status_mask) ? 0 : 1; + return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->cfg_addr) & 8) ? 1 : 0; } int max77620_regulator_config_fps(u32 id) @@ -79,7 +79,7 @@ int max77620_regulator_config_fps(u32 id) const max77620_regulator_t *reg = &_pmic_regulators[id]; - i2c_send_byte(I2C_5, 0x3C, reg->fps_addr, (reg->fps_src << 6) | (reg->pu_period << 3) | (reg->pd_period)); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg->fps_addr, (reg->fps_src << 6) | (reg->pu_period << 3) | (reg->pd_period)); return 1; } @@ -95,9 +95,9 @@ int max77620_regulator_set_voltage(u32 id, u32 mv) return 0; u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step; - u8 val = i2c_recv_byte(I2C_5, 0x3C, reg->volt_addr); + u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr); val = (val & ~reg->volt_mask) | (mult & reg->volt_mask); - i2c_send_byte(I2C_5, 0x3C, reg->volt_addr, val); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr, val); usleep(1000); return 1; @@ -111,12 +111,12 @@ int max77620_regulator_enable(u32 id, int enable) const max77620_regulator_t *reg = &_pmic_regulators[id]; u32 addr = reg->type == REGULATOR_SD ? reg->cfg_addr : reg->volt_addr; - u8 val = i2c_recv_byte(I2C_5, 0x3C, addr); + u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, addr); if (enable) val = (val & ~reg->enable_mask) | ((3 << reg->enable_shift) & reg->enable_mask); else val &= ~reg->enable_mask; - i2c_send_byte(I2C_5, 0x3C, addr, val); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, addr, val); usleep(1000); return 1; @@ -126,16 +126,17 @@ void max77620_config_default() { for (u32 i = 1; i <= REGULATOR_MAX; i++) { - i2c_recv_byte(I2C_5, 0x3C, MAX77620_REG_CID4); + i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4); max77620_regulator_config_fps(i); max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default); if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE) max77620_regulator_enable(i, 1); } - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_SD_CFG2, 4); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, 4); } void max77620_low_battery_monitor_config() { - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_CNFGGLBL1, MAX77620_CNFGGLBL1_LBDAC_EN | MAX77620_CNFGGLBL1_LBHYST_N | MAX77620_CNFGGLBL1_LBDAC_N); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGGLBL1, + MAX77620_CNFGGLBL1_LBDAC_EN | MAX77620_CNFGGLBL1_LBHYST_N | MAX77620_CNFGGLBL1_LBDAC_N); } diff --git a/bootloader/power/max7762x.h b/bootloader/power/max7762x.h index 43ba3e8..e5cf394 100644 --- a/bootloader/power/max7762x.h +++ b/bootloader/power/max7762x.h @@ -59,6 +59,51 @@ #define REGULATOR_LDO8 12 #define REGULATOR_MAX 12 +#define MAX77621_CPU_I2C_ADDR 0x1B +#define MAX77621_GPU_I2C_ADDR 0x1C + +#define MAX77621_VOUT_REG 0 +#define MAX77621_VOUT_DVC_REG 1 +#define MAX77621_CONTROL1_REG 2 +#define MAX77621_CONTROL2_REG 3 + +/* MAX77621_VOUT */ +#define MAX77621_VOUT_ENABLE (1 << 7) +#define MAX77621_VOUT_MASK 0x7F + +/* MAX77621_VOUT_DVC_DVS */ +#define MAX77621_DVS_VOUT_MASK 0x7F + +/* MAX77621_CONTROL1 */ +#define MAX77621_SNS_ENABLE (1 << 7) +#define MAX77621_FPWM_EN_M (1 << 6) +#define MAX77621_NFSR_ENABLE (1 << 5) +#define MAX77621_AD_ENABLE (1 << 4) +#define MAX77621_BIAS_ENABLE (1 << 3) +#define MAX77621_FREQSHIFT_9PER (1 << 2) + +#define MAX77621_RAMP_12mV_PER_US 0x0 +#define MAX77621_RAMP_25mV_PER_US 0x1 +#define MAX77621_RAMP_50mV_PER_US 0x2 +#define MAX77621_RAMP_200mV_PER_US 0x3 +#define MAX77621_RAMP_MASK 0x3 + +/* MAX77621_CONTROL2 */ +#define MAX77621_WDTMR_ENABLE (1 << 6) +#define MAX77621_DISCH_ENBABLE (1 << 5) +#define MAX77621_FT_ENABLE (1 << 4) +#define MAX77621_T_JUNCTION_120 (1 << 7) + +#define MAX77621_CKKADV_TRIP_DISABLE 0xC +#define MAX77621_CKKADV_TRIP_75mV_PER_US 0x0 +#define MAX77621_CKKADV_TRIP_150mV_PER_US 0x4 +#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS 0x8 + +#define MAX77621_INDUCTOR_MIN_30_PER 0x0 +#define MAX77621_INDUCTOR_NOMINAL 0x1 +#define MAX77621_INDUCTOR_PLUS_30_PER 0x2 +#define MAX77621_INDUCTOR_PLUS_60_PER 0x3 + int max77620_regulator_get_status(u32 id); int max77620_regulator_config_fps(u32 id); int max77620_regulator_set_voltage(u32 id, u32 mv); diff --git a/bootloader/sec/se.c b/bootloader/sec/se.c index 3578c21..4f01022 100644 --- a/bootloader/sec/se.c +++ b/bootloader/sec/se.c @@ -167,7 +167,9 @@ int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input) { SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_KEYTAB); SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT); + SE(SE_BLOCK_COUNT_REG_OFFSET) = 0; SE(SE_CRYPTO_KEYTABLE_DST_REG_OFFSET) = SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(ks_dst); + return _se_execute(OP_START, NULL, 0, input, 0x10); } diff --git a/bootloader/soc/clock.c b/bootloader/soc/clock.c index 3b20f8c..cb6133e 100644 --- a/bootloader/soc/clock.c +++ b/bootloader/soc/clock.c @@ -36,7 +36,8 @@ static const clock_t _clock_i2c[] = { /* I2C6 */ { 0 } }; -static clock_t _clock_se = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, 0x42C, 0x1F, 0, 0 }; +static clock_t _clock_se = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 0x1F, 0, 0 }; +static clock_t _clock_unk2 = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_RST_SOURCE, 0x1E, 0, 0 }; static clock_t _clock_host1x = { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3 }; static clock_t _clock_tsec = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2 }; @@ -71,7 +72,7 @@ void clock_disable(const clock_t *clk) CLOCK(clk->enable) &= ~(1 << clk->index); } -void clock_enable_fuse(u32 enable) +void clock_enable_fuse(bool enable) { CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = (CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF) | ((enable & 1) << 28); } @@ -86,11 +87,21 @@ void clock_enable_i2c(u32 idx) clock_enable(&_clock_i2c[idx]); } +void clock_disable_i2c(u32 idx) +{ + clock_disable(&_clock_i2c[idx]); +} + void clock_enable_se() { clock_enable(&_clock_se); } +void clock_enable_unk2() +{ + clock_enable(&_clock_unk2); +} + void clock_enable_host1x() { clock_enable(&_clock_host1x); @@ -172,6 +183,11 @@ void clock_enable_coresight() clock_enable(&_clock_coresight); } +void clock_disable_coresight() +{ + clock_disable(&_clock_coresight); +} + #define L_SWR_SDMMC1_RST (1 << 14) #define L_SWR_SDMMC2_RST (1 << 9) #define L_SWR_SDMMC4_RST (1 << 15) diff --git a/bootloader/soc/clock.h b/bootloader/soc/clock.h index 20ba295..45ef277 100644 --- a/bootloader/soc/clock.h +++ b/bootloader/soc/clock.h @@ -57,6 +57,7 @@ #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C #define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180 #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0 +#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 0x1B8 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC #define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4 #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C @@ -94,9 +95,11 @@ #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4 #define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4 #define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410 +#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C #define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440 #define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448 #define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C +#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450 #define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454 #define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488 #define CLK_RST_CONTROLLER_PLLE_AUX 0x48C @@ -128,10 +131,12 @@ void clock_enable(const clock_t *clk); void clock_disable(const clock_t *clk); /*! Clock control for specific hardware portions. */ -void clock_enable_fuse(u32 enable); +void clock_enable_fuse(bool enable); void clock_enable_uart(u32 idx); void clock_enable_i2c(u32 idx); +void clock_disable_i2c(u32 idx); void clock_enable_se(); +void clock_enable_unk2(); void clock_enable_host1x(); void clock_disable_host1x(); void clock_enable_tsec(); @@ -147,6 +152,7 @@ void clock_disable_kfuse(); void clock_enable_cl_dvfs(); void clock_disable_cl_dvfs(); void clock_enable_coresight(); +void clock_disable_coresight(); void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val); void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type); int clock_sdmmc_is_not_reset_and_enabled(u32 id); diff --git a/bootloader/soc/cluster.c b/bootloader/soc/cluster.c index 40466fb..de3dbdd 100644 --- a/bootloader/soc/cluster.c +++ b/bootloader/soc/cluster.c @@ -21,24 +21,25 @@ #include "../soc/pmc.h" #include "../soc/t210.h" #include "../power/max77620.h" +#include "../power/max7762x.h" void _cluster_enable_power() { - u8 tmp = i2c_recv_byte(I2C_5, 0x3C, MAX77620_REG_AME_GPIO); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_AME_GPIO, tmp & 0xDF); - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_GPIO5, 0x09); + u8 tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, tmp & 0xDF); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 0x09); // Enable cores power. - i2c_send_byte(I2C_5, 0x1B, 0x2, 0x20); - i2c_send_byte(I2C_5, 0x1B, 0x3, 0x8D); - i2c_send_byte(I2C_5, 0x1B, 0x0, 0xB7); - i2c_send_byte(I2C_5, 0x1B, 0x1, 0xB7); + i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_NFSR_ENABLE); + i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG, MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL); + i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | 0x37); + i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | 0x37); } -int _cluster_pmc_enable_partition(u32 part, u32 toggle) +int _cluster_pmc_enable_partition(u32 part, u32 toggle, bool enable) { // Check if the partition has already been turned on. - if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part) + if (enable && PMC(APBDEV_PMC_PWRGATE_STATUS) & part) return 1; u32 i = 5001; @@ -50,7 +51,7 @@ int _cluster_pmc_enable_partition(u32 part, u32 toggle) return 0; } - PMC(APBDEV_PMC_PWRGATE_TOGGLE) = toggle | 0x100; + PMC(APBDEV_PMC_PWRGATE_TOGGLE) = toggle | (enable ? 0x100 : 0); i = 5001; while (i > 0) @@ -98,9 +99,9 @@ void cluster_boot_cpu0(u32 entry) CLOCK(CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2) &= 0xFFFFF000; // Enable CPU rail. - _cluster_pmc_enable_partition(1, 0); - //Enable cluster 0 non-CPU. - _cluster_pmc_enable_partition(0x8000, 15); + _cluster_pmc_enable_partition(1, 0, true); + // Enable cluster 0 non-CPU. + _cluster_pmc_enable_partition(0x8000, 15, true); // Enable CE0. _cluster_pmc_enable_partition(0x4000, 14); diff --git a/bootloader/soc/i2c.c b/bootloader/soc/i2c.c index 255e372..df1c09d 100644 --- a/bootloader/soc/i2c.c +++ b/bootloader/soc/i2c.c @@ -26,11 +26,11 @@ static u32 i2c_addrs[] = { static void _i2c_wait(vu32 *base) { - base[0x23] = 0x25; + base[I2C_CONFIG_LOAD] = 0x25; for (u32 i = 0; i < 20; i++) { usleep(1); - if (!(base[0x23] & 1)) + if (!(base[I2C_CONFIG_LOAD] & 1)) break; } } @@ -44,16 +44,16 @@ static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size) memcpy(&tmp, buf, size); vu32 *base = (vu32 *)i2c_addrs[idx]; - base[1] = x << 1; //Set x (send mode). - base[3] = tmp; //Set value. - base[0] = (2 * size - 2) | 0x2800; //Set size and send mode. + base[I2C_CMD_ADDR0] = x << 1; //Set x (send mode). + base[I2C_CMD_DATA1] = tmp; //Set value. + base[I2C_CNFG] = (2 * size - 2) | 0x2800; //Set size and send mode. _i2c_wait(base); //Kick transaction. - base[0] = (base[0] & 0xFFFFFDFF) | 0x200; - while (base[7] & 0x100) + base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200; + while (base[I2C_STATUS] & 0x100) ; - if (base[7] << 28) + if (base[I2C_STATUS] << 28) return 0; return 1; @@ -65,18 +65,18 @@ static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x) return 0; vu32 *base = (vu32 *)i2c_addrs[idx]; - base[1] = (x << 1) | 1; // Set x (recv mode). - base[0] = (2 * size - 2) | 0x2840; // Set size and recv mode. + base[I2C_CMD_ADDR0] = (x << 1) | 1; // Set x (recv mode). + base[I2C_CNFG] = (size - 1) << 1 | 0x2840; // Set size and recv mode. _i2c_wait(base); // Kick transaction. - base[0] = (base[0] & 0xFFFFFDFF) | 0x200; - while (base[7] & 0x100) + base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200; + while (base[I2C_STATUS] & 0x100) ; - if (base[7] << 28) + if (base[I2C_STATUS] << 28) return 0; - u32 tmp = base[3]; // Get value. + u32 tmp = base[I2C_CMD_DATA1]; // Get LS value. memcpy(buf, &tmp, size); return 1; @@ -86,19 +86,19 @@ void i2c_init(u32 idx) { vu32 *base = (vu32 *)i2c_addrs[idx]; - base[0x1B] = 0x50001; - base[0x21] = 0x90003; + base[I2C_CLK_DIVISOR_REGISTER] = 0x50001; + base[I2C_BUS_CLEAR_CONFIG] = 0x90003; _i2c_wait(base); for (u32 i = 0; i < 10; i++) { usleep(20000); - if (base[0x1A] & 0x800) + if (base[INTERRUPT_STATUS_REGISTER] & 0x800) break; } - (vu32)base[0x22]; - base[0x1A] = base[0x1A]; + (vu32)base[I2C_BUS_CLEAR_STATUS]; + base[INTERRUPT_STATUS_REGISTER] = base[INTERRUPT_STATUS_REGISTER]; } int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size) diff --git a/bootloader/soc/i2c.h b/bootloader/soc/i2c.h index f808e93..e2b2af5 100644 --- a/bootloader/soc/i2c.h +++ b/bootloader/soc/i2c.h @@ -26,6 +26,17 @@ #define I2C_5 4 #define I2C_6 5 +#define I2C_CNFG 0x00 +#define I2C_CMD_ADDR0 0x01 +#define I2C_CMD_DATA1 0x03 +#define I2C_CMD_DATA2 0x04 +#define I2C_STATUS 0x07 +#define INTERRUPT_STATUS_REGISTER 0x1A +#define I2C_CLK_DIVISOR_REGISTER 0x1B +#define I2C_BUS_CLEAR_CONFIG 0x21 +#define I2C_BUS_CLEAR_STATUS 0x22 +#define I2C_CONFIG_LOAD 0x23 + void i2c_init(u32 idx); int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size); int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y); diff --git a/bootloader/soc/t210.h b/bootloader/soc/t210.h index 5e42ca1..a07d11b 100644 --- a/bootloader/soc/t210.h +++ b/bootloader/soc/t210.h @@ -19,9 +19,8 @@ #include "../utils/types.h" -#define BOOTROM_BASE 0x100000 #define BOOTROM_SIZE 0x18000 - +#define BOOTROM_BASE 0x100000 #define HOST1X_BASE 0x50000000 #define BPMP_CACHE_BASE 0x50040000 #define DISPLAY_A_BASE 0x54200000 @@ -48,9 +47,10 @@ #define APB_MISC_BASE 0x70000000 #define PINMUX_AUX_BASE 0x70003000 #define UART_BASE 0x70006000 +#define PWM_BASE 0x7000A000 #define RTC_BASE 0x7000E000 #define PMC_BASE 0x7000E400 -#define SYSCTR0_BASE 0x7000F000 +#define SYSCTR0_BASE 0x700F0000 #define FUSE_BASE 0x7000F800 #define KFUSE_BASE 0x7000FC00 #define SE_BASE 0x70012000 @@ -58,6 +58,7 @@ #define EMC_BASE 0x7001B000 #define MIPI_CAL_BASE 0x700E3000 #define I2S_BASE 0x702D1000 +#define CL_DVFS_BASE 0x70110000 #define _REG(base, off) *(vu32 *)((base) + (off)) @@ -95,6 +96,8 @@ #define EMC(off) _REG(EMC_BASE, off) #define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off) #define I2S(off) _REG(I2S_BASE, off) +#define CL_DVFS(off) _REG(CL_DVFS_BASE, off) +#define TEST_REG(off) _REG(0x0, off) /*! Misc registers. */ #define APB_MISC_PP_PINMUX_GLOBAL 0x40 diff --git a/bootloader/utils/btn.c b/bootloader/utils/btn.c index b29f036..795ee93 100644 --- a/bootloader/utils/btn.c +++ b/bootloader/utils/btn.c @@ -20,6 +20,7 @@ #include "../soc/gpio.h" #include "../soc/t210.h" #include "util.h" +#include "../power/max77620.h" u32 btn_read() { @@ -28,7 +29,7 @@ u32 btn_read() res |= BTN_VOL_DOWN; if (!gpio_read(GPIO_PORT_X, GPIO_PIN_6)) res |= BTN_VOL_UP; - if (i2c_recv_byte(4, 0x3C, 0x15) & 0x4) + if (i2c_recv_byte(4, MAX77620_I2C_ADDR, 0x15) & 0x4) res |= BTN_POWER; return res; }