From fb31cb2926d8aae4b91a53512155c021e573ad4c Mon Sep 17 00:00:00 2001 From: CTCaer Date: Wed, 13 Mar 2024 01:37:52 +0200 Subject: [PATCH] bdk: ccplex: add no rst vector lock & powergating Allow not locking the reset vectors and launch a new payload after powergating ccplex. --- bdk/mem/smmu.c | 4 +-- bdk/soc/ccplex.c | 81 ++++++++++++++++++++++++++++++++++++++++-------- bdk/soc/ccplex.h | 3 +- 3 files changed, 72 insertions(+), 16 deletions(-) diff --git a/bdk/mem/smmu.c b/bdk/mem/smmu.c index 8bc9aac..6e2b7e8 100644 --- a/bdk/mem/smmu.c +++ b/bdk/mem/smmu.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2018 naehrwert * Copyright (c) 2018 balika011 - * Copyright (c) 2018-2022 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -94,7 +94,7 @@ void smmu_enable() if (smmu_used) return; - ccplex_boot_cpu0((u32)smmu_payload); + ccplex_boot_cpu0((u32)smmu_payload, true); smmu_used = true; msleep(150); diff --git a/bdk/soc/ccplex.c b/bdk/soc/ccplex.c index 37ce73d..d8e315a 100644 --- a/bdk/soc/ccplex.c +++ b/bdk/soc/ccplex.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2022 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -27,7 +27,9 @@ #include #include -void _ccplex_enable_power_t210() +#define CCPLEX_FLOWCTRL_POWERGATING 0 + +static void _ccplex_enable_power_t210() { // Configure GPIO5 and enable output in order to power CPU pmic. max77620_config_gpio(5, MAX77620_GPIO_OUTPUT_ENABLE); @@ -37,19 +39,31 @@ void _ccplex_enable_power_t210() // 1.0.0-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL. max77621_config_default(REGULATOR_CPU0, MAX77621_CTRL_HOS_CFG); - // Set voltage and enable cores power. + // Set voltage and enable cluster power. max7762x_regulator_set_voltage(REGULATOR_CPU0, 950000); max7762x_regulator_enable(REGULATOR_CPU0, true); } -void _ccplex_enable_power_t210b01() +static void _ccplex_enable_power_t210b01() { - // Set voltage and enable cores power. + // Set voltage and enable cluster power. max7762x_regulator_set_voltage(REGULATOR_CPU1, 800000); max7762x_regulator_enable(REGULATOR_CPU1, true); } -void ccplex_boot_cpu0(u32 entry) +static void _ccplex_disable_power() +{ + // Disable cluster power. + if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210) + { + max7762x_regulator_enable(REGULATOR_CPU0, false); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 0); + } + else + max7762x_regulator_enable(REGULATOR_CPU1, false); +} + +void ccplex_boot_cpu0(u32 entry, bool lock) { // Set ACTIVE_CLUSER to FAST. FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= ~CLUSTER_CTRL_ACTIVE_SLOW; @@ -62,12 +76,12 @@ void ccplex_boot_cpu0(u32 entry) clock_enable_pllx(); // Configure MSELECT source and enable clock to 102MHz. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6; + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = 6; CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_MSELECT); // Configure initial CPU clock frequency and enable clock. CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888; // PLLX_OUT0_LJ. - CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000; + CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = BIT(31); // SUPER_CDIV_ENB. CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_CPUG); clock_enable_coresight(); @@ -90,12 +104,15 @@ void ccplex_boot_cpu0(u32 entry) EXCP_VEC(EVP_CPU_RESET_VECTOR) = 0; // Set reset vector. - SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN; + SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN; SB(SB_AA64_RESET_HIGH) = 0; // Non-secure reset vector write disable. - SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS; - (void)SB(SB_CSR); + if (lock) + { + SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS; + (void)SB(SB_CSR); + } // Tighten up the security aperture. // MC(MC_TZ_SECURITY_CTRL) = 1; @@ -103,8 +120,46 @@ void ccplex_boot_cpu0(u32 entry) // Clear MSELECT reset. CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_CLR) = BIT(CLK_V_MSELECT); // Clear NONCPU reset. - CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000; + CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = BIT(29); // CLR_NONCPURESET. // Clear CPU0 reset. // < 5.x: 0x411F000F, Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset. - CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x41010001; + CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = BIT(30) | BIT(24) | BIT(16) | BIT(0); +} + +void ccplex_powergate_cpu0() +{ +#if CCPLEX_FLOWCTRL_POWERGATING + // Halt CPU0. + FLOW_CTLR(FLOW_CTLR_HALT_CPU0_EVENTS) = HALT_MODE_STOP_UNTIL_IRQ; + + // Powergate cluster via flow control without waiting for WFI. + FLOW_CTLR(FLOW_CTLR_CPU0_CSR) = CSR_INTR_FLAG | CSR_EVENT_FLAG | CSR_ENABLE_EXT_CPU_RAIL | CSR_WAIT_WFI_NONE | CSR_ENABLE; + + // Wait for the rail power off to finish. + while((FLOW_CTLR(FLOW_CTLR_CPU_PWR_CSR) & CPU_PWR_RAIL_STS_MASK) != CPU_PWR_RAIL_OFF); + + // Set CPU0 to waitevent. + FLOW_CTLR(FLOW_CTLR_HALT_CPU0_EVENTS) = HALT_MODE_WAITEVENT; +#endif + + // Set CPU0 POR and CORE, CX0, L2, and DBG reset. + CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET) = BIT(30) | BIT(24) | BIT(16) | BIT(0); + // Set NONCPU reset. + CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET) = BIT(29); + // Set MSELECT reset. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_SET) = BIT(CLK_V_MSELECT); + + // Disable CE0. + pmc_enable_partition(POWER_RAIL_CE0, DISABLE); + // Disable cluster 0 non-CPU. + pmc_enable_partition(POWER_RAIL_C0NC, DISABLE); + // Disable CPU rail. + pmc_enable_partition(POWER_RAIL_CRAIL, DISABLE); + + clock_disable_coresight(); + + // Clear out MSELECT and CPU clocks. + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_CLR) = BIT(CLK_V_MSELECT) | BIT(CLK_V_CPUG); + + _ccplex_disable_power(); } diff --git a/bdk/soc/ccplex.h b/bdk/soc/ccplex.h index fb5be92..496da43 100644 --- a/bdk/soc/ccplex.h +++ b/bdk/soc/ccplex.h @@ -19,6 +19,7 @@ #include -void ccplex_boot_cpu0(u32 entry); +void ccplex_boot_cpu0(u32 entry, bool lock); +void ccplex_powergate_cpu0(); #endif