utils: Fix ms timer accuracy

Additionally add BPMP delay timers for future use.
This commit is contained in:
CTCaer 2019-08-28 01:33:38 +03:00
parent 6cc0711382
commit f622d57f6b
14 changed files with 163 additions and 53 deletions

View file

@ -1303,6 +1303,7 @@ void ipl_main()
while (true) while (true)
tui_do_menu(&menu_top); tui_do_menu(&menu_top);
// Halt BPMP if we managed to get out of execution.
while (true) while (true)
; bpmp_halt();
} }

View file

@ -216,3 +216,37 @@ void bpmp_clk_rate_set(bpmp_freq_t fid)
} }
} }
// The following functions halt BPMP to reduce power while sleeping.
// They are not as accurate as RTC at big values but they guarantee time+ delay.
void bpmp_usleep(u32 us)
{
u32 delay;
// Each iteration takes 1us.
while (us)
{
delay = (us > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : us;
us -= delay;
FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_USEC | delay;
}
}
void bpmp_msleep(u32 ms)
{
u32 delay;
// Iteration time is variable. ~200 - 1000us.
while (ms)
{
delay = (ms > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : ms;
ms -= delay;
FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_MSEC | delay;
}
}
void bpmp_halt()
{
FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_JTAG;
}

View file

@ -47,5 +47,8 @@ void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
void bpmp_mmu_enable(); void bpmp_mmu_enable();
void bpmp_mmu_disable(); void bpmp_mmu_disable();
void bpmp_clk_rate_set(bpmp_freq_t fid); void bpmp_clk_rate_set(bpmp_freq_t fid);
void bpmp_usleep(u32 us);
void bpmp_msleep(u32 ms);
void bpmp_halt();
#endif #endif

View file

@ -19,19 +19,6 @@
#include "../utils/types.h" #include "../utils/types.h"
/*! Flow controller registers. */
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
#define FLOW_CTLR_HALT_COP_EVENTS 0x4
#define FLOW_CTLR_CPU0_CSR 0x8
#define FLOW_CTLR_CPU1_CSR 0x18
#define FLOW_CTLR_CPU2_CSR 0x20
#define FLOW_CTLR_CPU3_CSR 0x28
#define FLOW_CTLR_RAM_REPAIR 0x40
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
void cluster_boot_cpu0(u32 entry); void cluster_boot_cpu0(u32 entry);
#endif #endif

View file

@ -189,4 +189,24 @@
#define EMC_HEKA_UPD (1 << 30) #define EMC_HEKA_UPD (1 << 30)
#define EMC_SEPT_RUN (1 << 31) #define EMC_SEPT_RUN (1 << 31)
/*! Flow controller registers. */
#define FLOW_CTLR_HALT_COP_EVENTS 0x4
#define HALT_COP_SEC (1 << 23)
#define HALT_COP_MSEC (1 << 24)
#define HALT_COP_USEC (1 << 25)
#define HALT_COP_JTAG (1 << 28)
#define HALT_COP_WAIT_EVENT (1 << 30)
#define HALT_COP_WAIT_IRQ (1 << 31)
#define HALT_COP_MAX_CNT 0xFF
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
#define FLOW_CTLR_CPU0_CSR 0x8
#define FLOW_CTLR_CPU1_CSR 0x18
#define FLOW_CTLR_CPU2_CSR 0x20
#define FLOW_CTLR_CPU3_CSR 0x28
#define FLOW_CTLR_RAM_REPAIR 0x40
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
#endif #endif

View file

@ -24,6 +24,8 @@
#include "../soc/pmc.h" #include "../soc/pmc.h"
#include "../soc/t210.h" #include "../soc/t210.h"
#define USE_RTC_TIMER
extern void sd_unmount(); extern void sd_unmount();
u32 get_tmr_s() u32 get_tmr_s()
@ -35,7 +37,7 @@ u32 get_tmr_ms()
{ {
// The registers must be read with the following order: // The registers must be read with the following order:
// RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC) // RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC)
return (RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10)); return (RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000));
} }
u32 get_tmr_us() u32 get_tmr_us()
@ -43,19 +45,28 @@ u32 get_tmr_us()
return TMR(TIMERUS_CNTR_1US); //TIMERUS_CNTR_1US return TMR(TIMERUS_CNTR_1US); //TIMERUS_CNTR_1US
} }
void msleep(u32 milliseconds) void msleep(u32 ms)
{ {
u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10); #ifdef USE_RTC_TIMER
while (((RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10)) - start) <= milliseconds) u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000);
// Casting to u32 is important!
while (((u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000)) - start) <= ms)
; ;
#else
bpmp_msleep(ms);
#endif
} }
void usleep(u32 microseconds) void usleep(u32 us)
{ {
#ifdef USE_RTC_TIMER
u32 start = TMR(TIMERUS_CNTR_1US); u32 start = TMR(TIMERUS_CNTR_1US);
// Casting to u32 is important! // Casting to u32 is important!
while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= microseconds) while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= us)
; ;
#else
bpmp_usleep(us);
#endif
} }
void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops) void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops)
@ -76,7 +87,6 @@ void panic(u32 val)
while (true) while (true)
usleep(1); usleep(1);
} }
void reboot_normal() void reboot_normal()
@ -100,7 +110,7 @@ void reboot_rcm()
PMC(APBDEV_PMC_CNTRL) |= PMC_CNTRL_MAIN_RST; PMC(APBDEV_PMC_CNTRL) |= PMC_CNTRL_MAIN_RST;
while (true) while (true)
usleep(1); bpmp_halt();
} }
void power_off() void power_off()
@ -114,5 +124,5 @@ void power_off()
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF); i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF);
while (true) while (true)
usleep(1); bpmp_halt();
} }

View file

@ -46,8 +46,8 @@ typedef struct _nyx_storage_t
u32 get_tmr_us(); u32 get_tmr_us();
u32 get_tmr_ms(); u32 get_tmr_ms();
u32 get_tmr_s(); u32 get_tmr_s();
void usleep(u32 ticks); void usleep(u32 us);
void msleep(u32 milliseconds); void msleep(u32 ms);
void panic(u32 val); void panic(u32 val);
void reboot_normal(); void reboot_normal();
void reboot_rcm(); void reboot_rcm();

View file

@ -358,6 +358,7 @@ void load_saved_configuration()
void nyx_init_load_res() void nyx_init_load_res()
{ {
bpmp_mmu_enable(); bpmp_mmu_enable();
bpmp_clk_rate_set(BPMP_CLK_SUPER_BOOST);
// Set bootloader's default configuration. // Set bootloader's default configuration.
set_default_configuration(); set_default_configuration();
@ -385,8 +386,6 @@ void nyx_init_load_res()
sd_unmount(false); sd_unmount(false);
h_cfg.rcm_patched = fuse_check_patched_rcm(); h_cfg.rcm_patched = fuse_check_patched_rcm();
bpmp_clk_rate_set(BPMP_CLK_SUPER_BOOST);
} }
#define IPL_STACK_TOP 0x90010000 #define IPL_STACK_TOP 0x90010000
@ -424,6 +423,7 @@ void ipl_main()
nyx_load_and_run(); nyx_load_and_run();
// Halt BPMP if we managed to get out of execution.
while (true) while (true)
; bpmp_halt();
} }

View file

@ -219,4 +219,39 @@ void bpmp_clk_rate_set(bpmp_freq_t fid)
} }
} }
// The following functions halt BPMP to reduce power while sleeping.
// They are not as accurate as RTC at big values but they guarantee time+ delay.
void bpmp_usleep(u32 us)
{
u32 delay;
// Each iteration takes 1us.
while (us)
{
delay = (us > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : us;
us -= delay;
FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_USEC | delay;
}
}
void bpmp_msleep(u32 ms)
{
u32 delay;
// Iteration time is variable. ~200 - 1000us.
while (ms)
{
delay = (ms > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : ms;
ms -= delay;
FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_MSEC | delay;
}
}
void bpmp_halt()
{
FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_JTAG;
}
#pragma GCC pop_options #pragma GCC pop_options

View file

@ -47,5 +47,8 @@ void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
void bpmp_mmu_enable(); void bpmp_mmu_enable();
void bpmp_mmu_disable(); void bpmp_mmu_disable();
void bpmp_clk_rate_set(bpmp_freq_t fid); void bpmp_clk_rate_set(bpmp_freq_t fid);
void bpmp_usleep(u32 us);
void bpmp_msleep(u32 ms);
void bpmp_halt();
#endif #endif

View file

@ -19,19 +19,6 @@
#include "../utils/types.h" #include "../utils/types.h"
/*! Flow controller registers. */
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
#define FLOW_CTLR_HALT_COP_EVENTS 0x4
#define FLOW_CTLR_CPU0_CSR 0x8
#define FLOW_CTLR_CPU1_CSR 0x18
#define FLOW_CTLR_CPU2_CSR 0x20
#define FLOW_CTLR_CPU3_CSR 0x28
#define FLOW_CTLR_RAM_REPAIR 0x40
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
void cluster_boot_cpu0(u32 entry); void cluster_boot_cpu0(u32 entry);
#endif #endif

View file

@ -188,4 +188,24 @@
#define EMC_HEKA_UPD (1 << 30) #define EMC_HEKA_UPD (1 << 30)
#define EMC_SEPT_RUN (1 << 31) #define EMC_SEPT_RUN (1 << 31)
/*! Flow controller registers. */
#define FLOW_CTLR_HALT_COP_EVENTS 0x4
#define HALT_COP_SEC (1 << 23)
#define HALT_COP_MSEC (1 << 24)
#define HALT_COP_USEC (1 << 25)
#define HALT_COP_JTAG (1 << 28)
#define HALT_COP_WAIT_EVENT (1 << 30)
#define HALT_COP_WAIT_IRQ (1 << 31)
#define HALT_COP_MAX_CNT 0xFF
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
#define FLOW_CTLR_CPU0_CSR 0x8
#define FLOW_CTLR_CPU1_CSR 0x18
#define FLOW_CTLR_CPU2_CSR 0x20
#define FLOW_CTLR_CPU3_CSR 0x28
#define FLOW_CTLR_RAM_REPAIR 0x40
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
#endif #endif

View file

@ -23,6 +23,8 @@
#include "../soc/pmc.h" #include "../soc/pmc.h"
#include "../soc/t210.h" #include "../soc/t210.h"
#define USE_RTC_TIMER
extern void sd_unmount(bool deinit); extern void sd_unmount(bool deinit);
u32 get_tmr_s() u32 get_tmr_s()
@ -34,7 +36,7 @@ u32 get_tmr_ms()
{ {
// The registers must be read with the following order: // The registers must be read with the following order:
// RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC) // RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC)
return (RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10)); return (RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000));
} }
u32 get_tmr_us() u32 get_tmr_us()
@ -42,19 +44,28 @@ u32 get_tmr_us()
return TMR(TIMERUS_CNTR_1US); //TIMERUS_CNTR_1US return TMR(TIMERUS_CNTR_1US); //TIMERUS_CNTR_1US
} }
void msleep(u32 milliseconds) void msleep(u32 ms)
{ {
u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10); #ifdef USE_RTC_TIMER
while (((RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10)) - start) <= milliseconds) u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000);
// Casting to u32 is important!
while (((u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000)) - start) <= ms)
; ;
#else
bpmp_msleep(ms);
#endif
} }
void usleep(u32 microseconds) void usleep(u32 us)
{ {
#ifdef USE_RTC_TIMER
u32 start = TMR(TIMERUS_CNTR_1US); u32 start = TMR(TIMERUS_CNTR_1US);
// Casting to u32 is important! // Casting to u32 is important!
while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= microseconds) while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= us)
; ;
#else
bpmp_usleep(us);
#endif
} }
void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops) void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops)
@ -75,7 +86,6 @@ void panic(u32 val)
while (true) while (true)
usleep(1); usleep(1);
} }
void reboot_normal() void reboot_normal()
@ -99,7 +109,7 @@ void reboot_rcm()
PMC(APBDEV_PMC_CNTRL) |= PMC_CNTRL_MAIN_RST; PMC(APBDEV_PMC_CNTRL) |= PMC_CNTRL_MAIN_RST;
while (true) while (true)
usleep(1); bpmp_halt();
} }
void power_off() void power_off()
@ -110,5 +120,5 @@ void power_off()
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF); i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF);
while (true) while (true)
usleep(1); bpmp_halt();
} }

View file

@ -46,8 +46,8 @@ typedef struct _nyx_storage_t
u32 get_tmr_us(); u32 get_tmr_us();
u32 get_tmr_ms(); u32 get_tmr_ms();
u32 get_tmr_s(); u32 get_tmr_s();
void usleep(u32 ticks); void usleep(u32 us);
void msleep(u32 milliseconds); void msleep(u32 ms);
void panic(u32 val); void panic(u32 val);
void reboot_normal(); void reboot_normal();
void reboot_rcm(); void reboot_rcm();