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bdk: sdmmc: add driver type set support

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CTCaer 2023-03-31 09:04:10 +03:00
parent d258c82d52
commit f4bf48e76a
3 changed files with 32 additions and 0 deletions
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22
bdk/storage/sdmmc.c
View file

@ -1030,6 +1030,28 @@ static void _sd_storage_set_power_limit(sdmmc_storage_t *storage, u16 power_limi
} }
} }
int _sd_storage_set_driver_type(sdmmc_storage_t *storage, u32 driver, u8 *buf)
{
if (!_sd_storage_switch(storage, buf, SD_SWITCH_CHECK, SD_SWITCH_GRP_DRVSTR, driver))
return 0;
u32 driver_out = buf[15] & 0xF;
if (driver_out != driver)
return 0;
DPRINTF("[SD] supports Driver Strength %d\n", driver);
if (!_sd_storage_switch(storage, buf, SD_SWITCH_SET, SD_SWITCH_GRP_DRVSTR, driver))
return 0;
if (driver_out != (buf[15] & 0xF))
return 0;
DPRINTF("[SD] card accepted Driver Strength %d\n", driver);
sdmmc_setup_drv_type(storage->sdmmc, driver);
return 1;
}
/* /*
* SD Card DDR200 (DDR208) support * SD Card DDR200 (DDR208) support
* *

7
bdk/storage/sdmmc_driver.c
View file

@ -297,6 +297,13 @@ static void _sdmmc_reset_all(sdmmc_t *sdmmc)
; ;
} }
void sdmmc_setup_drv_type(sdmmc_t *sdmmc, u32 type)
{
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_DRV_TYPE_MASK)) | SDHCI_CTRL_DRV_TYPE(type);
_sdmmc_commit_changes(sdmmc);
}
int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type) int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
{ {
// Disable the SD clock if it was enabled, and reenable it later. // Disable the SD clock if it was enabled, and reenable it later.

3
bdk/storage/sdmmc_driver.h
View file

@ -120,10 +120,12 @@
/*! SDMMC host control 2. 0x3E. */ /*! SDMMC host control 2. 0x3E. */
#define SDHCI_CTRL_UHS_MASK 0x7 #define SDHCI_CTRL_UHS_MASK 0x7
#define SDHCI_CTRL_VDD_180 BIT(3) #define SDHCI_CTRL_VDD_180 BIT(3)
#define SDHCI_CTRL_DRV_TYPE_MASK (3U << 4)
#define SDHCI_CTRL_DRV_TYPE_B (0U << 4) #define SDHCI_CTRL_DRV_TYPE_B (0U << 4)
#define SDHCI_CTRL_DRV_TYPE_A (1U << 4) #define SDHCI_CTRL_DRV_TYPE_A (1U << 4)
#define SDHCI_CTRL_DRV_TYPE_C (2U << 4) #define SDHCI_CTRL_DRV_TYPE_C (2U << 4)
#define SDHCI_CTRL_DRV_TYPE_D (3U << 4) #define SDHCI_CTRL_DRV_TYPE_D (3U << 4)
#define SDHCI_CTRL_DRV_TYPE(type) ((type) << 4)
#define SDHCI_CTRL_EXEC_TUNING BIT(6) #define SDHCI_CTRL_EXEC_TUNING BIT(6)
#define SDHCI_CTRL_TUNED_CLK_SHIFT 7 #define SDHCI_CTRL_TUNED_CLK_SHIFT 7
#define SDHCI_CTRL_TUNED_CLK BIT(7) #define SDHCI_CTRL_TUNED_CLK BIT(7)
@ -317,6 +319,7 @@ int sdmmc_get_io_power(sdmmc_t *sdmmc);
u32 sdmmc_get_bus_width(sdmmc_t *sdmmc); u32 sdmmc_get_bus_width(sdmmc_t *sdmmc);
void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width); void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width);
void sdmmc_save_tap_value(sdmmc_t *sdmmc); void sdmmc_save_tap_value(sdmmc_t *sdmmc);
void sdmmc_setup_drv_type(sdmmc_t *sdmmc, u32 type);
int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type); int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type);
void sdmmc_card_clock_powersave(sdmmc_t *sdmmc, int powersave_enable); void sdmmc_card_clock_powersave(sdmmc_t *sdmmc, int powersave_enable);
int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type); int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type);