diff --git a/bdk/mem/mc.c b/bdk/mem/mc.c index d577bd7..31af89c 100644 --- a/bdk/mem/mc.c +++ b/bdk/mem/mc.c @@ -21,8 +21,6 @@ #include #include -//#define CONFIG_ENABLE_AHB_REDIRECT - void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock) { MC(MC_SEC_CARVEOUT_BOM) = bom; @@ -125,13 +123,13 @@ void mc_config_carveout() MC(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F; } -void mc_enable_ahb_redirect(bool full_aperture) +void mc_enable_ahb_redirect() { // Enable ARC_CLK_OVR_ON. - CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = (CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) & 0xFFF7FFFF) | 0x80000; - //MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE; - MC(MC_IRAM_BOM) = 0x40000000; - MC(MC_IRAM_TOM) = full_aperture ? DRAM_START : 0x4003F000; + CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) |= BIT(19); + //MC(MC_IRAM_REG_CTRL) &= ~BIT(0); + MC(MC_IRAM_BOM) = IRAM_BASE; + MC(MC_IRAM_TOM) = DRAM_START; // Default is only IRAM: 0x4003F000. } void mc_disable_ahb_redirect() @@ -139,15 +137,27 @@ void mc_disable_ahb_redirect() MC(MC_IRAM_BOM) = 0xFFFFF000; MC(MC_IRAM_TOM) = 0; // Disable IRAM_CFG_WRITE_ACCESS (sticky). - //MC(MC_IRAM_REG_CTRL) = MC(MC_IRAM_REG_CTRL) & 0xFFFFFFFE | 1; + //MC(MC_IRAM_REG_CTRL) |= BIT(0); // Disable ARC_CLK_OVR_ON. - CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= 0xFFF7FFFF; + CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= ~BIT(19); +} + +bool mc_client_has_access(void *address) +{ + // Check if address is in DRAM or if arbitration for IRAM is enabled. + if ((u32)address >= DRAM_START) + return true; // Access by default. + else if ((u32)address >= IRAM_BASE && MC(MC_IRAM_BOM) == IRAM_BASE) + return true; // Access by AHB arbitration. + + // No access to address space. + return false; } void mc_enable() { // Reset EMC source to PLLP. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | 0x40000000; + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | (2 << 29); // Enable memory clocks. CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC); CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MEM); @@ -156,7 +166,7 @@ void mc_enable() CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM); usleep(5); -#ifdef CONFIG_ENABLE_AHB_REDIRECT +#ifdef BDK_MC_ENABLE_AHB_REDIRECT mc_enable_ahb_redirect(); #else mc_disable_ahb_redirect(); diff --git a/bdk/mem/mc.h b/bdk/mem/mc.h index d873c7d..300bbfd 100644 --- a/bdk/mem/mc.h +++ b/bdk/mem/mc.h @@ -23,8 +23,9 @@ void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock); void mc_config_carveout(); void mc_config_carveout_finalize(); -void mc_enable_ahb_redirect(bool full_aperture); +void mc_enable_ahb_redirect(); void mc_disable_ahb_redirect(); +bool mc_client_has_access(void *address); void mc_enable(); #endif diff --git a/bdk/sec/tsec.c b/bdk/sec/tsec.c index 50a90ae..6d6f895 100644 --- a/bdk/sec/tsec.c +++ b/bdk/sec/tsec.c @@ -95,7 +95,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) pmc_enable_partition(POWER_RAIL_CE3, DISABLE); // Enable AHB aperture and set it to full mmio. - mc_enable_ahb_redirect(true); + mc_enable_ahb_redirect(); } // Configure Falcon. @@ -287,11 +287,10 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) memcpy(tsec_keys, &buf, SE_KEY_128_SIZE); } -out_free:; +out_free: free(fwbuf); -out:; - +out: // Disable clocks. clock_disable_kfuse(); clock_disable_sor1(); @@ -301,9 +300,5 @@ out:; bpmp_mmu_enable(); bpmp_clk_rate_set(prev_fid); - // Disable AHB aperture. - if (type == TSEC_FW_TYPE_NEW) - mc_disable_ahb_redirect(); - return res; } diff --git a/bdk/storage/sdmmc.c b/bdk/storage/sdmmc.c index 8980d61..54cbbf1 100644 --- a/bdk/storage/sdmmc.c +++ b/bdk/storage/sdmmc.c @@ -327,8 +327,8 @@ out: int sdmmc_storage_read(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf) { - // Ensure that buffer resides in DRAM and it's DMA aligned. - if (((u32)buf >= DRAM_START) && !((u32)buf % 8)) + // Ensure that SDMMC has access to buffer and it's SDMMC DMA aligned. + if (mc_client_has_access(buf) && !((u32)buf % 8)) return _sdmmc_storage_readwrite(storage, sector, num_sectors, buf, 0); if (num_sectors > (SDMMC_UP_BUF_SZ / 512)) @@ -345,8 +345,8 @@ int sdmmc_storage_read(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, vo int sdmmc_storage_write(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf) { - // Ensure that buffer resides in DRAM and it's DMA aligned. - if (((u32)buf >= DRAM_START) && !((u32)buf % 8)) + // Ensure that SDMMC has access to buffer and it's SDMMC DMA aligned. + if (mc_client_has_access(buf) && !((u32)buf % 8)) return _sdmmc_storage_readwrite(storage, sector, num_sectors, buf, 1); if (num_sectors > (SDMMC_UP_BUF_SZ / 512)) diff --git a/bdk/usb/xusbd.c b/bdk/usb/xusbd.c index 0f68ec7..8556ee5 100644 --- a/bdk/usb/xusbd.c +++ b/bdk/usb/xusbd.c @@ -881,7 +881,7 @@ int xusb_device_init() _xusbd_init_device_clocks(); // Enable AHB redirect for access to IRAM for Event/EP ring buffers. - mc_enable_ahb_redirect(false); // Can be skipped if IRAM is not used. + mc_enable_ahb_redirect(); // Enable XUSB device IPFS. XUSB_DEV_DEV(XUSB_DEV_CONFIGURATION) |= DEV_CONFIGURATION_EN_FPCI; @@ -1912,7 +1912,6 @@ void xusb_end(bool reset_ep, bool only_controller) CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = BIT(CLK_W_XUSB_PADCTL); CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = BIT(CLK_W_XUSB); CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = BIT(CLK_W_XUSB); - mc_disable_ahb_redirect(); // Can be skipped if IRAM is not used. } int xusb_handle_ep0_ctrl_setup()