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https://github.com/CTCaer/hekate
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pmc: Add latest pmc secure scratch lock
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parent
a85891ae00
commit
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3 changed files with 77 additions and 30 deletions
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@ -14,10 +14,68 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#include <soc/hw_init.h>
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#include <soc/pmc.h>
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#include <soc/pmc.h>
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#include <soc/t210.h>
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#include <soc/t210.h>
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#include <utils/util.h>
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#include <utils/util.h>
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void pmc_scratch_lock(pmc_sec_lock_t lock_mask)
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{
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// Lock Private key disable, Fuse write enable, MC carveout, Warmboot PA id and Warmboot address.
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if (lock_mask & PMC_SEC_LOCK_MISC)
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{
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PMC(APBDEV_PMC_SEC_DISABLE) |= 0x700FF0; // RW lock: 0-3.
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PMC(APBDEV_PMC_SEC_DISABLE2) |= 0xFC000000; // RW lock: 21-23.
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PMC(APBDEV_PMC_SEC_DISABLE3) |= 0x3F0FFF00; // RW lock: 28-33, 36-38.
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PMC(APBDEV_PMC_SEC_DISABLE6) |= 0xC000000; // RW lock: 85.
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PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xFF00FF00; // RW lock: 108-111, 116-119.
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// SE2 context.
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if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01)
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{
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PMC(APBDEV_PMC_SEC_DISABLE9) |= 0x3FF; // RW lock: 120-124. (0xB38)
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PMC(APBDEV_PMC_SEC_DISABLE10) = 0xFFFFFFFF; // RW lock: 135-150.
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}
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}
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if (lock_mask & PMC_SEC_LOCK_LP0_PARAMS)
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{
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PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x3FCFFFF; // RW lock: 8-15, 17-20.
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PMC(APBDEV_PMC_SEC_DISABLE4) |= 0x3F3FFFFF; // RW lock: 40-50, 52-54.
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PMC(APBDEV_PMC_SEC_DISABLE5) = 0xFFFFFFFF; // RW lock: 56-71.
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PMC(APBDEV_PMC_SEC_DISABLE6) |= 0xF3FFC00F; // RW lock: 72-73, 79-84, 86-87.
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PMC(APBDEV_PMC_SEC_DISABLE7) |= 0x3FFFFF; // RW lock: 88-98.
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PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xFF; // RW lock: 104-107.
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}
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if (lock_mask & PMC_SEC_LOCK_RST_VECTOR)
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PMC(APBDEV_PMC_SEC_DISABLE3) |= 0xF00000; // RW lock: 34-35.
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if (lock_mask & PMC_SEC_LOCK_CARVEOUTS)
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{
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PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x30000; // RW lock: 16.
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PMC(APBDEV_PMC_SEC_DISABLE3) |= 0xC0000000; // RW lock: 39.
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PMC(APBDEV_PMC_SEC_DISABLE4) |= 0xC0C00000; // RW lock: 51, 55.
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PMC(APBDEV_PMC_SEC_DISABLE6) |= 0x3FF0; // RW lock: 74-78.
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PMC(APBDEV_PMC_SEC_DISABLE7) |= 0xFFC00000; // RW lock: 99-103.
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}
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if (lock_mask & PMC_SEC_LOCK_TZ_CMAC_W)
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PMC(APBDEV_PMC_SEC_DISABLE8) |= 0x550000; // W lock: 112-115.
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if (lock_mask & PMC_SEC_LOCK_TZ_CMAC_R)
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PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xAA0000; // R lock: 112-115.
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if (lock_mask & PMC_SEC_LOCK_TZ_KEK_W)
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PMC(APBDEV_PMC_SEC_DISABLE3) |= 0x55; // W lock: 24-27.
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if (lock_mask & PMC_SEC_LOCK_TZ_KEK_R)
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PMC(APBDEV_PMC_SEC_DISABLE3) |= 0xAA; // R lock: 24-27.
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if (lock_mask & PMC_SEC_LOCK_SE_SRK)
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PMC(APBDEV_PMC_SEC_DISABLE) |= 0xFF000; // RW lock: 4-7
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}
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int pmc_enable_partition(u32 part, int enable)
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int pmc_enable_partition(u32 part, int enable)
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{
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{
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u32 part_mask = BIT(part);
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u32 part_mask = BIT(part);
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@ -91,6 +91,8 @@
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#define APBDEV_PMC_SEC_DISABLE6 0x5B8
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#define APBDEV_PMC_SEC_DISABLE6 0x5B8
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#define APBDEV_PMC_SEC_DISABLE7 0x5BC
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#define APBDEV_PMC_SEC_DISABLE7 0x5BC
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#define APBDEV_PMC_SEC_DISABLE8 0x5C0
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#define APBDEV_PMC_SEC_DISABLE8 0x5C0
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#define APBDEV_PMC_SEC_DISABLE9 0x5C4
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#define APBDEV_PMC_SEC_DISABLE10 0x5C8
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#define APBDEV_PMC_SCRATCH188 0x810
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#define APBDEV_PMC_SCRATCH188 0x810
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#define APBDEV_PMC_SCRATCH190 0x818
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#define APBDEV_PMC_SCRATCH190 0x818
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#define APBDEV_PMC_SCRATCH200 0x840
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#define APBDEV_PMC_SCRATCH200 0x840
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@ -98,6 +100,20 @@
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#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
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#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
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#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0
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#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0
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int pmc_enable_partition(u32 part, int enable);
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typedef enum _pmc_sec_lock_t
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{
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PMC_SEC_LOCK_MISC = BIT(0),
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PMC_SEC_LOCK_LP0_PARAMS = BIT(1),
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PMC_SEC_LOCK_RST_VECTOR = BIT(2),
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PMC_SEC_LOCK_CARVEOUTS = BIT(3),
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PMC_SEC_LOCK_TZ_CMAC_W = BIT(4),
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PMC_SEC_LOCK_TZ_CMAC_R = BIT(5),
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PMC_SEC_LOCK_TZ_KEK_W = BIT(6),
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PMC_SEC_LOCK_TZ_KEK_R = BIT(7),
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PMC_SEC_LOCK_SE_SRK = BIT(8),
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} pmc_sec_lock_t;
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void pmc_scratch_lock(pmc_sec_lock_t lock_mask);
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int pmc_enable_partition(u32 part, int enable);
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#endif
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#endif
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@ -152,33 +152,6 @@ static void _se_lock(bool lock_se)
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gfx_hexdump(SE_BASE, (void *)SE_BASE, 0x400);*/
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gfx_hexdump(SE_BASE, (void *)SE_BASE, 0x400);*/
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}
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}
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void _pmc_scratch_lock(u32 kb)
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{
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switch (kb)
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{
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case KB_FIRMWARE_VERSION_100_200:
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case KB_FIRMWARE_VERSION_300:
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case KB_FIRMWARE_VERSION_301:
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PMC(APBDEV_PMC_SEC_DISABLE) = 0x7FFFF3;
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PMC(APBDEV_PMC_SEC_DISABLE2) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE3) = 0xFFAFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE4) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE5) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE6) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE7) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE8) = 0xFFAAFFFF;
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break;
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default:
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PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x3FCFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE4) |= 0x3F3FFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE5) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE6) |= 0xF3FFC00F;
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PMC(APBDEV_PMC_SEC_DISABLE7) |= 0x3FFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xFF;
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break;
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}
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}
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void _sysctr0_reset()
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void _sysctr0_reset()
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{
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{
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SYSCTR0(SYSCTR0_CNTCR) = 0;
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SYSCTR0(SYSCTR0_CNTCR) = 0;
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@ -1090,8 +1063,8 @@ int hos_launch(ini_sec_t *cfg)
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if (kb >= KB_FIRMWARE_VERSION_620)
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if (kb >= KB_FIRMWARE_VERSION_620)
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_sysctr0_reset();
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_sysctr0_reset();
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// < 4.0.0 pkg1.1 locks PMC scratches.
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// NX Bootloader locks LP0 Carveout secure scratch registers.
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//_pmc_scratch_lock(kb);
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//pmc_scratch_lock(PMC_SEC_LOCK_LP0_PARAMS);
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// Set secmon mailbox address and clear it.
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// Set secmon mailbox address and clear it.
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if (kb >= KB_FIRMWARE_VERSION_700 || exo_new)
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if (kb >= KB_FIRMWARE_VERSION_700 || exo_new)
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