From e158d9bc002039e59e9af94b34056ff89116501a Mon Sep 17 00:00:00 2001 From: CTCaer Date: Fri, 17 Jul 2020 16:50:17 +0300 Subject: [PATCH] clk: Refactor CLK devices bits --- bdk/gfx/di.c | 30 ++--- bdk/mem/mc.c | 13 +-- bdk/mem/sdram.c | 7 +- bdk/soc/ccplex.c | 6 +- bdk/soc/clock.c | 134 +++++++++------------- bdk/soc/clock.h | 263 +++++++++++++++++++++++++++++++++++++++++++ bdk/soc/hw_init.c | 82 ++++++++++---- bdk/usb/usbd.c | 16 +-- bdk/utils/types.h | 1 + bootloader/hos/hos.c | 2 +- 10 files changed, 414 insertions(+), 140 deletions(-) diff --git a/bdk/gfx/di.c b/bdk/gfx/di.c index 1549e7b..8b4758f 100644 --- a/bdk/gfx/di.c +++ b/bdk/gfx/di.c @@ -64,28 +64,28 @@ void display_init() i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO7, MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DRV_PUSHPULL); // Enable Display Interface specific clocks. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x1010000; // Clear reset DSI, MIPI_CAL. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x1010000; // Set enable clock DSI, MIPI_CAL. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI); - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; // Clear reset DISP1, HOST1X. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = 0x18000000; // Set enable clock DISP1, HOST1X. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x20000; // Set enable clock UART_FST_MIPI_CAL. + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_UART_FST_MIPI_CAL); CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = 10; // Set PLLP_OUT3 and div 6 (17MHz). - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000; // Set enable clock DSIA_LP. + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = BIT(CLK_W_DSIA_LP); CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10; // Set PLLP_OUT and div 6 (68MHz). // Disable deep power down. - PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000; + PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000; PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000; // Config LCD and Backlight pins. - PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN - PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE; // PULL_DOWN + PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN + PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE; // PULL_DOWN PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; // PULL_DOWN | 1 - PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN - PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE; // PULL_DOWN + PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN + PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE; // PULL_DOWN // Set Backlight +-5V pins mode and direction gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO); @@ -305,10 +305,10 @@ void display_end() usleep(10000); // Disable Display Interface specific clocks. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x1010000; // Set reset clock DSI, MIPI_CAL. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = 0x1010000; // Clear enable clock DSI, MIPI_CAL. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000; // Set reset DISP1, HOST1X. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = 0x18000000; // Clear enable DISP1, HOST1X. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); // Power down pads. DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF); diff --git a/bdk/mem/mc.c b/bdk/mem/mc.c index 8a0da1a..cc136dc 100644 --- a/bdk/mem/mc.c +++ b/bdk/mem/mc.c @@ -144,13 +144,12 @@ void mc_disable_ahb_redirect() void mc_enable() { CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | 0x40000000; - // Enable EMC clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFDFFFFFF) | 0x2000000; - // Enable MC clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE) | 1; - // Enable EMC DLL clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF) | 0x4000; - CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x2000001; //Clear EMC and MC reset. + // Enable memory clocks. + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & ~BIT(CLK_H_EMC)) | BIT(CLK_H_EMC); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & ~BIT(CLK_H_MEM)) | BIT(CLK_H_MEM); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & ~BIT(CLK_X_EMC_DLL)) | BIT(CLK_X_EMC_DLL); + // Clear clock resets for memory. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM); usleep(5); //#ifdef CONFIG_ENABLE_AHB_REDIRECT diff --git a/bdk/mem/sdram.c b/bdk/mem/sdram.c index e58a1eb..230b087 100644 --- a/bdk/mem/sdram.c +++ b/bdk/mem/sdram.c @@ -143,9 +143,10 @@ break_nosleep: if (params->clear_clock2_mc1) CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = 0x40000000; // Clear Reset to MC1. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x2000001; // Enable EMC and MEM clocks. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x4000; // Enable EMC_DLL clock. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x2000001; // Clear EMC and MEM resets. + // Enable and clear reset for memory clocks. + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_EMC_DLL); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM); // Set pad macros. EMC(EMC_PMACRO_VTTGEN_CTRL_0) = params->emc_pmacro_vttgen_ctrl0; diff --git a/bdk/soc/ccplex.c b/bdk/soc/ccplex.c index 24a4787..785cdc8 100644 --- a/bdk/soc/ccplex.c +++ b/bdk/soc/ccplex.c @@ -94,12 +94,12 @@ void ccplex_boot_cpu0(u32 entry) // Configure MSELECT source and enable clock. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6; - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & 0xFFFFFFF7) | 8; + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & ~BIT(CLK_V_MSELECT)) | BIT(CLK_V_MSELECT); // Configure initial CPU clock frequency and enable clock. CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888; CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000; - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = 1; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_CPUG); clock_enable_coresight(); @@ -131,7 +131,7 @@ void ccplex_boot_cpu0(u32 entry) // MC(MC_TZ_SECURITY_CTRL) = 1; // Clear MSELECT reset. - CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7; + CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= ~BIT(CLK_V_MSELECT); // Clear NONCPU reset. CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000; // Clear CPU0 reset. diff --git a/bdk/soc/clock.c b/bdk/soc/clock.c index 41e69a2..7ed36fb 100644 --- a/bdk/soc/clock.c +++ b/bdk/soc/clock.c @@ -34,63 +34,63 @@ /* clock_t: reset, enable, source, index, clk_src, clk_div */ static const clock_t _clock_uart[] = { -/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 2 }, -/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 2 }, -/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 23, 0, 2 }, -/* UART D */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD, 1, 0, 2 }, -/* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 } + { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, CLK_L_UARTA, 0, 2 }, + { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, CLK_L_UARTB, 0, 2 }, + { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, CLK_H_UARTC, 0, 2 }, + { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD, CLK_U_UARTD, 0, 2 }, + { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, CLK_Y_UARTAPE, 0, 2 } }; //I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0, FM_DIV: 26. static const clock_t _clock_i2c[] = { -/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz -/* I2C2 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, 22, 0, 4 }, //81.6MHz -> 400KHz -/* I2C3 */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, 3, 0, 4 }, //81.6MHz -> 400KHz -/* I2C4 */ { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, 7, 0, 19 }, //20.4MHz -> 100KHz -/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 15, 0, 4 }, //81.6MHz -> 400KHz -/* I2C6 */ { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, 6, 0, 19 } //20.4MHz -> 100KHz + { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, CLK_L_I2C1, 0, 19 }, //20.4MHz -> 100KHz + { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, CLK_H_I2C2, 0, 4 }, //81.6MHz -> 400KHz + { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, CLK_U_I2C3, 0, 4 }, //81.6MHz -> 400KHz + { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, CLK_V_I2C4, 0, 19 }, //20.4MHz -> 100KHz + { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, CLK_H_I2C5, 0, 4 }, //81.6MHz -> 400KHz + { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, CLK_X_I2C6, 0, 19 } //20.4MHz -> 100KHz }; static clock_t _clock_se = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 31, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, CLK_V_SE, 0, 0 }; static clock_t _clock_tzram = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, 30, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, CLK_V_TZRAM, 0, 0 }; static clock_t _clock_host1x = { - CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 28, 4, 3 + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, CLK_L_HOST1X, 4, 3 }; static clock_t _clock_tsec = { - CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 19, 0, 2 + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, CLK_U_TSEC, 0, 2 }; static clock_t _clock_sor_safe = { - CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, 30, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, CLK_Y_SOR_SAFE, 0, 0 }; static clock_t _clock_sor0 = { - CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, 22, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, CLK_X_SOR0, 0, 0 }; static clock_t _clock_sor1 = { - CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 23, 0, 2 + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, CLK_X_SOR1, 0, 2 }; static clock_t _clock_kfuse = { - CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, 8, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_KFUSE, 0, 0 }; static clock_t _clock_cl_dvfs = { - CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, 27, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, CLK_W_DVFS, 0, 0 }; static clock_t _clock_coresight = { - CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4 + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, CLK_U_CSITE, 0, 4 }; static clock_t _clock_pwm = { - CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Fref: 6.2MHz. + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, CLK_L_PWM, 6, 4 // Fref: 6.2MHz. }; static clock_t _clock_sdmmc_legacy_tm = { - CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, 1, 4, 66 + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, CLK_Y_SDMMC_LEGACY_TM, 4, 66 }; void clock_enable(const clock_t *clk) @@ -223,12 +223,12 @@ void clock_disable_sor1() void clock_enable_kfuse() { - //clock_enable(&_clock_kfuse); - CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) = (CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) & 0xFFFFFEFF) | 0x100; - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) &= 0xFFFFFEFF; - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) & 0xFFFFFEFF) | 0x100; + u32 kfuse_clk_unmask = ~BIT(CLK_H_KFUSE); + CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) = (CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) & kfuse_clk_unmask) | BIT(CLK_H_KFUSE); + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) &= kfuse_clk_unmask; + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) & kfuse_clk_unmask) | BIT(CLK_H_KFUSE); usleep(10); - CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= 0xFFFFFEFF; + CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= kfuse_clk_unmask; usleep(20); } @@ -362,48 +362,18 @@ static void _clock_disable_pllc4(u32 mask) pllc4_enabled = 0; } -#define L_SWR_SDMMC1_RST (1 << 14) -#define L_SWR_SDMMC2_RST (1 << 9) -#define L_SWR_SDMMC4_RST (1 << 15) -#define U_SWR_SDMMC3_RST (1 << 5) - -#define L_CLK_ENB_SDMMC1 (1 << 14) -#define L_CLK_ENB_SDMMC2 (1 << 9) -#define L_CLK_ENB_SDMMC4 (1 << 15) -#define U_CLK_ENB_SDMMC3 (1 << 5) - -#define L_SET_SDMMC1_RST (1 << 14) -#define L_SET_SDMMC2_RST (1 << 9) -#define L_SET_SDMMC4_RST (1 << 15) -#define U_SET_SDMMC3_RST (1 << 5) - -#define L_CLR_SDMMC1_RST (1 << 14) -#define L_CLR_SDMMC2_RST (1 << 9) -#define L_CLR_SDMMC4_RST (1 << 15) -#define U_CLR_SDMMC3_RST (1 << 5) - -#define L_SET_CLK_ENB_SDMMC1 (1 << 14) -#define L_SET_CLK_ENB_SDMMC2 (1 << 9) -#define L_SET_CLK_ENB_SDMMC4 (1 << 15) -#define U_SET_CLK_ENB_SDMMC3 (1 << 5) - -#define L_CLR_CLK_ENB_SDMMC1 (1 << 14) -#define L_CLR_CLK_ENB_SDMMC2 (1 << 9) -#define L_CLR_CLK_ENB_SDMMC4 (1 << 15) -#define U_CLR_CLK_ENB_SDMMC3 (1 << 5) - static int _clock_sdmmc_is_reset(u32 id) { switch (id) { case SDMMC_1: - return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC1_RST; + return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & BIT(CLK_L_SDMMC1); case SDMMC_2: - return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC2_RST; + return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & BIT(CLK_L_SDMMC2); case SDMMC_3: - return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_U) & U_SWR_SDMMC3_RST; + return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_U) & BIT(CLK_U_SDMMC3); case SDMMC_4: - return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC4_RST; + return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & BIT(CLK_L_SDMMC4); } return 0; } @@ -413,16 +383,16 @@ static void _clock_sdmmc_set_reset(u32 id) switch (id) { case SDMMC_1: - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC1_RST; + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_SDMMC1); break; case SDMMC_2: - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC2_RST; + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_SDMMC2); break; case SDMMC_3: - CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = U_SET_SDMMC3_RST; + CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = BIT(CLK_U_SDMMC3); break; case SDMMC_4: - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC4_RST; + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_SDMMC4); break; } } @@ -432,16 +402,16 @@ static void _clock_sdmmc_clear_reset(u32 id) switch (id) { case SDMMC_1: - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC1_RST; + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_SDMMC1); break; case SDMMC_2: - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC2_RST; + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_SDMMC2); break; case SDMMC_3: - CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_CLR) = U_CLR_SDMMC3_RST; + CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_CLR) = BIT(CLK_U_SDMMC3); break; case SDMMC_4: - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC4_RST; + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_SDMMC4); break; } } @@ -451,13 +421,13 @@ static int _clock_sdmmc_is_enabled(u32 id) switch (id) { case SDMMC_1: - return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC1; + return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & BIT(CLK_L_SDMMC1); case SDMMC_2: - return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC2; + return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & BIT(CLK_L_SDMMC2); case SDMMC_3: - return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) & U_CLK_ENB_SDMMC3; + return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) & BIT(CLK_U_SDMMC3); case SDMMC_4: - return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC4; + return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & BIT(CLK_L_SDMMC4); } return 0; } @@ -467,16 +437,16 @@ static void _clock_sdmmc_set_enable(u32 id) switch (id) { case SDMMC_1: - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC1; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_SDMMC1); break; case SDMMC_2: - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC2; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_SDMMC2); break; case SDMMC_3: - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_SET) = U_SET_CLK_ENB_SDMMC3; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_SET) = BIT(CLK_U_SDMMC3); break; case SDMMC_4: - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC4; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_SDMMC4); break; } } @@ -486,16 +456,16 @@ static void _clock_sdmmc_clear_enable(u32 id) switch (id) { case SDMMC_1: - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC1; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_SDMMC1); break; case SDMMC_2: - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC2; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_SDMMC2); break; case SDMMC_3: - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = U_CLR_CLK_ENB_SDMMC3; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = BIT(CLK_U_SDMMC3); break; case SDMMC_4: - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC4; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_SDMMC4); break; } } diff --git a/bdk/soc/clock.h b/bdk/soc/clock.h index bbcd482..3edb5e8 100644 --- a/bdk/soc/clock.h +++ b/bdk/soc/clock.h @@ -171,6 +171,269 @@ #define PLLC4_OUT3_CLKEN (1 << 1) #define PLLC4_OUT3_RSTN_CLR (1 << 0) +/* + * CLOCK Peripherals: + * L 0 - 31 + * H 32 - 63 + * U 64 - 95 + * V 96 - 127 + * W 128 - 159 + * X 160 - 191 + * Y 192 - 223 + */ + +enum CLK_L_DEV +{ + CLK_L_CPU = 0, // Only reset. Deprecated. + CLK_L_BPMP = 1, // Only reset. + CLK_L_SYS = 2, // Only reset. + CLK_L_ISPB = 3, + CLK_L_RTC = 4, + CLK_L_TMR = 5, + CLK_L_UARTA = 6, + CLK_L_UARTB = 7, + CLK_L_GPIO = 8, + CLK_L_SDMMC2 = 9, + CLK_L_SPDIF = 10, + CLK_L_I2S2 = 11, // I2S1 + CLK_L_I2C1 = 12, + CLK_L_NDFLASH = 13, // HIDDEN. + CLK_L_SDMMC1 = 14, + CLK_L_SDMMC4 = 15, + CLK_L_TWC = 16, // HIDDEN. + CLK_L_PWM = 17, + CLK_L_I2S3 = 18, + CLK_L_EPP = 19, // HIDDEN. + CLK_L_VI = 20, + CLK_L_2D = 21, // HIDDEN. + CLK_L_USBD = 22, + CLK_L_ISP = 23, + CLK_L_3D = 24, // HIDDEN. + //CLK_L_ = 25, + CLK_L_DISP2 = 26, + CLK_L_DISP1 = 27, + CLK_L_HOST1X = 28, + CLK_L_VCP = 29, // HIDDEN. + CLK_L_I2S1 = 30, // I2S0 + CLK_L_BPMP_CACHE_CTRL = 31, // CONTROLLER +}; + +enum CLK_H_DEV +{ + CLK_H_MEM = 0, // MC. + CLK_H_AHBDMA = 1, + CLK_H_APBDMA = 2, + //CLK_H_ = 3, + CLK_H_KBC = 4, // HIDDEN. + CLK_H_STAT_MON = 5, + CLK_H_PMC = 6, + CLK_H_FUSE = 7, + CLK_H_KFUSE = 8, + CLK_H_SPI1 = 9, + CLK_H_SNOR = 10, // HIDDEN. + CLK_H_JTAG2TBC = 11, + CLK_H_SPI2 = 12, + CLK_H_XIO = 13, // HIDDEN. + CLK_H_SPI3 = 14, + CLK_H_I2C5 = 15, + CLK_H_DSI = 16, + //CLK_H_ = 17, + CLK_H_HSI = 18, // HIDDEN. + CLK_H_HDMI = 19, // HIDDEN. + CLK_H_CSI = 20, + //CLK_H_ = 21, + CLK_H_I2C2 = 22, + CLK_H_UARTC = 23, + CLK_H_MIPI_CAL = 24, + CLK_H_EMC = 25, + CLK_H_USB2 = 26, + CLK_H_USB3 = 27, // HIDDEN. + CLK_H_MPE = 28, // HIDDEN. + CLK_H_VDE = 29, // HIDDEN. + CLK_H_BSEA = 30, // HIDDEN. + CLK_H_BSEV = 31, +}; + +enum CLK_U_DEV +{ + //CLK_U_ = 0, + CLK_U_UARTD = 1, + CLK_U_UARTE = 2, // HIDDEN. + CLK_U_I2C3 = 3, + CLK_U_SPI4 = 4, + CLK_U_SDMMC3 = 5, + CLK_U_PCIE = 6, + CLK_U_UNUSED = 7, // RESERVED + CLK_U_AFI = 8, + CLK_U_CSITE = 9, + CLK_U_PCIEXCLK = 10, // Only reset. + CLK_U_BPMPUCQ = 11, // HIDDEN. + CLK_U_LA = 12, + CLK_U_TRACECLKIN = 13, // HIDDEN. + CLK_U_SOC_THERM = 14, + CLK_U_DTV = 15, + CLK_U_NAND_SPEED = 16, // HIDDEN. + CLK_U_I2C_SLOW = 17, + CLK_U_DSIB = 18, + CLK_U_TSEC = 19, + CLK_U_IRAMA = 20, + CLK_U_IRAMB = 21, + CLK_U_IRAMC = 22, + CLK_U_IRAMD = 23, // EMUCIF ON RESET + CLK_U_BPMP_CACHE_RAM = 24, + CLK_U_XUSB_HOST = 25, + CLK_U_CLK_M_DOUBLER = 26, + CLK_U_MSENC = 27, // HIDDEN. + CLK_U_SUS_OUT = 28, + CLK_U_DEV2_OUT = 29, + CLK_U_DEV1_OUT = 30, + CLK_U_XUSB_DEV = 31, +}; + +enum CLK_V_DEV +{ + CLK_V_CPUG = 0, + CLK_V_CPULP = 1, // Reserved. + CLK_V_3D2 = 2, // HIDDEN. + CLK_V_MSELECT = 3, + CLK_V_TSENSOR = 4, + CLK_V_I2S4 = 5, + CLK_V_I2S5 = 6, + CLK_V_I2C4 = 7, + CLK_V_SPI5 = 8, // HIDDEN. + CLK_V_SPI6 = 9, // HIDDEN. + CLK_V_AHUB = 10, // AUDIO. + CLK_V_APB2APE = 11, // APBIF. + CLK_V_DAM0 = 12, // HIDDEN. + CLK_V_DAM1 = 13, // HIDDEN. + CLK_V_DAM2 = 14, // HIDDEN. + CLK_V_HDA2CODEC_2X = 15, + CLK_V_ATOMICS = 16, + //CLK_V_ = 17, + //CLK_V_ = 18, + //CLK_V_ = 19, + //CLK_V_ = 20, + //CLK_V_ = 21, + CLK_V_SPDIF_DOUBLER = 22, + CLK_V_ACTMON = 23, + CLK_V_EXTPERIPH1 = 24, + CLK_V_EXTPERIPH2 = 25, + CLK_V_EXTPERIPH3 = 26, + CLK_V_SATA_OOB = 27, + CLK_V_SATA = 28, + CLK_V_HDA = 29, + CLK_V_TZRAM = 30, // HIDDEN. + CLK_V_SE = 31, // HIDDEN. +}; + +enum CLK_W_DEV +{ + CLK_W_HDA2HDMICODEC = 0, + CLK_W_RESERVED0 = 1, //satacoldrstn + CLK_W_PCIERX0 = 2, + CLK_W_PCIERX1 = 3, + CLK_W_PCIERX2 = 4, + CLK_W_PCIERX3 = 5, + CLK_W_PCIERX4 = 6, + CLK_W_PCIERX5 = 7, + CLK_W_CEC = 8, + CLK_W_PCIE2_IOBIST = 9, + CLK_W_EMC_IOBIST = 10, + CLK_W_HDMI_IOBIST = 11, // HIDDEN. + CLK_W_SATA_IOBIST = 12, + CLK_W_MIPI_IOBIST = 13, + CLK_W_XUSB_PADCTL = 14, // Only reset. + CLK_W_XUSB = 15, + CLK_W_CILAB = 16, + CLK_W_CILCD = 17, + CLK_W_CILEF = 18, + CLK_W_DSIA_LP = 19, + CLK_W_DSIB_LP = 20, + CLK_W_ENTROPY = 21, + CLK_W_DDS = 22, // HIDDEN. + //CLK_W_ = 23, + CLK_W_DP2 = 24, // HIDDEN. + CLK_W_AMX0 = 25, // HIDDEN. + CLK_W_ADX0 = 26, // HIDDEN. + CLK_W_DVFS = 27, + CLK_W_XUSB_SS = 28, + CLK_W_EMC_LATENCY = 29, + CLK_W_MC1 = 30, + //CLK_W_ = 31, +}; + +enum CLK_X_DEV +{ + CLK_X_SPARE = 0, + CLK_X_DMIC1 = 1, + CLK_X_DMIC2 = 2, + CLK_X_ETR = 3, + CLK_X_CAM_MCLK = 4, + CLK_X_CAM_MCLK2 = 5, + CLK_X_I2C6 = 6, + CLK_X_MC_CAPA = 7, // MC DAISY CHAIN1 + CLK_X_MC_CBPA = 8, // MC DAISY CHAIN2 + CLK_X_MC_CPU = 9, + CLK_X_MC_BBC = 10, + CLK_X_VIM2_CLK = 11, + //CLK_X_ = 12, + CLK_X_MIPIBIF = 13, //RESERVED + CLK_X_EMC_DLL = 14, + //CLK_X_ = 15, + CLK_X_HDMI_AUDIO = 16, // HIDDEN. + CLK_X_UART_FST_MIPI_CAL = 17, + CLK_X_VIC = 18, + //CLK_X_ = 19, + CLK_X_ADX1 = 20, // HIDDEN. + CLK_X_DPAUX = 21, + CLK_X_SOR0 = 22, + CLK_X_SOR1 = 23, + CLK_X_GPU = 24, + CLK_X_DBGAPB = 25, + CLK_X_HPLL_ADSP = 26, + CLK_X_PLLP_ADSP = 27, + CLK_X_PLLA_ADSP = 28, + CLK_X_PLLG_REF = 29, + //CLK_X_ = 30, + //CLK_X_ = 31, +}; + +enum CLK_Y_DEV +{ + CLK_Y_SPARE1 = 0, + CLK_Y_SDMMC_LEGACY_TM = 1, + CLK_Y_NVDEC = 2, + CLK_Y_NVJPG = 3, + CLK_Y_AXIAP = 4, + CLK_Y_DMIC3 = 5, + CLK_Y_APE = 6, + CLK_Y_ADSP = 7, + CLK_Y_MC_CDPA = 8, // MC DAISY CHAIN4 + CLK_Y_MC_CCPA = 9, // MC DAISY CHAIN3 + CLK_Y_MAUD = 10, + //CLK_Y_ = 11, + CLK_Y_SATA_USB_UPHY = 12, // Only reset. + CLK_Y_PEX_USB_UPHY = 13, // Only reset. + CLK_Y_TSECB = 14, + CLK_Y_DPAUX1 = 15, + CLK_Y_VI_I2C = 16, + CLK_Y_HSIC_TRK = 17, + CLK_Y_USB2_TRK = 18, + CLK_Y_QSPI = 19, + CLK_Y_UARTAPE = 20, + CLK_Y_ADSPINTF = 21, // Only reset. + CLK_Y_ADSPPERIPH = 22, // Only reset. + CLK_Y_ADSPDBG = 23, // Only reset. + CLK_Y_ADSPWDT = 24, // Only reset. + CLK_Y_ADSPSCU = 25, // Only reset. + CLK_Y_ADSPNEON = 26, + CLK_Y_NVENC = 27, + CLK_Y_IQC2 = 28, + CLK_Y_IQC1 = 29, + CLK_Y_SOR_SAFE = 30, + CLK_Y_PLLP_OUT_CPU = 31, +}; + /*! Generic clock descriptor. */ typedef struct _clock_t { diff --git a/bdk/soc/hw_init.c b/bdk/soc/hw_init.c index ecb2371..2e0f78e 100644 --- a/bdk/soc/hw_init.c +++ b/bdk/soc/hw_init.c @@ -129,18 +129,19 @@ void _config_pmc_scratch() void _mbist_workaround() { - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock. + // Make sure Audio clocks are enabled before accessing I2S. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB); + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE); // Set mux output to SOR1 clock switch. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) | 0x8000) & 0xFFFFBFFF; // Enabled PLLD and set csi to PLLD for test pattern generation. CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000; - // Clear per-clock resets. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40; // Clear reset APE. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000; // Clear reset VIC. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; // Clear reset DISP1, HOST1X. + // Clear per-clock resets for APE/VIC/HOST1X/DISP1. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = BIT(CLK_Y_APE); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = BIT(CLK_X_VIC); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); usleep(2); // I2S channels to master and disable SLCG. @@ -159,20 +160,59 @@ void _mbist_workaround() VIC(0x8C) = 0xFFFFFFFF; usleep(2); - // Set per-clock reset. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = 0x40; // Set reset APE. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000; // Set reset DISP1, HOST1x. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = 0x40000; // Set reset VIC. + // Set per-clock reset for APE/VIC/HOST1X/DISP1. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = BIT(CLK_Y_APE); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = BIT(CLK_X_VIC); // Enable specific clocks and disable all others. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = 0xC0; // Enable clock PMC, FUSE. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80000130; // Enable clock RTC, TMR, GPIO, BPMP_CACHE. - //CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80400130; // Keep USBD ON. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) = 0x1F00200; // Enable clock CSITE, IRAMA, IRAMB, IRAMC, IRAMD, BPMP_CACHE_RAM. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = 0x80400808; // Enable clock MSELECT, APB2APE, SPDIF_DOUBLER, SE. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) = 0x402000FC; // Enable clock PCIERX0, PCIERX1, PCIERX2, PCIERX3, PCIERX4, PCIERX5, ENTROPY, MC1. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) = 0x23000780; // Enable clock MC_CAPA, MC_CAPB, MC_CPU, MC_BBC, DBGAPB, HPLL_ADSP, PLLG_REF. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) = 0x300; // Enable clock MC_CDPA, MC_CCPA. + // CLK L Devices. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = + BIT(CLK_H_PMC) | + BIT(CLK_H_FUSE); + // CLK H Devices. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = + BIT(CLK_L_RTC) | + BIT(CLK_L_TMR) | + BIT(CLK_L_GPIO) | + BIT(CLK_L_BPMP_CACHE_CTRL); + // CLK U Devices. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) = + BIT(CLK_U_CSITE) | + BIT(CLK_U_IRAMA) | + BIT(CLK_U_IRAMB) | + BIT(CLK_U_IRAMC) | + BIT(CLK_U_IRAMD) | + BIT(CLK_U_BPMP_CACHE_RAM); + // CLK V Devices. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = + BIT(CLK_V_MSELECT) | + BIT(CLK_V_APB2APE) | + BIT(CLK_V_SPDIF_DOUBLER) | + BIT(CLK_V_SE); + // CLK W Devices. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) = + BIT(CLK_W_PCIERX0) | + BIT(CLK_W_PCIERX1) | + BIT(CLK_W_PCIERX2) | + BIT(CLK_W_PCIERX3) | + BIT(CLK_W_PCIERX4) | + BIT(CLK_W_PCIERX5) | + BIT(CLK_W_ENTROPY) | + BIT(CLK_W_MC1); + // CLK X Devices. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) = + BIT(CLK_X_MC_CAPA) | + BIT(CLK_X_MC_CBPA) | + BIT(CLK_X_MC_CPU) | + BIT(CLK_X_MC_BBC) | + BIT(CLK_X_GPU) | + BIT(CLK_X_DBGAPB) | + BIT(CLK_X_PLLG_REF); + // CLK Y Devices. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) = + BIT(CLK_Y_MC_CDPA) | + BIT(CLK_Y_MC_CCPA); // Disable clock gate overrides. CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA) = 0; @@ -353,8 +393,8 @@ void reconfig_hw_workaround(bool extra_reconfig, u32 magic) nyx_str->mtc_cfg.init_done = 0; // Re-enable clocks to Audio Processing Engine as a workaround to hanging. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB); + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE); if (extra_reconfig) { @@ -376,7 +416,7 @@ void reconfig_hw_workaround(bool extra_reconfig, u32 magic) // Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits. if (magic == 0xBAADF00D) { - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) |= (1 << 22); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_USBD); sdmmc_init(&sd_sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, 0); clock_disable_cl_dvfs(); diff --git a/bdk/usb/usbd.c b/bdk/usb/usbd.c index 712629a..fa3c1f6 100644 --- a/bdk/usb/usbd.c +++ b/bdk/usb/usbd.c @@ -351,15 +351,15 @@ int usb_device_init() CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) | 0x2600000 | 0x800000; // Enable USBD clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = (1 << 22); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_USBD); usleep(2); - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = (1 << 22); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_USBD); usleep(2); - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = (1 << 22); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_USBD); usleep(2); // Clear XUSB_PADCTL reset - CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_CLR) = (1 << 14); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_CLR) = BIT(CLK_W_XUSB_PADCTL); // Enable USB PHY and reset for programming. u32 usb_susp_ctrl = USB(USB1_IF_USB_SUSP_CTRL); @@ -419,7 +419,7 @@ int usb_device_init() // Enable crystal clock. CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) |= 0x40000000; // Enable USB2 tracking. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= 0x40000; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK); CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) & 0xFFFFFF00) | 6; // Set trank divisor to 4. USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFFC03F07) | 0x78000 | 0x50; // Set delays. @@ -442,7 +442,7 @@ int usb_device_init() USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFF7FFFFF) | 1; // Disable USB2_TRK clock and configure UTMIP misc. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) &= 0xFFFBFFFF; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_CLR) = BIT(CLK_Y_USB2_TRK); CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) & 0xFEFFFFEA) | 0x2000000 | 0x28 | 2; usleep(1); @@ -535,10 +535,10 @@ static void _usb_device_power_down() CLOCK(CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0) |= 2; // Set XUSB_PADCTL reset - CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = (1 << 14); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = BIT(CLK_W_XUSB_PADCTL); // Disable USBD clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = (1 << 22); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_USBD); // Completely disable PLLU. CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~0x2E00000; // Disable PLLU USB/HSIC/ICUSB/48M. diff --git a/bdk/utils/types.h b/bdk/utils/types.h index 00af900..d305464 100644 --- a/bdk/utils/types.h +++ b/bdk/utils/types.h @@ -21,6 +21,7 @@ #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) #define ALIGN_DOWN(x, a) (((x) - ((a) - 1)) & ~((a) - 1)) +#define BIT(n) (1U << (n)) #define MAX(a, b) ((a) > (b) ? (a) : (b)) #define MIN(a, b) ((a) < (b) ? (a) : (b)) diff --git a/bootloader/hos/hos.c b/bootloader/hos/hos.c index 1b30edd..362fb04 100644 --- a/bootloader/hos/hos.c +++ b/bootloader/hos/hos.c @@ -1034,7 +1034,7 @@ int hos_launch(ini_sec_t *cfg) EMC(EMC_SCRATCH0) = 0; // Hold USBD in reset for SoC state validation on sleep. - CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) |= 0x400000; + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_USBD); // Flush cache and disable MMU. bpmp_mmu_disable();