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mtc: Update minerva to simplify some logic

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CTCaer 2020-12-26 17:28:49 +02:00
parent 11ca6caf5f
commit dfcdb2e1e6
1 changed files with 19 additions and 19 deletions
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30
modules/hekate_libsys_minerva/sys_sdrammtc.c
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@ -1229,17 +1229,19 @@ static void _change_dll_src(emc_table_t *mtc_table_entry, u32 clk_src_emc)
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = dll_setting; CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = dll_setting;
//OLD // Commit clock write.
u32 clk_enb_emc_dll = ((mtc_table_entry->clk_out_enb_x_0_clk_enb_emc_dll & 1) << 14) | (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) & 0xFFFFBFFF); (void)CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X);
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) = clk_enb_emc_dll; _usleep(2);
//NEW // Enable/Disable EMC DLL.
// _usleep(2); if (mtc_table_entry->clk_out_enb_x_0_clk_enb_emc_dll)
// if (mtc_table_entry->clk_out_enb_x_0_clk_enb_emc_dll) CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (1 << 14);
// CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) |= 0x4000; else
// else CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_CLR) = (1 << 14);
// CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_CLR) |= 0x4000;
// _usleep(2); // Commit clock write.
(void)CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X);
_usleep(2);
} }
static u32 _digital_dll_prelock(emc_table_t *mtc_table_entry, u32 needs_tristate_training, u32 selected_clk_src_emc) static u32 _digital_dll_prelock(emc_table_t *mtc_table_entry, u32 needs_tristate_training, u32 selected_clk_src_emc)
@ -3057,15 +3059,14 @@ s32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_entry, u
// Writing burst_mc_regs. // Writing burst_mc_regs.
for (u32 i = 0; dst_emc_entry->num_mc_regs > i; i++) for (u32 i = 0; dst_emc_entry->num_mc_regs > i; i++)
MC(burst_mc_regs_addr_table[i]) = dst_emc_entry->burst_mc_regs[i]; MC(burst_mc_regs_addr_table[i]) = dst_emc_entry->burst_mc_regs[i];
}
// Writing la_scale_regs. // Writing la_scale_regs.
//if ((dst_emc_entry->rate_khz < src_emc_entry->rate_khz) && dst_emc_entry->num_up_down) //NEW TODO if (dst_emc_entry->rate_khz < src_emc_entry->rate_khz)
if ((dst_emc_entry->rate_khz < src_emc_entry->rate_khz) > needs_tristate_training)
{ {
for (u32 i = 0; dst_emc_entry->num_up_down > i; i++) for (u32 i = 0; dst_emc_entry->num_up_down > i; i++)
MC(la_scale_regs_mc_addr_table[i]) = dst_emc_entry->la_scale_regs[i]; MC(la_scale_regs_mc_addr_table[i]) = dst_emc_entry->la_scale_regs[i];
} }
}
// Step 9 - LPDDR4. // Step 9 - LPDDR4.
EPRINTF("Step 9"); EPRINTF("Step 9");
@ -3470,8 +3471,7 @@ step_19_2:
// Step 25 - Program MC updown regs. // Step 25 - Program MC updown regs.
EPRINTF("Step 25"); EPRINTF("Step 25");
//if (dst_emc_entry->rate_khz > src_emc_entry->rate_khz) //NEW TODO if ((dst_emc_entry->rate_khz > src_emc_entry->rate_khz) && !needs_tristate_training)
if ((dst_emc_entry->rate_khz > src_emc_entry->rate_khz) > needs_tristate_training)
{ {
for (u32 i = 0; dst_emc_entry->num_up_down > i; i++) for (u32 i = 0; dst_emc_entry->num_up_down > i; i++)
MC(la_scale_regs_mc_addr_table[i]) = dst_emc_entry->la_scale_regs[i]; MC(la_scale_regs_mc_addr_table[i]) = dst_emc_entry->la_scale_regs[i];