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mtc: Name sdram ids

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CTCaer 2020-06-14 17:39:39 +03:00
parent 029d66bd95
commit d37fe213d7
2 changed files with 13 additions and 5 deletions
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8
modules/hekate_libsys_minerva/mtc_switch_tables.h
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@ -20,6 +20,14 @@
#ifndef _MTC_SWITCH_TABLES_H_ #ifndef _MTC_SWITCH_TABLES_H_
#define _MTC_SWITCH_TABLES_H_ #define _MTC_SWITCH_TABLES_H_
#define DRAM_4GB_SAMSUNG_K4F6E304HB_MGCH 0
#define DRAM_4GB_HYNIX_H9HCNNNBPUMLHR_NLN 1
#define DRAM_4GB_MICRON_MT53B512M32D2NP_062_WT 2
#define DRAM_4GB_COPPER_SAMSUNG 3
#define DRAM_6GB_SAMSUNG_K4FHE3D4HM_MFCH 4
#define DRAM_4GB_COPPER_HYNIX 5
#define DRAM_4GB_COPPER_MICRON 6
// nx_abca2_0_3 and nx_abca2_1. For sdram ids 0,2,3,4 // nx_abca2_0_3 and nx_abca2_1. For sdram ids 0,2,3,4
static const unsigned char nx_abca2_0_3_10NoCfgVersion_V9_8_7_V1_6[49280] = static const unsigned char nx_abca2_0_3_10NoCfgVersion_V9_8_7_V1_6[49280] =
{ {

10
modules/hekate_libsys_minerva/sys_sdrammtc.c
View file

@ -3856,13 +3856,13 @@ static void _minerva_get_table(mtc_config_t *mtc_cfg)
{ {
switch (mtc_cfg->sdram_id) switch (mtc_cfg->sdram_id)
{ {
case 1: case DRAM_4GB_HYNIX_H9HCNNNBPUMLHR_NLN:
memcpy(mtc_cfg->mtc_table, nx_abca2_2_10NoCfgVersion_V9_8_7_V1_6, EMC_TABLE_SIZE_R7); memcpy(mtc_cfg->mtc_table, nx_abca2_2_10NoCfgVersion_V9_8_7_V1_6, EMC_TABLE_SIZE_R7);
break; break;
case 0: case DRAM_4GB_SAMSUNG_K4F6E304HB_MGCH:
case 2: case DRAM_4GB_MICRON_MT53B512M32D2NP_062_WT:
case 3: case DRAM_4GB_COPPER_SAMSUNG:
case 4: case DRAM_6GB_SAMSUNG_K4FHE3D4HM_MFCH:
default: default:
memcpy(mtc_cfg->mtc_table, nx_abca2_0_3_10NoCfgVersion_V9_8_7_V1_6, EMC_TABLE_SIZE_R7); memcpy(mtc_cfg->mtc_table, nx_abca2_0_3_10NoCfgVersion_V9_8_7_V1_6, EMC_TABLE_SIZE_R7);
break; break;