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minerva: name needs_training flags
This commit is contained in:
CTCaer
parent
6092994240
commit
d1c0d464dc
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@ -51,6 +51,27 @@
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#define EMC_PERIODIC_TRAIN_MS 100
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#define EMC_TEMP_COMP_MS 1000
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/* Training types */
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#define NEEDS_TRAINING_CA BIT(0)
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#define NEEDS_TRAINING_CA_VREF BIT(1)
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#define NEEDS_TRAINING_QUSE BIT(2)
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#define NEEDS_TRAINING_QUSE_VREF BIT(3)
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#define NEEDS_TRAINING_WR BIT(4)
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#define NEEDS_TRAINING_WR_VREF BIT(5)
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#define NEEDS_TRAINING_RD BIT(6)
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#define NEEDS_TRAINING_RD_VREF BIT(7)
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#define NEEDS_TRAINING_SWAP_RANK BIT(8)
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#define NEEDS_TRAINING_IN_SELF_REFRESH BIT(9)
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#define NEEDS_TRISTATE_TRAINING (NEEDS_TRAINING_CA | NEEDS_TRAINING_CA_VREF | \
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NEEDS_TRAINING_QUSE | NEEDS_TRAINING_WR | \
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NEEDS_TRAINING_WR_VREF | NEEDS_TRAINING_RD | \
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NEEDS_TRAINING_RD_VREF)
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#define NEEDS_TRAINING_CA_COMBO (NEEDS_TRAINING_CA | NEEDS_TRAINING_CA_VREF)
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#define NEEDS_TRAINING_QUSE_COMBO (NEEDS_TRAINING_QUSE | NEEDS_TRAINING_QUSE_VREF)
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#define NEEDS_TRAINING_WR_COMBO (NEEDS_TRAINING_WR | NEEDS_TRAINING_WR_VREF)
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#define NEEDS_TRAINING_RD_COMBO (NEEDS_TRAINING_RD | NEEDS_TRAINING_RD_VREF)
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typedef struct
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{
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u32 rate_to;
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@ -1411,7 +1411,7 @@ static u32 _dvfs_power_ramp_down(bool flip_backward, emc_table_t *src_emc_table_
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return ramp_down_wait;
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}
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static u32 _dvfs_power_ramp_up(bool flip_backward, emc_table_t *src_emc_table_entry, emc_table_t *dst_emc_table_entry, u8 needs_training, u32 dst_clock_period)
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static u32 _dvfs_power_ramp_up(bool flip_backward, emc_table_t *src_emc_table_entry, emc_table_t *dst_emc_table_entry, u32 needs_training, u32 dst_clock_period)
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{
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u32 pmacro_cmd_pad;
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u32 pmacro_dq_pad;
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@ -1431,7 +1431,7 @@ static u32 _dvfs_power_ramp_up(bool flip_backward, emc_table_t *src_emc_table_en
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pmacro_cfg5 = src_emc_table_entry->burst_regs.emc_fbio_cfg5_idx;
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pmacro_common_tx = src_emc_table_entry->burst_regs.emc_pmacro_common_pad_tx_ctrl_idx;
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}
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else if (needs_training & 3)
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else if (needs_training & NEEDS_TRAINING_CA_COMBO)
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{
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pmacro_cmd_pad = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_cmd_pad_tx_ctrl_idx;
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pmacro_dq_pad = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_data_pad_tx_ctrl_idx;
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@ -1439,7 +1439,7 @@ static u32 _dvfs_power_ramp_up(bool flip_backward, emc_table_t *src_emc_table_en
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pmacro_cfg5 = dst_emc_table_entry->shadow_regs_ca_train.emc_fbio_cfg5_idx;
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pmacro_common_tx = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_common_pad_tx_ctrl_idx;
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}
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else if (needs_training & 0xC)
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else if (needs_training & NEEDS_TRAINING_QUSE_COMBO)
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{
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pmacro_cmd_pad = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_cmd_pad_tx_ctrl_idx;
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pmacro_dq_pad = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_data_pad_tx_ctrl_idx;
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@ -1447,7 +1447,7 @@ static u32 _dvfs_power_ramp_up(bool flip_backward, emc_table_t *src_emc_table_en
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pmacro_cfg5 = dst_emc_table_entry->shadow_regs_quse_train.emc_fbio_cfg5_idx;
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pmacro_common_tx = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_common_pad_tx_ctrl_idx;
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}
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else if (needs_training & 0xF0)
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else if (needs_training & (NEEDS_TRAINING_WR_COMBO | NEEDS_TRAINING_RD_COMBO))
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{
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pmacro_cmd_pad = dst_emc_table_entry->shadow_regs_rdwr_train.emc_pmacro_cmd_pad_tx_ctrl_idx;
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pmacro_dq_pad = dst_emc_table_entry->shadow_regs_rdwr_train.emc_pmacro_data_pad_tx_ctrl_idx;
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@ -2190,15 +2190,15 @@ static bool _check_freq_changed(u32 dst_entry_rate_KHz, u32 dst_entry_clk_src_em
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static void _save_train_results(emc_table_t *mtc_table_entry, u32 needs_training, u32 dram_dev_num, bool channel1_enabled)
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{
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bool needs_ca_training = needs_training & 1;
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bool needs_ca_vref_training = (needs_training >> 1) & 1;
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bool needs_quse_training = (needs_training >> 2) & 1;
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bool needs_quse_vref_training = (needs_training >> 3) & 1;
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bool needs_wr_training = (needs_training >> 4) & 1;
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bool needs_wr_vref_training = (needs_training >> 5) & 1;
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bool needs_rd_training = (needs_training >> 6) & 1;
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bool needs_rd_vref_training = (needs_training >> 7) & 1;
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bool needs_training_in_self_refresh = (needs_training >> 9) & 1;
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bool needs_ca_training = !!(needs_training & NEEDS_TRAINING_CA);
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bool needs_ca_vref_training = !!(needs_training & NEEDS_TRAINING_CA_VREF);
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bool needs_quse_training = !!(needs_training & NEEDS_TRAINING_QUSE);
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bool needs_quse_vref_training = !!(needs_training & NEEDS_TRAINING_QUSE_VREF);
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bool needs_wr_training = !!(needs_training & NEEDS_TRAINING_WR);
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bool needs_wr_vref_training = !!(needs_training & NEEDS_TRAINING_WR_VREF);
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bool needs_rd_training = !!(needs_training & NEEDS_TRAINING_RD);
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bool needs_rd_vref_training = !!(needs_training & NEEDS_TRAINING_RD_VREF);
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bool needs_training_in_self_refresh = !!(needs_training & NEEDS_TRAINING_IN_SELF_REFRESH);
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if (needs_ca_training)
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{
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@ -2565,32 +2565,35 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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u32 mr13_flip_fspwr = 0;
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u32 mr13_catr_enable;
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/* needs_training LOBYTE table var */
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/* needs_training flags */
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/*
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| bit | Description |
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|-----|----------------------------|
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| 0 | Needs CA training |
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| 1 | Needs CA_VREF training |
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| 2 | Needs QUSE training |
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| 3 | Needs QUSE_VREF training |
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| 4 | Needs WR training |
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| 5 | Needs WR_VREF training |
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| 6 | Needs RD training |
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| 7 | Needs RD_VREF training |
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| bit | Description |
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|-----|----------------------------------|
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| 0 | Needs CA training |
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| 1 | Needs CA_VREF training |
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| 2 | Needs QUSE training |
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| 3 | Needs QUSE_VREF training |
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| 4 | Needs WR training |
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| 5 | Needs WR_VREF training |
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| 6 | Needs RD training |
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| 7 | Needs RD_VREF training |
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| 8 | Needs SWAP_RANK training |
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| 9 | Needs IN_SELF_REFRESH training |
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*/
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bool compensate_trimmer_applicable = false;
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bool needs_ca_or_cavref_training = (needs_training & 3) != 0;
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bool needs_tristate_training = (needs_training & 0xF7) != 0;
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bool needs_ca_training = needs_training & 1;
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bool needs_ca_vref_training = (needs_training >> 1) & 1;
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bool needs_quse_training = (needs_training >> 2) & 1;
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bool needs_quse_vref_training = (needs_training >> 3) & 1;
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bool needs_wr_training = (needs_training >> 4) & 1;
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bool needs_wr_vref_training = (needs_training >> 5) & 1;
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bool needs_rd_training = (needs_training >> 6) & 1;
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bool needs_rd_vref_training = (needs_training >> 7) & 1;
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bool needs_swap_rank_training = (needs_training >> 8) & 1;
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bool needs_ca_combo_training = !!(needs_training & NEEDS_TRAINING_CA_COMBO);
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bool needs_tristate_training = !!(needs_training & NEEDS_TRISTATE_TRAINING);
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bool needs_ca_training = !!(needs_training & NEEDS_TRAINING_CA);
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bool needs_ca_vref_training = !!(needs_training & NEEDS_TRAINING_CA_VREF);
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bool needs_quse_training = !!(needs_training & NEEDS_TRAINING_QUSE);
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bool needs_quse_vref_training = !!(needs_training & NEEDS_TRAINING_QUSE_VREF);
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bool needs_wr_training = !!(needs_training & NEEDS_TRAINING_WR);
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bool needs_wr_vref_training = !!(needs_training & NEEDS_TRAINING_WR_VREF);
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bool needs_rd_training = !!(needs_training & NEEDS_TRAINING_RD);
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bool needs_rd_vref_training = !!(needs_training & NEEDS_TRAINING_RD_VREF);
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bool needs_swap_rank_training = !!(needs_training & NEEDS_TRAINING_SWAP_RANK);
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bool zcal_resistor_shared = (src_emc_entry->burst_regs.emc_zcal_wait_cnt_idx >> 31) & 1;
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bool enable_bg_regulator = (dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx & 1) ^ 1;
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@ -2748,7 +2751,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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// Step 7 - Bug 200024907 - Patch RP R2P.
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EPRINTF("Step 7");
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if (needs_ca_or_cavref_training && dram_dev_num == TWO_RANK)
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if (needs_ca_combo_training && dram_dev_num == TWO_RANK)
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EMC(EMC_PIN) = 0x107;
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u32 R2P_war = 0;
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@ -2849,7 +2852,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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else
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mr13_catr_enable = (mr13_flip_fspwr & 0x3FFFFFFF) | 0x80000001;
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if (needs_ca_or_cavref_training)
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if (needs_ca_combo_training)
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{
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if (needs_swap_rank_training)
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mr13_flip_fspop = (mr13_flip_fspop & 0x3FFFFFFF) | 0x80000000;
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@ -2878,11 +2881,11 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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reg_addr = burst_regs_emc_addr_table[i];
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if (needs_tristate_training)
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{
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if (needs_ca_or_cavref_training)
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if (needs_ca_combo_training)
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reg_val = dst_burst_regs->shadow_regs_ca_train[i];
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else if (needs_training & 0xC)
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else if (needs_training & NEEDS_TRAINING_QUSE_COMBO)
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reg_val = dst_burst_regs->shadow_regs_quse_train[i];
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else if (needs_training & 0xF0)
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else if (needs_training & (NEEDS_TRAINING_WR_COMBO | NEEDS_TRAINING_RD_COMBO))
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reg_val = dst_burst_regs->shadow_regs_rdwr_train[i];
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else
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continue;
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@ -3069,7 +3072,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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EMC(EMC_DBG) = emc_dbg_o | 2;
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EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = dst_emc_entry->burst_regs.emc_pmacro_autocal_cfg_common_idx | 0x10000;
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if (needs_ca_or_cavref_training)
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if (needs_ca_combo_training)
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EMC(EMC_FBIO_CFG5) = src_emc_entry->burst_regs.emc_fbio_cfg5_idx | 0x8000000;
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EMC(EMC_DBG) = emc_dbg_o;
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@ -3084,7 +3087,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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EPRINTF("Step 10");
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_ccfifo_write(EMC_SELF_REF, 0x101, 0);
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if (!needs_ca_or_cavref_training && (dst_clock_period <= 2000))
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if (!needs_ca_combo_training && (dst_clock_period <= 2000))
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{
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_ccfifo_write(EMC_MRW3, mr13_flip_fspwr ^ 0x40, 0);
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_ccfifo_write(EMC_MRW6, (src_emc_entry->burst_regs.emc_mrw6_idx & 0xC0C0) | (dst_emc_entry->burst_regs.emc_mrw6_idx & 0xFFFF3F3F), 0);
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@ -3114,7 +3117,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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_ccfifo_write(EMC_DBG, emc_dbg_val, 0);
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}
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if (needs_ca_or_cavref_training)
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if (needs_ca_combo_training)
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{
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_ccfifo_write(EMC_PMACRO_DATA_RX_TERM_MODE, src_emc_entry->burst_regs.emc_pmacro_data_rx_term_mode_idx & 0xFFFFFCCC, 0);
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@ -3160,7 +3163,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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// Step 14 - Bringup CKE pins.
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EPRINTF("Step 14");
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u32 emc_pin_val_final = 0;
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if (needs_ca_or_cavref_training)
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if (needs_ca_combo_training)
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{
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emc_pin_val_final = emc_pin_o & 0xFFFFFFF8;
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if (dram_dev_num == TWO_RANK)
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@ -3180,7 +3183,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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// Step 15 - Zqlatch.
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EPRINTF("Step 15");
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if (!needs_ca_or_cavref_training)
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if (!needs_ca_combo_training)
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{
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s32 zq_latch_dvfs_wait_time;
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u32 T_PDEX_timing = div_o3(dst_emc_entry->dram_timings.t_pdex * 1000, dst_clock_period);
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@ -3291,7 +3294,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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_ccfifo_write(EMC_SWITCH_BACK_CTRL, 1, 0);
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if (!needs_ca_or_cavref_training || needs_swap_rank_training)
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if (!needs_ca_combo_training || needs_swap_rank_training)
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{
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_ccfifo_write(EMC_MRW3, mr13_flip_fspop ^ 0xC0, 0);
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_ccfifo_write(EMC_INTSTATUS, 0, 1000000 / dst_clock_period);
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@ -3315,7 +3318,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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else
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_ccfifo_write(EMC_PIN, (emc_pin_o & 0xFFFFFFF8) | 1, 0);
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if (needs_ca_or_cavref_training)
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if (needs_ca_combo_training)
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{
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_ccfifo_write(EMC_TR_CTRL_0, 0x4A, 200000 / src_clock_period);
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_ccfifo_write(EMC_TR_CTRL_0, 0x40, 1000000 / src_clock_period);
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@ -3329,14 +3332,14 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e
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_ccfifo_write(EMC_ZQ_CAL, 0x80000001, 0);
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_ccfifo_write(EMC_ZQ_CAL, 0x80000002, 1000000 / src_clock_period);
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if ((!needs_ca_or_cavref_training || needs_swap_rank_training) && dram_dev_num == TWO_RANK)
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if ((!needs_ca_combo_training || needs_swap_rank_training) && dram_dev_num == TWO_RANK)
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{
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_ccfifo_write(EMC_ZQ_CAL, 0x40000001, 0);
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_ccfifo_write(EMC_ZQ_CAL, 0x40000002, 1000000 / src_clock_period);
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}
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if (!needs_ca_or_cavref_training)
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if (!needs_ca_combo_training)
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_ccfifo_write(EMC_MRW3, (mr13_flip_fspop & 0xF3FFFFF7) ^ 0xC0000C0, 0);
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_ccfifo_write(EMC_SELF_REF, 0, 0); // Was 0x100.
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@ -3536,24 +3539,29 @@ static void _minerva_train_patterns(emc_table_t *src_emc_entry, emc_table_t *dst
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if (!dst_emc_entry->trained)
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{
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if (needs_training & 3)
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if (needs_training & NEEDS_TRAINING_CA_COMBO)
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{
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needs_training_emc_table[needs_training_idx++] = needs_training & 0x203;
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needs_training_emc_table[needs_training_idx++] =
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needs_training & (NEEDS_TRAINING_CA_COMBO | NEEDS_TRAINING_IN_SELF_REFRESH);
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if (MC(MC_EMEM_ADR_CFG) & 1) // if mapping W8 (1KB page).
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needs_training_emc_table[needs_training_idx++] = needs_training & 0x303;
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needs_training_emc_table[needs_training_idx++] =
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needs_training & (NEEDS_TRAINING_CA_COMBO | NEEDS_TRAINING_SWAP_RANK | NEEDS_TRAINING_IN_SELF_REFRESH);
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}
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if (needs_training & 0xC)
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if (needs_training & NEEDS_TRAINING_QUSE_COMBO)
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{
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needs_training_emc_table[needs_training_idx++] = needs_training & 0x20C;
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needs_training_emc_table[needs_training_idx++] =
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needs_training & (NEEDS_TRAINING_QUSE_COMBO | NEEDS_TRAINING_IN_SELF_REFRESH);
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if (MC(MC_EMEM_ADR_CFG) & 1)
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needs_training_emc_table[needs_training_idx++] = needs_training & 0x204;
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needs_training_emc_table[needs_training_idx++] =
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needs_training & (NEEDS_TRAINING_QUSE | NEEDS_TRAINING_IN_SELF_REFRESH);
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}
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if (needs_training & 0xF0)
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needs_training_emc_table[needs_training_idx++] = needs_training & 0x2F0;
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if (needs_training & (NEEDS_TRAINING_WR_COMBO | NEEDS_TRAINING_RD_COMBO))
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needs_training_emc_table[needs_training_idx++] =
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needs_training & (NEEDS_TRAINING_WR_COMBO | NEEDS_TRAINING_RD_COMBO | NEEDS_TRAINING_IN_SELF_REFRESH);
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for (u32 i = 0; needs_training_idx > i; i++) // Runs more than once for needs_training & 0xF
|
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for (u32 i = 0; needs_training_idx > i; i++) // Runs more than once for needs_training CA/QUSE/WR/RD.
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{
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_minerva_set_clock(src_emc_entry, dst_emc_entry, needs_training_emc_table[i], selected_clk_src_emc);
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|
||||
|
|
|
|||
Loading…
Reference in a new issue