diff --git a/bdk/display/di.c b/bdk/display/di.c
index 5aba103..fd767e9 100644
--- a/bdk/display/di.c
+++ b/bdk/display/di.c
@@ -379,8 +379,8 @@ void display_init()
 	// Enable Display Interface specific clocks.
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
 	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_HOST1X)   | BIT(CLK_L_DISP1);
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_HOST1X)   | BIT(CLK_L_DISP1);
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_DISP1);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_DISP1);
 
 	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_UART_FST_MIPI_CAL);
 	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = 10; // Set PLLP_OUT3 and div 6 (17MHz).
@@ -798,8 +798,8 @@ skip_panel_deinit:
 	// Disable Display Interface specific clocks.
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
 	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_HOST1X)   | BIT(CLK_L_DISP1);
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_HOST1X)   | BIT(CLK_L_DISP1);
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_DISP1);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_DISP1);
 
 	// Power down pads.
 	DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) |
diff --git a/bdk/display/vic.c b/bdk/display/vic.c
index 5bfc990..26c119d 100644
--- a/bdk/display/vic.c
+++ b/bdk/display/vic.c
@@ -539,7 +539,6 @@ int vic_init()
 	// Ease the stress to APB.
 	bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
 
-	clock_enable_host1x();
 	clock_enable_vic();
 
 	// Restore sys clock.
diff --git a/bdk/sec/tsec.c b/bdk/sec/tsec.c
index 201df3d..306f9dc 100644
--- a/bdk/sec/tsec.c
+++ b/bdk/sec/tsec.c
@@ -77,8 +77,6 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 	bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
 
 	// Enable clocks.
-	clock_enable_host1x();
-	usleep(2);
 	clock_enable_tsec();
 	clock_enable_sor_safe();
 	clock_enable_sor0();
diff --git a/bdk/soc/hw_init.c b/bdk/soc/hw_init.c
index 7010922..26a9f27 100644
--- a/bdk/soc/hw_init.c
+++ b/bdk/soc/hw_init.c
@@ -415,6 +415,9 @@ void hw_init()
 	sdram_init();
 
 	bpmp_mmu_enable();
+
+	// Enable HOST1X used by every display module (DC, VIC, NVDEC, NVENC, TSEC, etc).
+	clock_enable_host1x();
 }
 
 void hw_reinit_workaround(bool coreboot, u32 bl_magic)
@@ -470,6 +473,7 @@ void hw_reinit_workaround(bool coreboot, u32 bl_magic)
 		break;
 	default:
 		display_end();
+		clock_disable_host1x();
 	}
 
 	// Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits.