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https://github.com/CTCaer/hekate
synced 2024-12-22 19:31:12 +00:00
clock: Move PLLC config from bpmp.c to clock.c
This commit is contained in:
parent
009db77426
commit
c99a87dd09
6 changed files with 104 additions and 64 deletions
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@ -253,30 +253,8 @@ void bpmp_clk_rate_set(bpmp_freq_t fid)
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msleep(1); // Wait a bit for clock source change.
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msleep(1); // Wait a bit for clock source change.
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}
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}
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// Take PLLC out of reset and set basic misc parameters.
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// Configure and enable PLLC.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) =
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clock_enable_pllc(pll_divn[fid]);
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((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x80000 << 4); // PLLC_EXT_FRU.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM.
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// Disable PLL and IDDQ in case they are on.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) &= ~PLLC_MISC1_IDDQ;
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usleep(10);
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// Set PLLC4 dividers.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) = 4 | (pll_divn[fid] << 10); // DIVM: 4, DIVP: 1.
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// Enable PLLC4 and wait for Phase and Frequency lock.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_ENABLE;
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_LOCK))
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;
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// Disable PLLC_OUT1, enable reset and set div to 1.5.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = (1 << 8);
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// Enable PLLC_OUT1 and bring it out of reset.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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msleep(1); // Wait a bit for clock source change.
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// Set SCLK / HCLK / PCLK.
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// Set SCLK / HCLK / PCLK.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK.
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@ -288,13 +266,8 @@ void bpmp_clk_rate_set(bpmp_freq_t fid)
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msleep(1); // Wait a bit for clock source change.
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msleep(1); // Wait a bit for clock source change.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK.
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// Disable PLLC and PLLC_OUT1.
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// Disable PLLC to save power.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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clock_disable_pllc();
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) |= PLLC_MISC1_IDDQ;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET;
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usleep(10);
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}
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}
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bpmp_clock_set = fid;
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bpmp_clock_set = fid;
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}
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}
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@ -228,6 +228,51 @@ void clock_disable_pwm()
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clock_disable(&_clock_pwm);
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clock_disable(&_clock_pwm);
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}
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}
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void clock_enable_pllc(u32 divn)
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{
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u8 pll_divn_curr = (CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) >> 10) & 0xFF;
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// Check if already enabled and configured.
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if ((CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_ENABLE) && (pll_divn_curr == divn))
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return;
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// Take PLLC out of reset and set basic misc parameters.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) =
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((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x80000 << 4); // PLLC_EXT_FRU.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM.
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// Disable PLL and IDDQ in case they are on.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) &= ~PLLC_MISC1_IDDQ;
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usleep(10);
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// Set PLLC4 dividers.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) = 4 | (divn << 10); // DIVM: 4, DIVP: 1.
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// Enable PLLC4 and wait for Phase and Frequency lock.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_ENABLE;
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_LOCK))
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;
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// Disable PLLC_OUT1, enable reset and set div to 1.5.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = (1 << 8);
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// Enable PLLC_OUT1 and bring it out of reset.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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msleep(1); // Wait a bit for clock source change.
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}
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void clock_disable_pllc()
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{
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// Disable PLLC and PLLC_OUT1.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) |= PLLC_MISC1_IDDQ;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET;
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usleep(10);
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}
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#define L_SWR_SDMMC1_RST (1 << 14)
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#define L_SWR_SDMMC1_RST (1 << 14)
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#define L_SWR_SDMMC2_RST (1 << 9)
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#define L_SWR_SDMMC2_RST (1 << 9)
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#define L_SWR_SDMMC4_RST (1 << 15)
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#define L_SWR_SDMMC4_RST (1 << 15)
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@ -190,6 +190,8 @@ void clock_enable_coresight();
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void clock_disable_coresight();
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void clock_disable_coresight();
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void clock_enable_pwm();
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void clock_enable_pwm();
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void clock_disable_pwm();
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void clock_disable_pwm();
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void clock_enable_pllc(u32 divn);
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void clock_disable_pllc();
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void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
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void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
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void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type);
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void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type);
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int clock_sdmmc_is_not_reset_and_enabled(u32 id);
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int clock_sdmmc_is_not_reset_and_enabled(u32 id);
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@ -253,30 +253,8 @@ void bpmp_clk_rate_set(bpmp_freq_t fid)
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msleep(1); // Wait a bit for clock source change.
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msleep(1); // Wait a bit for clock source change.
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}
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}
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// Take PLLC out of reset and set basic misc parameters.
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// Configure and enable PLLC.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) =
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clock_enable_pllc(pll_divn[fid]);
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((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x80000 << 4); // PLLC_EXT_FRU.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM.
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// Disable PLL and IDDQ in case they are on.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) &= ~PLLC_MISC1_IDDQ;
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usleep(10);
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// Set PLLC4 dividers.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) = 4 | (pll_divn[fid] << 10); // DIVM: 4, DIVP: 1.
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// Enable PLLC4 and wait for Phase and Frequency lock.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_ENABLE;
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_LOCK))
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;
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// Disable PLLC_OUT1, enable reset and set div to 1.5.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = (1 << 8);
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// Enable PLLC_OUT1 and bring it out of reset.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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msleep(1); // Wait a bit for clock source change.
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// Set SCLK / HCLK / PCLK.
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// Set SCLK / HCLK / PCLK.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK.
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@ -288,13 +266,8 @@ void bpmp_clk_rate_set(bpmp_freq_t fid)
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msleep(1); // Wait a bit for clock source change.
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msleep(1); // Wait a bit for clock source change.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK.
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// Disable PLLC and PLLC_OUT1.
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// Disable PLLC to save power.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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clock_disable_pllc();
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) |= PLLC_MISC1_IDDQ;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET;
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usleep(10);
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}
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}
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bpmp_clock_set = fid;
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bpmp_clock_set = fid;
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}
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}
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@ -228,6 +228,51 @@ void clock_disable_pwm()
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clock_disable(&_clock_pwm);
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clock_disable(&_clock_pwm);
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}
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}
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void clock_enable_pllc(u32 divn)
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{
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u8 pll_divn_curr = (CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) >> 10) & 0xFF;
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// Check if already enabled and configured.
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if ((CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_ENABLE) && (pll_divn_curr == divn))
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return;
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// Take PLLC out of reset and set basic misc parameters.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) =
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((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x80000 << 4); // PLLC_EXT_FRU.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM.
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// Disable PLL and IDDQ in case they are on.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) &= ~PLLC_MISC1_IDDQ;
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usleep(10);
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// Set PLLC4 dividers.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) = 4 | (divn << 10); // DIVM: 4, DIVP: 1.
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// Enable PLLC4 and wait for Phase and Frequency lock.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_ENABLE;
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_LOCK))
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;
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// Disable PLLC_OUT1, enable reset and set div to 1.5.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = (1 << 8);
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// Enable PLLC_OUT1 and bring it out of reset.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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msleep(1); // Wait a bit for clock source change.
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}
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void clock_disable_pllc()
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{
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// Disable PLLC and PLLC_OUT1.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) |= PLLC_MISC1_IDDQ;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET;
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usleep(10);
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}
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#define L_SWR_SDMMC1_RST (1 << 14)
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#define L_SWR_SDMMC1_RST (1 << 14)
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#define L_SWR_SDMMC2_RST (1 << 9)
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#define L_SWR_SDMMC2_RST (1 << 9)
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#define L_SWR_SDMMC4_RST (1 << 15)
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#define L_SWR_SDMMC4_RST (1 << 15)
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@ -190,6 +190,8 @@ void clock_enable_coresight();
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void clock_disable_coresight();
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void clock_disable_coresight();
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void clock_enable_pwm();
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void clock_enable_pwm();
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void clock_disable_pwm();
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void clock_disable_pwm();
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void clock_enable_pllc(u32 divn);
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void clock_disable_pllc();
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void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
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void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
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void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type);
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void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type);
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int clock_sdmmc_is_not_reset_and_enabled(u32 id);
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int clock_sdmmc_is_not_reset_and_enabled(u32 id);
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