diff --git a/bdk/mem/heap.h b/bdk/mem/heap.h
index 6b0c17a..9150104 100644
--- a/bdk/mem/heap.h
+++ b/bdk/mem/heap.h
@@ -33,15 +33,15 @@ typedef struct _heap
 {
 	void *start;
 	hnode_t *first;
-    hnode_t *last;
+	hnode_t *last;
 } heap_t;
 
 typedef struct
 {
-    u32 total;
-    u32 used;
-    u32 nodes_total;
-    u32 nodes_used;
+	u32 total;
+	u32 used;
+	u32 nodes_total;
+	u32 nodes_used;
 } heap_monitor_t;
 
 void heap_init(void *base);
diff --git a/bdk/mem/mc_t210.h b/bdk/mem/mc_t210.h
index a4590b3..ed96852 100644
--- a/bdk/mem/mc_t210.h
+++ b/bdk/mem/mc_t210.h
@@ -579,14 +579,14 @@
 #define SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY (1 << ADDRESS_TYPE_SHIFT)
 
 #define READ_ACCESS_LEVEL_SHIFT 3
-#define SEC_CARVEOUT_CFG_RD_ALL       (1 << READ_ACCESS_LEVEL_SHIFT)
-#define SEC_CARVEOUT_CFG_RD_UNK       (2 << READ_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_RD_NS        (1 << READ_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_RD_SEC       (2 << READ_ACCESS_LEVEL_SHIFT)
 #define SEC_CARVEOUT_CFG_RD_FALCON_LS (4 << READ_ACCESS_LEVEL_SHIFT)
 #define SEC_CARVEOUT_CFG_RD_FALCON_HS (8 << READ_ACCESS_LEVEL_SHIFT)
 
 #define WRITE_ACCESS_LEVEL_SHIFT 7
-#define SEC_CARVEOUT_CFG_WR_ALL       (1 << WRITE_ACCESS_LEVEL_SHIFT)
-#define SEC_CARVEOUT_CFG_WR_UNK       (2 << WRITE_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_WR_NS        (1 << WRITE_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_WR_SEC       (2 << WRITE_ACCESS_LEVEL_SHIFT)
 #define SEC_CARVEOUT_CFG_WR_FALCON_LS (4 << WRITE_ACCESS_LEVEL_SHIFT)
 #define SEC_CARVEOUT_CFG_WR_FALCON_HS (8 << WRITE_ACCESS_LEVEL_SHIFT)
 
@@ -594,16 +594,16 @@
 #define SEC_CARVEOUT_CFG_APERTURE_ID(id) ((id) << 11)
 
 #define DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT 14
-#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_L0 (1 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT)
-#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_L1 (2 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT)
-#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_L2 (4 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT)
-#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_L3 (8 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_NS (1 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_SEC (2 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_FLCN_LS (4 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_FLCN_HS (8 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT)
 
 #define DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT 18
-#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L0 (1 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
-#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L1 (2 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
-#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L2 (4 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
-#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L3 (8 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_NS (1 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_SEC (2 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_FLCN_LS (4 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
+#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_FLCN_HS (8 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
 
 #define SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU BIT(22)
 
diff --git a/bdk/mem/sdram.c b/bdk/mem/sdram.c
index 6eb265d..2ef4c6d 100644
--- a/bdk/mem/sdram.c
+++ b/bdk/mem/sdram.c
@@ -121,6 +121,14 @@ static void _sdram_req_mrr_data(u32 data, bool dual_channel)
 emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)
 {
 	emc_mr_data_t data;
+	u32 dual_channel = (EMC(EMC_FBIO_CFG7) >> 2) & 1;
+
+	// Clear left overs.
+	for (u32 i = 0; i < 32; i++)
+	{
+		(void)EMC(EMC_MRR);
+		usleep(1);
+	}
 
 	/*
 	 * When a dram chip has only one rank, then the info from the 2 ranks differs.
@@ -128,14 +136,23 @@ emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)
 	 */
 
 	// Get Device 0 (Rank 0) info from both dram chips (channels).
-	_sdram_req_mrr_data(BIT(31) | (mrx << 16), EMC_CHAN0);
+	_sdram_req_mrr_data((2u << 30) | (mrx << 16), dual_channel);
 	data.rank0_ch0 = EMC(EMC_MRR) & 0xFF;
 	data.rank0_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
 
-	// Get Device 1 (Rank 1) info from both dram chips (channels).
-	_sdram_req_mrr_data(BIT(30) | (mrx << 16), EMC_CHAN1);
-	data.rank1_ch0 = EMC(EMC_MRR) & 0xFF;
-	data.rank1_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
+	// If Rank 1 exists, get info.
+	if (EMC(EMC_ADR_CFG) & 1)
+	{
+		// Get Device 1 (Rank 1) info from both dram chips (channels).
+		_sdram_req_mrr_data((1u << 30) | (mrx << 16), dual_channel);
+		data.rank1_ch0 = EMC(EMC_MRR) & 0xFF;
+		data.rank1_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
+	}
+	else
+	{
+		data.rank1_ch0 = 0xFF;
+		data.rank1_ch1 = 0xFF;
+	}
 
 	return data;
 }