mirror of
https://github.com/CTCaer/hekate
synced 2024-12-22 19:31:12 +00:00
SD errata, bugfixes, replace hardcoded values
This commit is contained in:
parent
c9f5a2516f
commit
c43b6f8a5d
6 changed files with 55 additions and 28 deletions
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@ -378,8 +378,13 @@ int hos_launch(ini_sec_t *cfg)
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memset(&ctxt, 0, sizeof(launch_ctxt_t));
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memset(&ctxt, 0, sizeof(launch_ctxt_t));
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list_init(&ctxt.kip1_list);
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list_init(&ctxt.kip1_list);
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gfx_clear(&gfx_ctxt, 0xFF1B1B1B);
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gfx_con_setpos(&gfx_con, 0, 0);
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if (cfg && !_config(&ctxt, cfg))
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if (cfg && !_config(&ctxt, cfg))
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return 0;
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return 0;
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gfx_printf(&gfx_con, "Initializing...\n\n");
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//Read package1 and the correct keyblob.
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//Read package1 and the correct keyblob.
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if (!_read_emmc_pkg1(&ctxt))
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if (!_read_emmc_pkg1(&ctxt))
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@ -497,7 +502,7 @@ int hos_launch(ini_sec_t *cfg)
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break;
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break;
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}
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}
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//Clear 'BootConfig'.
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//Clear 'BootConfig' for retail systems.
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memset((void *)0x4003D000, 0, 0x3000);
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memset((void *)0x4003D000, 0, 0x3000);
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//pkg2_decrypt((void *)0xA9800000);
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//pkg2_decrypt((void *)0xA9800000);
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@ -995,7 +995,7 @@ int dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part)
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if(isSmallSdCard)
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if(isSmallSdCard)
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{
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{
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f_unlink(partialIdxFilename);
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f_unlink(partialIdxFilename);
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gfx_printf(&gfx_con, "%k%K\n\nYou can now join the files and get the complete raw eMMC dump.", 0xFFCCCCCC, 0xFF1B1B1B);
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gfx_printf(&gfx_con, "%k\n\nYou can now join the files\nand get the complete raw eMMC dump.", 0xFFCCCCCC);
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}
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}
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gfx_puts(&gfx_con, "\n\n");
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gfx_puts(&gfx_con, "\n\n");
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@ -1097,10 +1097,10 @@ static void dump_emmc_selected(dumpType_t dumpType)
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}
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}
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gfx_putc(&gfx_con, '\n');
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gfx_putc(&gfx_con, '\n');
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gfx_printf(&gfx_con, "%kTime taken: %d seconds.%k\n", 0xFF00FF96, (get_tmr() - timer) / 1000000, 0xFFCCCCCC);
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gfx_printf(&gfx_con, "Time taken: %d seconds.\n", (get_tmr() - timer) / 1000000);
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sdmmc_storage_end(&storage);
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sdmmc_storage_end(&storage);
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if (res)
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if (res)
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gfx_puts(&gfx_con, "\nFinished and verified!\nPress any key.\n");
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gfx_printf(&gfx_con, "\n%kFinished and verified!%k\nPress any key.\n",0xFF00FF96, 0xFFCCCCCC);
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out:;
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out:;
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btn_wait();
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btn_wait();
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3
ipl/sd.h
3
ipl/sd.h
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@ -86,6 +86,7 @@
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#define UHS_SDR50_BUS_SPEED 2
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#define UHS_SDR50_BUS_SPEED 2
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#define UHS_SDR104_BUS_SPEED 3
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#define UHS_SDR104_BUS_SPEED 3
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#define UHS_DDR50_BUS_SPEED 4
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#define UHS_DDR50_BUS_SPEED 4
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#define HS400_BUS_SPEED 5
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/*
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/*
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* SD_SWITCH mode
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* SD_SWITCH mode
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@ -102,6 +103,6 @@
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* SD_SWITCH access modes
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* SD_SWITCH access modes
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*/
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*/
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#define SD_SWITCH_ACCESS_DEF 0
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#define SD_SWITCH_ACCESS_DEF 0
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#define SD_SWITCH_ACCESS_HS 1
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#define SD_SWITCH_ACCESS_HS 1
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#endif /* LINUX_MMC_SD_H */
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#endif /* LINUX_MMC_SD_H */
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@ -204,32 +204,34 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
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case 1:
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case 1:
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case 5:
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case 5:
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case 6:
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case 6:
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sdmmc->regs->hostctl &= 0xFB;
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sdmmc->regs->hostctl &= 0xFB; //Should this be 0xFFFB (~4) ?
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sdmmc->regs->hostctl2 &= 0xFFF7;
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sdmmc->regs->hostctl2 &= SDHCI_CTRL_VDD_330;
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break;
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break;
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case 2:
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case 2:
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case 7:
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case 7:
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sdmmc->regs->hostctl |= 4;
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sdmmc->regs->hostctl |= 4;
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sdmmc->regs->hostctl2 &= 0xFFF7;
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sdmmc->regs->hostctl2 &= SDHCI_CTRL_VDD_330;
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break;
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break;
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case 3:
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case 3:
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case 11:
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case 11:
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case 13:
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case 13:
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case 14:
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case 14:
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & 0xFFF8) | 3;
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR104_BUS_SPEED;
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sdmmc->regs->hostctl2 |= 8;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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break;
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case 4:
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case 4:
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & 0xFFF8) | 5;
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//Non standard
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sdmmc->regs->hostctl2 |= 8;
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | HS400_BUS_SPEED;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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break;
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case 8:
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case 8:
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sdmmc->regs->hostctl2 = sdmmc->regs->hostctl2 & 0xFFF8;
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR12_BUS_SPEED;
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sdmmc->regs->hostctl2 |= 8;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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break;
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case 10:
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case 10:
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & 0xFFF8) | 2;
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//T210 Errata for SDR50, the host must be set to SDR104.
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sdmmc->regs->hostctl2 |= 8;
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR104_BUS_SPEED;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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break;
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}
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}
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@ -551,16 +553,16 @@ int sdmmc_config_tuning(sdmmc_t *sdmmc, u32 type, u32 cmd)
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sdmmc->regs->field_1C0 = (sdmmc->regs->field_1C0 & 0xFFFF1FFF) | flag;
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sdmmc->regs->field_1C0 = (sdmmc->regs->field_1C0 & 0xFFFF1FFF) | flag;
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sdmmc->regs->field_1C0 = (sdmmc->regs->field_1C0 & 0xFFFFE03F) | 0x40;
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sdmmc->regs->field_1C0 = (sdmmc->regs->field_1C0 & 0xFFFFE03F) | 0x40;
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sdmmc->regs->field_1C0 |= 0x20000;
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sdmmc->regs->field_1C0 |= 0x20000;
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sdmmc->regs->hostctl2 |= 0x40;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_EXEC_TUNING;
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for (u32 i = 0; i < max; i++)
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for (u32 i = 0; i < max; i++)
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{
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{
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_sdmmc_config_tuning_once(sdmmc, cmd);
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_sdmmc_config_tuning_once(sdmmc, cmd);
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if (!(sdmmc->regs->hostctl2 & 0x40))
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if (!(sdmmc->regs->hostctl2 & SDHCI_CTRL_EXEC_TUNING))
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break;
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break;
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}
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}
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if (sdmmc->regs->hostctl2 & 0x80)
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if (sdmmc->regs->hostctl2 & SDHCI_CTRL_TUNED_CLK)
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return 1;
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return 1;
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return 0;
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return 0;
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}
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}
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@ -577,14 +579,14 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc)
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return 0;
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return 0;
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}
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}
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sdmmc->regs->hostctl2 &= 0x7FFF;
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sdmmc->regs->hostctl2 &= ~SDHCI_CTRL_PRESET_VAL_EN;
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sdmmc->regs->clkcon &= ~TEGRA_MMC_CLKCON_CLKGEN_SELECT;
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sdmmc->regs->clkcon &= ~TEGRA_MMC_CLKCON_CLKGEN_SELECT;
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sdmmc->regs->hostctl2 |= 0x1000;
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sdmmc->regs->hostctl2 |= SDHCI_HOST_VERSION_4_EN;
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if (!(sdmmc->regs->capareg & 0x10000000))
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if (!(sdmmc->regs->capareg & 0x10000000))
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return 0;
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return 0;
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sdmmc->regs->hostctl2 |= 0x2000;
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sdmmc->regs->hostctl2 |= SDHCI_ADDRESSING_64BIT_EN;
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sdmmc->regs->hostctl &= 0xE7;
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sdmmc->regs->hostctl &= 0xE7;
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sdmmc->regs->timeoutcon = (sdmmc->regs->timeoutcon & 0xF0) | 0xE;
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sdmmc->regs->timeoutcon = (sdmmc->regs->timeoutcon & 0xF0) | 0xE;
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@ -1076,7 +1078,7 @@ int sdmmc_enable_low_voltage(sdmmc_t *sdmmc)
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_sdmmc_get_clkcon(sdmmc);
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_sdmmc_get_clkcon(sdmmc);
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sleep(5000);
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sleep(5000);
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if (sdmmc->regs->hostctl2 & 8)
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if (sdmmc->regs->hostctl2 & SDHCI_CTRL_VDD_180)
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{
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{
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sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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_sdmmc_get_clkcon(sdmmc);
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_sdmmc_get_clkcon(sdmmc);
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@ -45,9 +45,28 @@
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#define SDMMC_RSP_TYPE_5 5
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#define SDMMC_RSP_TYPE_5 5
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/*! SDMMC mask interrupt status. */
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/*! SDMMC mask interrupt status. */
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#define SDMMC_MASKINT_MASKED 0
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#define SDMMC_MASKINT_MASKED 0
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#define SDMMC_MASKINT_NOERROR -1
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#define SDMMC_MASKINT_NOERROR -1
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#define SDMMC_MASKINT_ERROR -2
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#define SDMMC_MASKINT_ERROR -2
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/*! SDMMC host control 2 */
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#define SDHCI_CTRL_UHS_MASK 0xFFF8
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#define SDHCI_CTRL_VDD_330 0xFFF7
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#define SDHCI_CTRL_VDD_180 8
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#define SDHCI_CTRL_EXEC_TUNING 0x40
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#define SDHCI_CTRL_TUNED_CLK 0x80
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#define SDHCI_HOST_VERSION_4_EN 0x1000
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#define SDHCI_ADDRESSING_64BIT_EN 0x2000
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#define SDHCI_CTRL_PRESET_VAL_EN 0x8000
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/*! SD bus speeds. */
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#define UHS_SDR12_BUS_SPEED 0
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#define HIGH_SPEED_BUS_SPEED 1
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#define UHS_SDR25_BUS_SPEED 1
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#define UHS_SDR50_BUS_SPEED 2
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#define UHS_SDR104_BUS_SPEED 3
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#define UHS_DDR50_BUS_SPEED 4
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#define HS400_BUS_SPEED 5
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/*! Helper for SWITCH command argument. */
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/*! Helper for SWITCH command argument. */
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#define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))
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#define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))
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@ -25,7 +25,7 @@ void tui_pbar(gfx_con_t *con, int x, int y, u32 val, u32 fgcol, u32 bgcol)
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gfx_con_setpos(con, x, y);
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gfx_con_setpos(con, x, y);
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gfx_printf(con, "%k[%3d%%]%k", fgcol, val, bgcol);
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gfx_printf(con, "%k[%3d%%]%k", fgcol, val, 0xFFCCCCCC);
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x += 7 * 8;
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x += 7 * 8;
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