diff --git a/bdk/soc/clock.c b/bdk/soc/clock.c
index 92fab67..f4d9e92 100644
--- a/bdk/soc/clock.c
+++ b/bdk/soc/clock.c
@@ -783,15 +783,25 @@ u32 clock_get_osc_freq()
 
 u32 clock_get_dev_freq(clock_pto_id_t id)
 {
-	u32 val = ((id & PTO_SRC_SEL_MASK) << PTO_SRC_SEL_SHIFT) | PTO_DIV_SEL_DIV1 | PTO_CLK_ENABLE | (16 - 1); // 16 periods of 32.76KHz window.
+	const u32 pto_win = 16;
+	const u32 pto_osc = 32768;
+
+	u32 val = ((id & PTO_SRC_SEL_MASK) << PTO_SRC_SEL_SHIFT) | PTO_DIV_SEL_DIV1 | PTO_CLK_ENABLE | (pto_win - 1);
 	CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val;
+	(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
 	usleep(2);
+
 	CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val | PTO_CNT_RST;
+	(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
 	usleep(2);
+
 	CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val;
+	(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
 	usleep(2);
+
 	CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val | PTO_CNT_EN;
-	usleep(502);
+	(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
+	usleep((1000000 * pto_win / pto_osc) + 12 + 2);
 
 	while (CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS) & PTO_CLK_CNT_BUSY)
 		;
@@ -799,9 +809,11 @@ u32 clock_get_dev_freq(clock_pto_id_t id)
 	u32 cnt = CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS) & PTO_CLK_CNT;
 
 	CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = 0;
+	(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
+	usleep(2);
 
-	u32 freq = ((cnt << 8) | 0x3E) / 125;
+	u32 freq_khz = (u64)cnt * pto_osc / pto_win / 1000;
 
-	return freq;
+	return freq_khz;
 }
 
diff --git a/bdk/soc/clock.h b/bdk/soc/clock.h
index 7821bd2..32afe8d 100644
--- a/bdk/soc/clock.h
+++ b/bdk/soc/clock.h
@@ -217,7 +217,7 @@
 #define OSC_FREQ_DET_BUSY        BIT(31)
 #define OSC_FREQ_DET_CNT         0xFFFF
 
-/*! PLLs omitted as they need PTO enabled in MISC registers. Norm div is 2. */
+/*! PTO IDs. */
 typedef enum _clock_pto_id_t
 {
 	CLK_PTO_PCLK_SYS =          0x06,
@@ -241,6 +241,9 @@ typedef enum _clock_pto_id_t
 	CLK_PTO_SDMMC4 =            0x23,
 	CLK_PTO_EMC =               0x24,
 
+	CLK_PTO_CCLK_LP =           0x2B,
+	CLK_PTO_CCLK_LP_DIV2 =      0x2C,
+
 	CLK_PTO_MSELECT =           0x2F,
 
 	CLK_PTO_VIC =               0x36,
@@ -323,6 +326,32 @@ typedef enum _clock_pto_id_t
 	CLK_PTO_XUSB_SS_HOST_DEV =  0x137,
 	CLK_PTO_XUSB_CORE_HOST =    0x138,
 	CLK_PTO_XUSB_CORE_DEV =     0x139,
+
+	/*
+	 * PLL need PTO enabled in MISC registers.
+	 * Normal div is 2 so result is multiplied with it.
+	 */
+	CLK_PTO_PLLC_DIV2 =              0x01,
+	CLK_PTO_PLLM_DIV2 =              0x02,
+	CLK_PTO_PLLP_DIV2 =              0x03,
+	CLK_PTO_PLLA_DIV2 =              0x04,
+	CLK_PTO_PLLX_DIV2 =              0x05,
+
+	CLK_PTO_PLLMB_DIV2 =             0x25,
+
+	CLK_PTO_PLLC4_DIV2 =             0x51,
+
+	CLK_PTO_PLLA1_DIV2 =             0x55,
+	CLK_PTO_PLLC2_DIV2 =             0x58,
+	CLK_PTO_PLLC3_DIV2 =             0x5A,
+
+	CLK_PTO_PLLD_DIV2 =              0xCB,
+	CLK_PTO_PLLD2_DIV2 =             0xCD,
+	CLK_PTO_PLLDP_DIV2 =             0xCF,
+
+	CLK_PTO_PLLU_DIV2 =              0x10D,
+
+	CLK_PTO_PLLREFE_DIV2 =           0x10F,
 } clock_pto_id_t;
 
 /*