mirror of
https://github.com/CTCaer/hekate
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Name various t210 registers
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CTCaer
parent
cadb95e3ce
commit
b4d2df8111
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@ -62,6 +62,7 @@
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#define PINMUX_AUX_LCD_BL_PWM 0x1FC
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#define PINMUX_AUX_LCD_BL_EN 0x200
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#define PINMUX_AUX_LCD_RST 0x204
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#define PINMUX_AUX_LCD_GPIO1 0x208
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#define PINMUX_AUX_LCD_GPIO2 0x20C
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#define PINMUX_AUX_TOUCH_INT 0x220
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#define PINMUX_AUX_MOTION_INT 0x224
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@ -28,9 +28,11 @@
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#define VIC_BASE 0x54340000
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#define TSEC_BASE 0x54500000
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#define SOR1_BASE 0x54580000
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#define ICTLR_BASE 0x60004000
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#define TMR_BASE 0x60005000
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#define CLOCK_BASE 0x60006000
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#define FLOW_CTLR_BASE 0x60007000
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#define AHBDMA_BASE 0x60008000
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#define SYSREG_BASE 0x6000C000
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#define SB_BASE (SYSREG_BASE + 0x200)
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#define GPIO_BASE 0x6000D000
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@ -44,6 +46,7 @@
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#define GPIO_8_BASE (GPIO_BASE + 0x700)
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#define EXCP_VEC_BASE 0x6000F000
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#define IPATCH_BASE 0x6001DC00
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#define APBDMA_BASE 0x60020000
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#define APB_MISC_BASE 0x70000000
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#define PINMUX_AUX_BASE 0x70003000
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#define UART_BASE 0x70006000
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@ -56,10 +59,16 @@
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#define SE_BASE 0x70012000
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#define MC_BASE 0x70019000
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#define EMC_BASE 0x7001B000
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#define EMC0_BASE 0x7001E000
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#define EMC1_BASE 0x7001F000
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#define MIPI_CAL_BASE 0x700E3000
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#define CL_DVFS_BASE 0x70110000
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#define I2S_BASE 0x702D1000
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#define ADMA_BASE 0x702E2000
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#define TZRAM_BASE 0x7C010000
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#define USB_BASE 0x7D000000
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#define USB_OTG_BASE USB_BASE
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#define USB1_BASE 0x7D004000
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#define _REG(base, off) *(vu32 *)((base) + (off))
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@ -70,10 +79,12 @@
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#define VIC(off) _REG(VIC_BASE, off)
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#define TSEC(off) _REG(TSEC_BASE, off)
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#define SOR1(off) _REG(SOR1_BASE, off)
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#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * cidx), off)
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#define TMR(off) _REG(TMR_BASE, off)
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#define CLOCK(off) _REG(CLOCK_BASE, off)
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#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
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#define SYSREG(off) _REG(SYSREG_BASE, off)
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#define AHB_GIZMO(off) _REG(SYSREG_BASE, off)
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#define SB(off) _REG(SB_BASE, off)
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#define GPIO(off) _REG(GPIO_BASE, off)
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#define GPIO_1(off) _REG(GPIO_1_BASE, off)
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@ -96,9 +107,14 @@
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#define SE(off) _REG(SE_BASE, off)
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#define MC(off) _REG(MC_BASE, off)
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#define EMC(off) _REG(EMC_BASE, off)
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#define EMC_CH0(off) _REG(EMC0_BASE, off)
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#define EMC_CH1(off) _REG(EMC1_BASE, off)
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#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
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#define I2S(off) _REG(I2S_BASE, off)
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#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
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#define I2S(off) _REG(I2S_BASE, off)
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#define ADMA(off) _REG(ADMA_BASE, off)
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#define USB(off) _REG(USB_BASE, off)
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#define USB1(off) _REG(USB1_BASE, off)
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#define TEST_REG(off) _REG(0x0, off)
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/* HOST1X registers. */
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@ -116,13 +132,40 @@
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#define EVP_COP_RSVD_VECTOR 0x214
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#define EVP_COP_IRQ_VECTOR 0x218
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#define EVP_COP_FIQ_VECTOR 0x21C
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#define EVP_COP_IRQ_STS 0x220
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/*! Primary Interrupt Controller registers. */
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#define PRI_ICTLR_FIR 0x14
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#define PRI_ICTLR_FIR_SET 0x18
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#define PRI_ICTLR_FIR_CLR 0x1C
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#define PRI_ICTLR_CPU_IER 0x20
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#define PRI_ICTLR_CPU_IER_SET 0x24
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#define PRI_ICTLR_CPU_IER_CLR 0x28
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#define PRI_ICTLR_CPU_IEP_CLASS 0x2C
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#define PRI_ICTLR_COP_IER 0x30
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#define PRI_ICTLR_COP_IER_SET 0x34
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#define PRI_ICTLR_COP_IER_CLR 0x38
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#define PRI_ICTLR_COP_IEP_CLASS 0x3C
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/*! AHB Gizmo registers. */
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#define AHB_ARBITRATION_PRIORITY_CTRL 0x8
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#define ARBITRATION_PRIORITY_CTRL_ENB_FAST_REARBITRATE (1 << 6)
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#define AHB_GIZMO_AHB_MEM 0x10
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#define AHB_MEM_ENB_FAST_REARBITRATE (1 << 2)
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#define AHB_GIZMO_USB 0x20
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#define AHB_GIZMO_USB_IMMEDIATE (1 << 18)
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#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0
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#define MEM_PREFETCH_ENABLE (1 << 31)
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#define MEM_PREFETCH_AHB_MST_USB 6
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/*! Misc registers. */
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#define APB_MISC_PP_STRAPPING_OPT_A 0x08
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#define APB_MISC_PP_PINMUX_GLOBAL 0x40
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#define APB_MISC_GP_HIDREV 0x804
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#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
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#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
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#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
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#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
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#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
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@ -170,9 +213,14 @@
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/*! TMR registers. */
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#define TIMERUS_CNTR_1US (0x10 + 0x0)
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#define TIMERUS_USEC_CFG (0x10 + 0x4)
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#define TIMER_TMR8_TMR_PTV 0x78
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#define TIMER_TMR9_TMR_PTV 0x80
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#define TIMER_EN (1 << 31)
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#define TIMER_PER_EN (1 << 30)
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#define TIMER_EN (1 << 31)
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#define TIMER_PER_EN (1 << 30)
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#define TIMER_TMR8_TMR_PCR 0x7C
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#define TIMER_TMR9_TMR_PCR 0x8C
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#define TIMER_INTR_CLR (1 << 30)
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#define TIMER_WDT4_CONFIG (0x100 + 0x80)
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#define TIMER_SRC(TMR) (TMR & 0xF)
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#define TIMER_PER(PER) ((PER & 0xFF) << 4)
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@ -210,13 +258,15 @@
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/*! Flow controller registers. */
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#define FLOW_CTLR_HALT_COP_EVENTS 0x4
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#define HALT_COP_SEC (1 << 23)
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#define HALT_COP_MSEC (1 << 24)
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#define HALT_COP_USEC (1 << 25)
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#define HALT_COP_JTAG (1 << 28)
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#define HALT_COP_WAIT_EVENT (1 << 30)
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#define HALT_COP_WAIT_IRQ (1 << 31)
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#define HALT_COP_MAX_CNT 0xFF
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#define HALT_COP_GIC_IRQ (1 << 9)
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#define HALT_COP_LIC_IRQ (1 << 11)
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#define HALT_COP_SEC (1 << 23)
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#define HALT_COP_MSEC (1 << 24)
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#define HALT_COP_USEC (1 << 25)
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#define HALT_COP_JTAG (1 << 28)
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#define HALT_COP_WAIT_EVENT (1 << 30)
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#define HALT_COP_STOP_UNTIL_IRQ (1 << 31)
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#define HALT_COP_MAX_CNT 0xFF
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#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
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#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
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#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
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@ -228,4 +278,9 @@
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#define FLOW_CTLR_RAM_REPAIR 0x40
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#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
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/*! USB controller registers. */
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#define USB1_UTMIP_BAT_CHRG_CFG0 0x830
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#define BAT_CHRG_CFG0_OP_SRC_EN (1 << 3)
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#define BAT_CHRG_CFG0_PWRDOWN_CHRG (1 << 0)
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#endif
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@ -62,6 +62,7 @@
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#define PINMUX_AUX_LCD_BL_PWM 0x1FC
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#define PINMUX_AUX_LCD_BL_EN 0x200
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#define PINMUX_AUX_LCD_RST 0x204
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#define PINMUX_AUX_LCD_GPIO1 0x208
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#define PINMUX_AUX_LCD_GPIO2 0x20C
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#define PINMUX_AUX_TOUCH_INT 0x220
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#define PINMUX_AUX_MOTION_INT 0x224
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@ -28,9 +28,11 @@
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#define VIC_BASE 0x54340000
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#define TSEC_BASE 0x54500000
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#define SOR1_BASE 0x54580000
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#define ICTLR_BASE 0x60004000
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#define TMR_BASE 0x60005000
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#define CLOCK_BASE 0x60006000
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#define FLOW_CTLR_BASE 0x60007000
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#define AHBDMA_BASE 0x60008000
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#define SYSREG_BASE 0x6000C000
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#define SB_BASE (SYSREG_BASE + 0x200)
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#define GPIO_BASE 0x6000D000
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@ -44,6 +46,7 @@
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#define GPIO_8_BASE (GPIO_BASE + 0x700)
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#define EXCP_VEC_BASE 0x6000F000
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#define IPATCH_BASE 0x6001DC00
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#define APBDMA_BASE 0x60020000
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#define APB_MISC_BASE 0x70000000
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#define PINMUX_AUX_BASE 0x70003000
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#define UART_BASE 0x70006000
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@ -56,10 +59,16 @@
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#define SE_BASE 0x70012000
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#define MC_BASE 0x70019000
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#define EMC_BASE 0x7001B000
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#define EMC0_BASE 0x7001E000
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#define EMC1_BASE 0x7001F000
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#define MIPI_CAL_BASE 0x700E3000
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#define CL_DVFS_BASE 0x70110000
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#define I2S_BASE 0x702D1000
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#define ADMA_BASE 0x702E2000
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#define TZRAM_BASE 0x7C010000
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#define USB_BASE 0x7D000000
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#define USB_OTG_BASE USB_BASE
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#define USB1_BASE 0x7D004000
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#define _REG(base, off) *(vu32 *)((base) + (off))
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@ -70,10 +79,12 @@
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#define VIC(off) _REG(VIC_BASE, off)
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#define TSEC(off) _REG(TSEC_BASE, off)
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#define SOR1(off) _REG(SOR1_BASE, off)
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#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * cidx), off)
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#define TMR(off) _REG(TMR_BASE, off)
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#define CLOCK(off) _REG(CLOCK_BASE, off)
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#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
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#define SYSREG(off) _REG(SYSREG_BASE, off)
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#define AHB_GIZMO(off) _REG(SYSREG_BASE, off)
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#define SB(off) _REG(SB_BASE, off)
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#define GPIO(off) _REG(GPIO_BASE, off)
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#define GPIO_1(off) _REG(GPIO_1_BASE, off)
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@ -96,9 +107,14 @@
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#define SE(off) _REG(SE_BASE, off)
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#define MC(off) _REG(MC_BASE, off)
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#define EMC(off) _REG(EMC_BASE, off)
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#define EMC_CH0(off) _REG(EMC0_BASE, off)
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#define EMC_CH1(off) _REG(EMC1_BASE, off)
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#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
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#define I2S(off) _REG(I2S_BASE, off)
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#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
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#define I2S(off) _REG(I2S_BASE, off)
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#define ADMA(off) _REG(ADMA_BASE, off)
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#define USB(off) _REG(USB_BASE, off)
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#define USB1(off) _REG(USB1_BASE, off)
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#define TEST_REG(off) _REG(0x0, off)
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/* HOST1X registers. */
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@ -116,13 +132,40 @@
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#define EVP_COP_RSVD_VECTOR 0x214
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#define EVP_COP_IRQ_VECTOR 0x218
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#define EVP_COP_FIQ_VECTOR 0x21C
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#define EVP_COP_IRQ_STS 0x220
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/*! Primary Interrupt Controller registers. */
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#define PRI_ICTLR_FIR 0x14
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#define PRI_ICTLR_FIR_SET 0x18
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#define PRI_ICTLR_FIR_CLR 0x1C
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#define PRI_ICTLR_CPU_IER 0x20
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#define PRI_ICTLR_CPU_IER_SET 0x24
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#define PRI_ICTLR_CPU_IER_CLR 0x28
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#define PRI_ICTLR_CPU_IEP_CLASS 0x2C
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#define PRI_ICTLR_COP_IER 0x30
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#define PRI_ICTLR_COP_IER_SET 0x34
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#define PRI_ICTLR_COP_IER_CLR 0x38
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#define PRI_ICTLR_COP_IEP_CLASS 0x3C
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/*! AHB Gizmo registers. */
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#define AHB_ARBITRATION_PRIORITY_CTRL 0x8
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#define ARBITRATION_PRIORITY_CTRL_ENB_FAST_REARBITRATE (1 << 6)
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#define AHB_GIZMO_AHB_MEM 0x10
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#define AHB_MEM_ENB_FAST_REARBITRATE (1 << 2)
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#define AHB_GIZMO_USB 0x20
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#define AHB_GIZMO_USB_IMMEDIATE (1 << 18)
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#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0
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#define MEM_PREFETCH_ENABLE (1 << 31)
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#define MEM_PREFETCH_AHB_MST_USB 6
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/*! Misc registers. */
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#define APB_MISC_PP_STRAPPING_OPT_A 0x08
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#define APB_MISC_PP_PINMUX_GLOBAL 0x40
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#define APB_MISC_GP_HIDREV 0x804
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#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
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#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
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#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
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#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
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#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
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@ -170,9 +213,14 @@
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/*! TMR registers. */
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#define TIMERUS_CNTR_1US (0x10 + 0x0)
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#define TIMERUS_USEC_CFG (0x10 + 0x4)
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#define TIMER_TMR8_TMR_PTV 0x78
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#define TIMER_TMR9_TMR_PTV 0x80
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#define TIMER_EN (1 << 31)
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#define TIMER_PER_EN (1 << 30)
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#define TIMER_EN (1 << 31)
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#define TIMER_PER_EN (1 << 30)
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#define TIMER_TMR8_TMR_PCR 0x7C
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#define TIMER_TMR9_TMR_PCR 0x8C
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#define TIMER_INTR_CLR (1 << 30)
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#define TIMER_WDT4_CONFIG (0x100 + 0x80)
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#define TIMER_SRC(TMR) (TMR & 0xF)
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#define TIMER_PER(PER) ((PER & 0xFF) << 4)
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@ -210,13 +258,15 @@
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/*! Flow controller registers. */
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#define FLOW_CTLR_HALT_COP_EVENTS 0x4
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#define HALT_COP_SEC (1 << 23)
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#define HALT_COP_MSEC (1 << 24)
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#define HALT_COP_USEC (1 << 25)
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#define HALT_COP_JTAG (1 << 28)
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#define HALT_COP_WAIT_EVENT (1 << 30)
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#define HALT_COP_WAIT_IRQ (1 << 31)
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#define HALT_COP_MAX_CNT 0xFF
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#define HALT_COP_GIC_IRQ (1 << 9)
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#define HALT_COP_LIC_IRQ (1 << 11)
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#define HALT_COP_SEC (1 << 23)
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#define HALT_COP_MSEC (1 << 24)
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#define HALT_COP_USEC (1 << 25)
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#define HALT_COP_JTAG (1 << 28)
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#define HALT_COP_WAIT_EVENT (1 << 30)
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#define HALT_COP_STOP_UNTIL_IRQ (1 << 31)
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#define HALT_COP_MAX_CNT 0xFF
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#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
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#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
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#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
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@ -228,4 +278,9 @@
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#define FLOW_CTLR_RAM_REPAIR 0x40
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#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
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/*! USB controller registers. */
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#define USB1_UTMIP_BAT_CHRG_CFG0 0x830
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#define BAT_CHRG_CFG0_OP_SRC_EN (1 << 3)
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#define BAT_CHRG_CFG0_PWRDOWN_CHRG (1 << 0)
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#endif
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