mirror of
https://github.com/CTCaer/hekate
synced 2024-12-22 19:31:12 +00:00
display: Provide dsi command reading/writing to user
These work while video stream is either disabled or enabled.
This commit is contained in:
parent
cf175fc00d
commit
aaaf470dcf
2 changed files with 318 additions and 10 deletions
165
bdk/gfx/di.c
165
bdk/gfx/di.c
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@ -54,6 +54,164 @@ static void _display_dsi_send_cmd(u8 cmd, u32 param, u32 wait)
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usleep(wait);
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usleep(wait);
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}
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}
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static void _display_dsi_read_rx_fifo(u32 *data)
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{
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u32 fifo_count = DSI(_DSIREG(DSI_STATUS)) & DSI_STATUS_RX_FIFO_SIZE;
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for (u32 i = 0; i < fifo_count; i++)
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{
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// Read or Drain RX FIFO.
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if (data)
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data[i] = DSI(_DSIREG(DSI_RD_DATA));
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else
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(void)DSI(_DSIREG(DSI_RD_DATA));
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}
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}
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int display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled)
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{
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int res = 0;
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u32 host_control = 0;
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u32 cmd_timeout = video_enabled ? 0 : 250000;
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u32 fifo[DSI_STATUS_RX_FIFO_SIZE] = {0};
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// Drain RX FIFO.
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_display_dsi_read_rx_fifo(NULL);
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// Save host control and enable host cmd packets during video.
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if (video_enabled)
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{
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host_control = DSI(_DSIREG(DSI_HOST_CONTROL));
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// Enable vblank interrupt.
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DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = DC_CMD_INT_FRAME_END_INT;
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// Use the 4th line to transmit the host cmd packet.
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE | DSI_DSI_LINE_TYPE(4);
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// Wait for vblank before starting the transfer.
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
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while (DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT)
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;
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}
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// Set reply size.
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_display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
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_display_dsi_wait(cmd_timeout, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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// Request register read.
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_display_dsi_send_cmd(MIPI_DSI_DCS_READ, cmd, 0);
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_display_dsi_wait(cmd_timeout, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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// Transfer bus control to device for transmitting the reply.
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u32 high_speed = video_enabled ? DSI_HOST_CONTROL_HS : 0;
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DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC | high_speed;
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_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
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// Wait a bit for the reply.
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usleep(5000);
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// Read RX FIFO.
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_display_dsi_read_rx_fifo(fifo);
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// Parse packet and copy over the data.
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if ((fifo[0] & 0xFF) == DSI_ESCAPE_CMD)
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{
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// Act based on reply type.
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switch (fifo[1] & 0xFF)
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{
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case GEN_LONG_RD_RES:
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case DCS_LONG_RD_RES:
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memcpy(data, &fifo[2], MIN((fifo[1] >> 8) & 0xFFFF, len));
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break;
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case GEN_1_BYTE_SHORT_RD_RES:
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case DCS_1_BYTE_SHORT_RD_RES:
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memcpy(data, &fifo[2], 1);
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break;
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case GEN_2_BYTE_SHORT_RD_RES:
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case DCS_2_BYTE_SHORT_RD_RES:
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memcpy(data, &fifo[2], 2);
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break;
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case ACK_ERROR_RES:
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default:
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res = 1;
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break;
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}
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}
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// Disable host cmd packets during video and restore host control.
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if (video_enabled)
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{
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// Wait for vblank before reseting sync points.
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
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while (DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT)
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;
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// Reset all states of syncpt block.
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DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = DSI_INCR_SYNCPT_SOFT_RESET;
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usleep(300); // Stabilization delay.
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// Clear syncpt block reset.
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DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = 0;
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usleep(300); // Stabilization delay.
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// Restore video mode and host control.
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
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DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control;
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// Disable and clear vblank interrupt.
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DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = 0;
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT;
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}
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return res;
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}
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void display_dsi_write(u8 cmd, u32 len, void *data, bool video_enabled)
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{
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u32 host_control;
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u32 fifo32[DSI_STATUS_RX_FIFO_SIZE] = {0};
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u8 *fifo8 = (u8 *)fifo32;
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// Enable host cmd packets during video and save host control.
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if (video_enabled)
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE;
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host_control = DSI(_DSIREG(DSI_HOST_CONTROL));
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// Enable host transfer trigger.
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DSI(_DSIREG(DSI_HOST_CONTROL)) |= DSI_HOST_CONTROL_TX_TRIG_HOST;
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switch (len)
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{
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case 0:
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
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break;
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case 1:
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd | (*(u8 *)data << 8), 0);
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break;
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default:
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fifo32[0] = (len << 8) | MIPI_DSI_DCS_LONG_WRITE;
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fifo8[4] = cmd;
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memcpy(&fifo8[5], data, len);
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len += 4 + 1; // Increase length by CMD/length word and DCS CMD.
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for (u32 i = 0; i < (ALIGN(len, 4) / 4); i++)
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DSI(_DSIREG(DSI_WR_DATA)) = fifo32[i];
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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break;
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}
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// Wait for the write to happen.
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST);
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// Disable host cmd packets during video and restore host control.
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if (video_enabled)
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
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DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control;
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}
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void display_init()
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void display_init()
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{
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{
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// Check if display is already initialized.
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// Check if display is already initialized.
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@ -175,6 +333,11 @@ void display_init()
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// Setup DSI device takeover timeout.
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// Setup DSI device takeover timeout.
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DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
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DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
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#if 0
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// Get Display ID.
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_display_id = 0xCCCCCC;
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display_dsi_read(MIPI_DCS_GET_DISPLAY_ID, 3, &_display_id, DSI_VIDEO_DISABLED);
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#else
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// Set reply size.
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// Set reply size.
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_display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 3, 0);
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_display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 3, 0);
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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@ -193,7 +356,7 @@ void display_init()
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// MIPI_DCS_GET_DISPLAY_ID reply is a long read, size 3 x u32.
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// MIPI_DCS_GET_DISPLAY_ID reply is a long read, size 3 x u32.
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for (u32 i = 0; i < 3; i++)
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for (u32 i = 0; i < 3; i++)
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_display_id = DSI(_DSIREG(DSI_RD_DATA)) & 0xFFFFFF; // Skip ack and msg type info and get the payload (display id).
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_display_id = DSI(_DSIREG(DSI_RD_DATA)) & 0xFFFFFF; // Skip ack and msg type info and get the payload (display id).
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#endif
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// Save raw Display ID to Nyx storage.
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// Save raw Display ID to Nyx storage.
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nyx_str->info.disp_id = _display_id;
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nyx_str->info.disp_id = _display_id;
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147
bdk/gfx/di.h
147
bdk/gfx/di.h
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@ -21,6 +21,9 @@
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#include <memory_map.h>
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#include <memory_map.h>
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#include <utils/types.h>
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#include <utils/types.h>
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#define DSI_VIDEO_DISABLED 0
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#define DSI_VIDEO_ENABLED 1
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/*! Display registers. */
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/*! Display registers. */
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#define _DIREG(reg) ((reg) * 4)
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#define _DIREG(reg) ((reg) * 4)
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@ -68,6 +71,7 @@
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#define DC_CMD_INT_STATUS 0x37
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#define DC_CMD_INT_STATUS 0x37
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#define DC_CMD_INT_MASK 0x38
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#define DC_CMD_INT_MASK 0x38
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#define DC_CMD_INT_ENABLE 0x39
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#define DC_CMD_INT_ENABLE 0x39
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#define DC_CMD_INT_FRAME_END_INT BIT(1)
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#define DC_CMD_STATE_ACCESS 0x40
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#define DC_CMD_STATE_ACCESS 0x40
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#define READ_MUX BIT(0)
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#define READ_MUX BIT(0)
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@ -360,6 +364,10 @@
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/*! Display serial interface registers. */
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/*! Display serial interface registers. */
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#define _DSIREG(reg) ((reg) * 4)
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#define _DSIREG(reg) ((reg) * 4)
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#define DSI_INCR_SYNCPT_CNTRL 0x1
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#define DSI_INCR_SYNCPT_SOFT_RESET BIT(0)
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#define DSI_INCR_SYNCPT_NO_STALL BIT(8)
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#define DSI_RD_DATA 0x9
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#define DSI_RD_DATA 0x9
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#define DSI_WR_DATA 0xA
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#define DSI_WR_DATA 0xA
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@ -403,7 +411,10 @@
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#define DSI_TRIGGER_HOST BIT(1)
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#define DSI_TRIGGER_HOST BIT(1)
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#define DSI_TX_CRC 0x14
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#define DSI_TX_CRC 0x14
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#define DSI_STATUS 0x15
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#define DSI_STATUS 0x15
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#define DSI_STATUS_RX_FIFO_SIZE 0x1F
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#define DSI_INIT_SEQ_CONTROL 0x1A
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#define DSI_INIT_SEQ_CONTROL 0x1A
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#define DSI_INIT_SEQ_DATA_0 0x1B
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#define DSI_INIT_SEQ_DATA_0 0x1B
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#define DSI_INIT_SEQ_DATA_1 0x1C
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#define DSI_INIT_SEQ_DATA_1 0x1C
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@ -450,6 +461,7 @@
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#define DSI_PAD_CONTROL_CD 0x4C
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#define DSI_PAD_CONTROL_CD 0x4C
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#define DSI_VIDEO_MODE_CONTROL 0x4E
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#define DSI_VIDEO_MODE_CONTROL 0x4E
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#define DSI_CMD_PKT_VID_ENABLE 1
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#define DSI_CMD_PKT_VID_ENABLE 1
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#define DSI_DSI_LINE_TYPE(x) ((x) << 1)
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#define DSI_PAD_CONTROL_1 0x4F
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#define DSI_PAD_CONTROL_1 0x4F
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#define DSI_PAD_CONTROL_2 0x50
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#define DSI_PAD_CONTROL_2 0x50
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@ -467,6 +479,18 @@
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#define DSI_INIT_SEQ_DATA_15 0x5F
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#define DSI_INIT_SEQ_DATA_15 0x5F
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#define DSI_INIT_SEQ_DATA_15_B01 0x62
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#define DSI_INIT_SEQ_DATA_15_B01 0x62
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/*! DSI packet defines */
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#define DSI_ESCAPE_CMD 0x87
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#define DSI_ACK_NO_ERR 0x84
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#define ACK_ERROR_RES 0x02
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#define GEN_LONG_RD_RES 0x1A
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#define DCS_LONG_RD_RES 0x1C
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#define GEN_1_BYTE_SHORT_RD_RES 0x11
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#define DCS_1_BYTE_SHORT_RD_RES 0x21
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#define GEN_2_BYTE_SHORT_RD_RES 0x12
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#define DCS_2_BYTE_SHORT_RD_RES 0x22
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/*! MIPI registers. */
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/*! MIPI registers. */
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#define MIPI_CAL_MIPI_CAL_CTRL (0x00 / 0x4)
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#define MIPI_CAL_MIPI_CAL_CTRL (0x00 / 0x4)
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#define MIPI_CAL_CIL_MIPI_CAL_STATUS (0x08 / 0x4)
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#define MIPI_CAL_CIL_MIPI_CAL_STATUS (0x08 / 0x4)
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@ -489,18 +513,136 @@
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#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x74 / 0x4)
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#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x74 / 0x4)
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/*! MIPI CMDs. */
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/*! MIPI CMDs. */
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#define MIPI_DSI_V_SYNC_START 0x01
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#define MIPI_DSI_COLOR_MODE_OFF 0x02
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#define MIPI_DSI_END_OF_TRANSMISSION 0x08
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#define MIPI_DSI_NULL_PACKET 0x09
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#define MIPI_DSI_V_SYNC_END 0x11
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#define MIPI_DSI_COLOR_MODE_ON 0x12
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#define MIPI_DSI_BLANKING_PACKET 0x19
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#define MIPI_DSI_H_SYNC_START 0x21
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#define MIPI_DSI_SHUTDOWN_PERIPHERAL 0x22
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#define MIPI_DSI_H_SYNC_END 0x31
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#define MIPI_DSI_TURN_ON_PERIPHERAL 0x32
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#define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37
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#define MIPI_DSI_DCS_SHORT_WRITE 0x05
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#define MIPI_DSI_DCS_SHORT_WRITE 0x05
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#define MIPI_DSI_DCS_READ 0x06
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#define MIPI_DSI_DCS_READ 0x06
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#define MIPI_DSI_DCS_SHORT_WRITE_PARAM 0x15
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#define MIPI_DSI_DCS_SHORT_WRITE_PARAM 0x15
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#define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37
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#define MIPI_DSI_DCS_LONG_WRITE 0x39
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#define MIPI_DSI_DCS_LONG_WRITE 0x39
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#define MIPI_DSI_GENERIC_LONG_WRITE 0x29
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#define MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM 0x03
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#define MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM 0x13
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#define MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM 0x23
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#define MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM 0x04
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#define MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM 0x14
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#define MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM 0x24
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/*! MIPI DCS CMDs. */
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/*! MIPI DCS CMDs. */
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#define MIPI_DCS_NOP 0x00
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#define MIPI_DCS_SOFT_RESET 0x01
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#define MIPI_DCS_GET_COMPRESSION_MODE 0x03
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#define MIPI_DCS_GET_DISPLAY_ID 0x04
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#define MIPI_DCS_GET_DISPLAY_ID 0x04
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#define MIPI_DCS_GET_DISPLAY_ID1 0xDA // GET_DISPLAY_ID Byte0, Module Manufacturer ID.
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#define MIPI_DCS_GET_DISPLAY_ID2 0xDB // GET_DISPLAY_ID Byte1, Module/Driver Version ID.
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#define MIPI_DCS_GET_DISPLAY_ID3 0xDC // GET_DISPLAY_ID Byte2, Module/Driver ID.
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#define MIPI_DCS_GET_NUM_ERRORS 0x05
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#define MIPI_DCS_GET_RED_CHANNEL 0x06
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#define MIPI_DCS_GET_GREEN_CHANNEL 0x07
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#define MIPI_DCS_GET_BLUE_CHANNEL 0x08
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#define MIPI_DCS_GET_DISPLAY_STATUS 0x09
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#define MIPI_DCS_GET_POWER_MODE 0x0A
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#define MIPI_DCS_GET_ADDRESS_MODE 0x0B
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#define MIPI_DCS_GET_PIXEL_FORMAT 0x0C
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#define MIPI_DCS_GET_DISPLAY_MODE 0x0D
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||||||
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#define MIPI_DCS_GET_SIGNAL_MODE 0x0E
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#define MIPI_DCS_GET_DIAGNOSTIC_RESULT 0x0F
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#define MIPI_DCS_ENTER_SLEEP_MODE 0x10
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#define MIPI_DCS_ENTER_SLEEP_MODE 0x10
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||||||
#define MIPI_DCS_EXIT_SLEEP_MODE 0x11
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#define MIPI_DCS_EXIT_SLEEP_MODE 0x11
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||||||
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#define MIPI_DCS_ENTER_PARTIAL_MODE 0x12
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#define MIPI_DCS_ENTER_NORMAL_MODE 0x13
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||||||
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#define MIPI_DCS_EXIT_INVERT_MODE 0x20
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|
#define MIPI_DCS_ENTER_INVERT_MODE 0x21
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||||||
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#define MIPI_DCS_ALL_PIXELS_OFF 0x22
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||||||
|
#define MIPI_DCS_ALL_PIXELS_ON 0x23
|
||||||
|
#define MIPI_DCS_SET_CONTRAST 0x25 // VCON in 40mV steps. 7-bit integer.
|
||||||
|
#define MIPI_DCS_SET_GAMMA_CURVE 0x26
|
||||||
#define MIPI_DCS_SET_DISPLAY_OFF 0x28
|
#define MIPI_DCS_SET_DISPLAY_OFF 0x28
|
||||||
#define MIPI_DCS_SET_DISPLAY_ON 0x29
|
#define MIPI_DCS_SET_DISPLAY_ON 0x29
|
||||||
|
#define MIPI_DCS_SET_COLUMN_ADDRESS 0x2A
|
||||||
|
#define MIPI_DCS_SET_PAGE_ADDRESS 0x2B
|
||||||
|
#define MIPI_DCS_WRITE_MEMORY_START 0x2C
|
||||||
|
#define MIPI_DCS_WRITE_LUT 0x2D // 24-bit: 192 bytes.
|
||||||
|
#define MIPI_DCS_READ_MEMORY_START 0x2E
|
||||||
|
#define MIPI_DCS_SET_PARTIAL_ROWS 0x30
|
||||||
|
#define MIPI_DCS_SET_PARTIAL_COLUMNS 0x31
|
||||||
|
#define MIPI_DCS_SET_SCROLL_AREA 0x33
|
||||||
|
#define MIPI_DCS_SET_TEAR_OFF 0x34
|
||||||
|
#define MIPI_DCS_SET_TEAR_ON 0x35
|
||||||
|
#define MIPI_DCS_SET_ADDRESS_MODE 0x36
|
||||||
|
#define MIPI_DCS_SET_SCROLL_START 0x37
|
||||||
|
#define MIPI_DCS_EXIT_IDLE_MODE 0x38
|
||||||
|
#define MIPI_DCS_ENTER_IDLE_MODE 0x39
|
||||||
|
#define MIPI_DCS_SET_PIXEL_FORMAT 0x3A
|
||||||
|
#define MIPI_DCS_WRITE_MEMORY_CONTINUE 0x3C
|
||||||
|
#define MIPI_DCS_READ_MEMORY_CONTINUE 0x3E
|
||||||
|
#define MIPI_DCS_GET_3D_CONTROL 0x3F
|
||||||
|
#define MIPI_DCS_SET_VSYNC_TIMING 0x40
|
||||||
|
#define MIPI_DCS_SET_TEAR_SCANLINE 0x44
|
||||||
|
#define MIPI_DCS_GET_SCANLINE 0x45
|
||||||
|
#define MIPI_DCS_SET_TEAR_SCANLINE_WIDTH 0x46
|
||||||
|
#define MIPI_DCS_GET_SCANLINE_WIDTH 0x47
|
||||||
|
#define MIPI_DCS_SET_BRIGHTNESS 0x51 // DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL.
|
||||||
|
#define MIPI_DCS_GET_BRIGHTNESS 0x52
|
||||||
|
#define MIPI_DCS_SET_CONTROL_DISPLAY 0x53
|
||||||
|
#define MIPI_DCS_GET_CONTROL_DISPLAY 0x54
|
||||||
|
#define MIPI_DCS_SET_CABC_VALUE 0x55
|
||||||
|
#define MIPI_DCS_GET_CABC_VALUE 0x56
|
||||||
|
#define MIPI_DCS_SET_CABC_MIN_BRI 0x5E
|
||||||
|
#define MIPI_DCS_GET_CABC_MIN_BRI 0x5F
|
||||||
|
#define MIPI_DCS_READ_DDB_START 0xA1
|
||||||
|
#define MIPI_DCS_READ_DDB_CONTINUE 0xA8
|
||||||
|
|
||||||
|
/*! MIPI DCS Panel Private CMDs. */
|
||||||
|
#define MIPI_DCS_PRIV_UNK_A0 0xA0
|
||||||
|
#define MIPI_DCS_PRIV_SET_POWER_CONTROL 0xB1
|
||||||
|
#define MIPI_DCS_PRIV_SET_EXTC 0xB9
|
||||||
|
#define MIPI_DCS_PRIV_UNK_BD 0xBD
|
||||||
|
#define MIPI_DCS_PRIV_UNK_D5 0xD5
|
||||||
|
#define MIPI_DCS_PRIV_UNK_D6 0xD6
|
||||||
|
#define MIPI_DCS_PRIV_UNK_D8 0xD8
|
||||||
|
#define MIPI_DCS_PRIV_UNK_D9 0xD9
|
||||||
|
|
||||||
|
/*! MIPI DCS CMD Defines. */
|
||||||
|
#define DCS_POWER_MODE_DISPLAY_ON BIT(2)
|
||||||
|
#define DCS_POWER_MODE_NORMAL_MODE BIT(3)
|
||||||
|
#define DCS_POWER_MODE_SLEEP_MODE BIT(4)
|
||||||
|
#define DCS_POWER_MODE_PARTIAL_MODE BIT(5)
|
||||||
|
#define DCS_POWER_MODE_IDLE_MODE BIT(6)
|
||||||
|
|
||||||
|
#define DCS_ADDRESS_MODE_V_FLIP BIT(0)
|
||||||
|
#define DCS_ADDRESS_MODE_H_FLIP BIT(1)
|
||||||
|
#define DCS_ADDRESS_MODE_LATCH_RL BIT(2) // Latch Data Order.
|
||||||
|
#define DCS_ADDRESS_MODE_BGR_COLOR BIT(3)
|
||||||
|
#define DCS_ADDRESS_MODE_LINE_ORDER BIT(4) // Line Refresh Order.
|
||||||
|
#define DCS_ADDRESS_MODE_SWAP_XY BIT(5) // Page/Column Addressing Reverse Order.
|
||||||
|
#define DCS_ADDRESS_MODE_MIRROR_X BIT(6) // Column Address Order.
|
||||||
|
#define DCS_ADDRESS_MODE_MIRROR_Y BIT(7) // Page Address Order.
|
||||||
|
#define DCS_ADDRESS_MODE_ROTATION_MASK (0xF << 4)
|
||||||
|
#define DCS_ADDRESS_MODE_ROTATION_90 (DCS_ADDRESS_MODE_SWAP_XY | DCS_ADDRESS_MODE_LINE_ORDER)
|
||||||
|
#define DCS_ADDRESS_MODE_ROTATION_180 (DCS_ADDRESS_MODE_MIRROR_X | DCS_ADDRESS_MODE_LINE_ORDER)
|
||||||
|
#define DCS_ADDRESS_MODE_ROTATION_270 (DCS_ADDRESS_MODE_SWAP_XY)
|
||||||
|
|
||||||
|
#define DCS_GAMMA_CURVE_NONE 0
|
||||||
|
#define DCS_GAMMA_CURVE_GC0_1_8 BIT(0)
|
||||||
|
#define DCS_GAMMA_CURVE_GC1_2_5 BIT(1)
|
||||||
|
#define DCS_GAMMA_CURVE_GC2_1_0 BIT(2)
|
||||||
|
#define DCS_GAMMA_CURVE_GC3_1_0 BIT(3) // Are there more?
|
||||||
|
|
||||||
|
#define DCS_CONTROL_DISPLAY_BACKLIGHT_CTRL BIT(2)
|
||||||
|
#define DCS_CONTROL_DISPLAY_DIMMING_CTRL BIT(3)
|
||||||
|
#define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL BIT(5)
|
||||||
|
|
||||||
/* Switch Panels:
|
/* Switch Panels:
|
||||||
*
|
*
|
||||||
|
@ -572,4 +714,7 @@ void display_init_cursor(void *crs_fb, u32 size);
|
||||||
void display_set_pos_cursor(u32 x, u32 y);
|
void display_set_pos_cursor(u32 x, u32 y);
|
||||||
void display_deinit_cursor();
|
void display_deinit_cursor();
|
||||||
|
|
||||||
|
void display_dsi_write(u8 cmd, u32 len, void *data, bool video_enabled);
|
||||||
|
int display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in a new issue