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bdk: hwinit: save boot reason for later usage

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CTCaer 2021-10-01 14:32:42 +03:00
parent 99d15eaac8
commit a1910156d8
4 changed files with 28 additions and 10 deletions
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25
bdk/soc/hw_init.c
View file

@ -48,14 +48,8 @@
extern boot_cfg_t b_cfg; extern boot_cfg_t b_cfg;
extern volatile nyx_storage_t *nyx_str; extern volatile nyx_storage_t *nyx_str;
/* u32 hw_rst_status;
* CLK_OSC - 38.4 MHz crystal. u32 hw_rst_reason;
* CLK_M - 19.2 MHz (osc/2).
* CLK_S - 32.768 KHz (from PMIC).
* SCLK - 204MHz init (-> 408MHz -> OC).
* HCLK - 204MHz init (-> 408MHz -> OC).
* PCLK - 68MHz init (-> 136MHz -> OC/4).
*/
u32 hw_get_chip_id() u32 hw_get_chip_id()
{ {
@ -65,6 +59,15 @@ u32 hw_get_chip_id()
return GP_HIDREV_MAJOR_T210; return GP_HIDREV_MAJOR_T210;
} }
/*
* CLK_OSC - 38.4 MHz crystal.
* CLK_M - 19.2 MHz (osc/2).
* CLK_S - 32.768 KHz (from PMIC).
* SCLK - 204MHz init (-> 408MHz -> OC).
* HCLK - 204MHz init (-> 408MHz -> OC).
* PCLK - 68MHz init (-> 136MHz -> OC/4).
*/
static void _config_oscillators() static void _config_oscillators()
{ {
CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2. CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2.
@ -264,7 +267,11 @@ static void _config_se_brom()
PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE; PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE;
SE(SE_INT_STATUS_REG) = 0x1F; // Clear all SE interrupts. SE(SE_INT_STATUS_REG) = 0x1F; // Clear all SE interrupts.
// Clear the boot reason to avoid problems later // Save reset reason.
hw_rst_status = PMC(APBDEV_PMC_SCRATCH200);
hw_rst_reason = PMC(APBDEV_PMC_RST_STATUS) & PMC_RST_STATUS_MASK;
// Clear the boot reason to avoid problems later.
PMC(APBDEV_PMC_SCRATCH200) = 0x0; PMC(APBDEV_PMC_SCRATCH200) = 0x0;
PMC(APBDEV_PMC_RST_STATUS) = 0x0; PMC(APBDEV_PMC_RST_STATUS) = 0x0;
APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10); APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);

5
bdk/soc/hw_init.h
View file

@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2018 naehrwert * Copyright (c) 2018 naehrwert
* Copyright (c) 2018 CTCaer * Copyright (c) 2018-2021 CTCaer
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@ -23,6 +23,9 @@
#define BL_MAGIC_CRBOOT_SLD 0x30444C53 // SLD0, seamless display type 0. #define BL_MAGIC_CRBOOT_SLD 0x30444C53 // SLD0, seamless display type 0.
#define BL_MAGIC_BROKEN_HWI 0xBAADF00D // Broken hwinit. #define BL_MAGIC_BROKEN_HWI 0xBAADF00D // Broken hwinit.
extern u32 hw_rst_status;
extern u32 hw_rst_reason;
void hw_init(); void hw_init();
void hw_reinit_workaround(bool coreboot, u32 magic); void hw_reinit_workaround(bool coreboot, u32 magic);
u32 hw_get_chip_id(); u32 hw_get_chip_id();

7
bdk/soc/pmc.h
View file

@ -60,6 +60,13 @@
#define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8 #define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8
#define PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2) #define PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2)
#define APBDEV_PMC_RST_STATUS 0x1B4 #define APBDEV_PMC_RST_STATUS 0x1B4
#define PMC_RST_STATUS_MASK 0x7
#define PMC_RST_STATUS_POR 0
#define PMC_RST_STATUS_WATCHDOG 1
#define PMC_RST_STATUS_SENSOR 2
#define PMC_RST_STATUS_SW_MAIN 3
#define PMC_RST_STATUS_LP0 4
#define PMC_RST_STATUS_AOTAG 5
#define APBDEV_PMC_IO_DPD_REQ 0x1B8 #define APBDEV_PMC_IO_DPD_REQ 0x1B8
#define PMC_IO_DPD_REQ_DPD_OFF BIT(30) #define PMC_IO_DPD_REQ_DPD_OFF BIT(30)
#define APBDEV_PMC_IO_DPD2_REQ 0x1C0 #define APBDEV_PMC_IO_DPD2_REQ 0x1C0

1
bdk/utils/util.h
View file

@ -46,6 +46,7 @@ typedef enum
ERR_SYSOLD_NYX = BIT(1), ERR_SYSOLD_NYX = BIT(1),
ERR_LIBSYS_MTC = BIT(2), ERR_LIBSYS_MTC = BIT(2),
ERR_SD_BOOT_EN = BIT(3), ERR_SD_BOOT_EN = BIT(3),
ERR_PANIC_CODE = BIT(4),
ERR_L4T_KERNEL = BIT(24), ERR_L4T_KERNEL = BIT(24),
ERR_EXCEPTION = BIT(31), ERR_EXCEPTION = BIT(31),
} hekate_errors_t; } hekate_errors_t;