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max7762x: Update registers for all pmic types
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CTCaer
parent
adf2045896
commit
9fbb28e887
3 changed files with 213 additions and 147 deletions
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@ -1,8 +1,7 @@
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/*
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* Defining registers address and its bit definitions of MAX77620 and MAX20024
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*
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* Copyright (c) 2016 NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019 CTCaer
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* Copyright (c) 2019-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -30,24 +29,33 @@
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#define MAX77620_CNFGGLBL1_LBHYST_200 (1 << 4)
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#define MAX77620_CNFGGLBL1_LBHYST_300 (2 << 4)
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#define MAX77620_CNFGGLBL1_LBHYST_400 (3 << 4)
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#define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4))
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#define MAX77620_CNFGGLBL1_MPPLD BIT(6)
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#define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
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#define MAX77620_REG_CNFGGLBL2 0x01
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#define MAX77620_REG_CNFGGLBL3 0x02
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#define MAX77620_WDTC_MASK 0x3
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#define MAX77620_WDTEN BIT(2)
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#define MAX77620_WDTSLPC BIT(3)
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#define MAX77620_WDTOFFC BIT(4)
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#define MAX77620_TWD_MASK 0x3
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#define MAX77620_TWD_2s 0x0
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#define MAX77620_TWD_16s 0x1
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#define MAX77620_TWD_64s 0x2
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#define MAX77620_TWD_128s 0x3
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#define MAX77620_WDTEN BIT(2)
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#define MAX77620_WDTSLPC BIT(3)
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#define MAX77620_WDTOFFC BIT(4)
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#define MAX77620_GLBL_LPM BIT(5)
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#define MAX77620_I2CTWD_MASK 0xC0
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#define MAX77620_I2CTWD_DISABLED 0x00
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#define MAX77620_I2CTWD_1_33ms 0x40
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#define MAX77620_I2CTWD_35_7ms 0x80
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#define MAX77620_I2CTWD_41_7ms 0xC0
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#define MAX77620_REG_CNFGGLBL3 0x02
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#define MAX77620_WDTC_MASK 0x3
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#define MAX77620_REG_CNFG1_32K 0x03
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#define MAX77620_CNFG1_PWR_MD_32K_MASK 0x3
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#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
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#define MAX77620_CNFG1_32KLOAD_MASK 0x30
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#define MAX77620_CNFG1_32K_OK BIT(7)
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#define MAX77620_REG_CNFGBBC 0x04
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#define MAX77620_CNFGBBC_ENABLE BIT(0)
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@ -64,6 +72,7 @@
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#define MAX77620_CNFGBBC_RESISTOR_6K (3 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
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#define MAX77620_REG_IRQTOP 0x05
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#define MAX77620_REG_IRQTOPM 0x0D
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#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
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#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
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#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
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@ -73,28 +82,53 @@
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#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
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#define MAX77620_REG_INTLBT 0x06
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#define MAX77620_REG_IRQTOPM 0x0D
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#define MAX77620_REG_INTENLBT 0x0E
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#define MAX77620_IRQ_GLBLM_MASK BIT(0)
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#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
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#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
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#define MAX77620_IRQ_LBM_MASK BIT(3)
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#define MAX77620_REG_IRQSD 0x07
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#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
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#define MAX77620_REG_IRQ_LVL2_L8 0x09
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#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
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#define MAX77620_REG_ONOFFIRQ 0x0B
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#define MAX77620_REG_NVERC 0x0C
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#define MAX77620_REG_INTENLBT 0x0E
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#define MAX77620_GLBLM_MASK BIT(0)
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#define MAX77620_REG_IRQMASKSD 0x0F
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#define MAX77620_IRQSD_PFI_SD3 BIT(4)
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#define MAX77620_IRQSD_PFI_SD2 BIT(5)
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#define MAX77620_IRQSD_PFI_SD1 BIT(6)
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#define MAX77620_IRQSD_PFI_SD0 BIT(7)
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#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 // LDO number that irq occured.
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#define MAX77620_REG_IRQ_MSK_L0_7 0x10
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#define MAX77620_REG_IRQ_LVL2_L8 0x09 // LDO number that irq occured. Only bit0: LDO8 is valid.
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#define MAX77620_REG_IRQ_MSK_L8 0x11
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#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A // Edge detection interrupt.
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#define MAX77620_REG_ONOFFIRQ 0x0B
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#define MAX77620_REG_ONOFFIRQM 0x12
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#define MAX77620_ONOFFIRQ_MRWRN BIT(0)
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#define MAX77620_ONOFFIRQ_EN0_1SEC BIT(1)
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#define MAX77620_ONOFFIRQ_EN0_F BIT(2)
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#define MAX77620_ONOFFIRQ_EN0_R BIT(3)
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#define MAX77620_ONOFFIRQ_LID_F BIT(4)
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#define MAX77620_ONOFFIRQ_LID_R BIT(5)
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#define MAX77620_ONOFFIRQ_ACOK_F BIT(6)
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#define MAX77620_ONOFFIRQ_ACOK_R BIT(7)
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#define MAX77620_REG_NVERC 0x0C // Shutdown reason (non-volatile).
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#define MAX77620_NVERC_SHDN BIT(0)
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#define MAX77620_NVERC_WTCHDG BIT(1)
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#define MAX77620_NVERC_HDRST BIT(2)
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#define MAX77620_NVERC_TOVLD BIT(3)
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#define MAX77620_NVERC_MBLSD BIT(4)
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#define MAX77620_NVERC_MBO BIT(5)
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#define MAX77620_NVERC_MBU BIT(6)
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#define MAX77620_NVERC_RSTIN BIT(7)
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#define MAX77620_REG_STATLBT 0x13
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#define MAX77620_REG_STATSD 0x14
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#define MAX77620_REG_ONOFFSTAT 0x15
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#define MAX77620_ONOFFSTAT_LID BIT(0)
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#define MAX77620_ONOFFSTAT_ACOK BIT(1)
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#define MAX77620_ONOFFSTAT_EN0 BIT(2)
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/* SD and LDO Registers */
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#define MAX77620_REG_SD0 0x16
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@ -102,18 +136,42 @@
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#define MAX77620_REG_SD2 0x18
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#define MAX77620_REG_SD3 0x19
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#define MAX77620_REG_SD4 0x1A
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#define MAX77620_REG_DVSSD0 0x1B
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#define MAX77620_REG_DVSSD1 0x1C
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#define MAX77620_SDX_VOLT_MASK 0xFF
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#define MAX77620_SD0_VOLT_MASK 0x3F
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#define MAX77620_SD1_VOLT_MASK 0x7F
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#define MAX77620_LDO_VOLT_MASK 0x3F
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#define MAX77620_REG_DVSSD0 0x1B
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#define MAX77620_REG_DVSSD1 0x1C
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#define MAX77620_REG_SD0_CFG 0x1D // SD CNFG1.
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#define MAX77620_REG_SD1_CFG 0x1E // SD CNFG1.
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#define MAX77620_REG_SD2_CFG 0x1F // SD CNFG1.
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#define MAX77620_REG_SD3_CFG 0x20 // SD CNFG1.
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#define MAX77620_REG_SD4_CFG 0x21 // SD CNFG1.
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#define MAX77620_REG_SD0_CFG 0x1D
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#define MAX77620_REG_SD1_CFG 0x1E
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#define MAX77620_REG_SD2_CFG 0x1F
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#define MAX77620_REG_SD3_CFG 0x20
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#define MAX77620_REG_SD4_CFG 0x21
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#define MAX77620_SD_SR_MASK 0xC0
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#define MAX77620_SD_SR_SHIFT 6
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#define MAX77620_SD_POWER_MODE_MASK 0x30
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#define MAX77620_SD_POWER_MODE_SHIFT 4
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#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
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#define MAX77620_SD_CFG1_ADE_DISABLE 0
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#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
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#define MAX77620_SD_FPWM_MASK 0x04
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#define MAX77620_SD_FPWM_SHIFT 2
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#define MAX77620_SD_FSRADE_MASK 0x01
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#define MAX77620_SD_FSRADE_SHIFT 0
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#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
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#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
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#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
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#define MAX77620_SD_CFG1_MPOK_MASK BIT(1)
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#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
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#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
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#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
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#define MAX77620_REG_SD_CFG2 0x22
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#define MAX77620_SD_CNF2_RSVD BIT(0)
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#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
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#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
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#define MAX77620_REG_LDO0_CFG 0x23
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#define MAX77620_REG_LDO0_CFG2 0x24
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#define MAX77620_REG_LDO1_CFG 0x25
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@ -132,26 +190,36 @@
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#define MAX77620_REG_LDO7_CFG2 0x32
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#define MAX77620_REG_LDO8_CFG 0x33
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#define MAX77620_REG_LDO8_CFG2 0x34
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#define MAX77620_LDO_CFG2_SS_MASK (1 << 0)
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#define MAX77620_LDO_CFG2_SS_FAST (1 << 0)
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#define MAX77620_LDO_CFG2_SS_SLOW 0
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#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1)
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#define MAX77620_LDO_CFG2_ADE_DISABLE (0 << 1)
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#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1)
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#define MAX20024_LDO_CFG2_MPOK_MASK BIT(2)
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#define MAX77620_LDO_POWER_MODE_MASK 0xC0
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/*! LDO CFG */
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#define MAX77620_LDO_POWER_MODE_SHIFT 6
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#define MAX77620_LDO_POWER_MODE_MASK (3 << MAX77620_LDO_POWER_MODE_SHIFT)
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#define MAX77620_POWER_MODE_NORMAL 3
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#define MAX77620_POWER_MODE_LPM 2
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#define MAX77620_POWER_MODE_GLPM 1
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#define MAX77620_POWER_MODE_DISABLE 0
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/*! LDO CFG2 */
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#define MAX77620_LDO_CFG2_SS_MASK (1 << 0)
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#define MAX77620_LDO_CFG2_SS_FAST (0 << 0)
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#define MAX77620_LDO_CFG2_SS_SLOW (1 << 0)
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#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1)
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#define MAX77620_LDO_CFG2_ADE_DISABLE (0 << 1)
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#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1)
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#define MAX77620_LDO_CFG2_MPOK_MASK BIT(2)
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#define MAX77620_LDO_CFG2_POK_MASK BIT(3)
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#define MAX77620_LDO_CFG2_COMP_SHIFT 4
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#define MAX77620_LDO_CFG2_COMP_MASK (3 << MAX77620_LDO_COMP_SHIFT)
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#define MAX77620_LDO_CFG2_COMP_SLOW 3
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#define MAX77620_LDO_CFG2_COMP_MID_SLOW 2
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#define MAX77620_LDO_CFG2_COMP_MID_FAST 1
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#define MAX77620_LDO_CFG2_COMP_FAST 0
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#define MAX77620_LDO_CFG2_ALPM_EN_MASK BIT(6)
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#define MAX77620_LDO_CFG2_OVCLMP_MASK BIT(7)
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#define MAX77620_REG_LDO_CFG3 0x35
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#define MAX77620_LDO_BIAS_EN BIT(0)
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#define MAX77620_TRACK4_SHIFT 5
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#define MAX77620_TRACK4_MASK (1 << MAX77620_TRACK4_SHIFT)
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#define MAX77620_LDO_SLEW_RATE_MASK 0x1
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#define MAX77620_REG_GPIO0 0x36
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#define MAX77620_REG_GPIO1 0x37
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#define MAX77620_REG_GPIO2 0x38
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@ -160,9 +228,6 @@
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#define MAX77620_REG_GPIO5 0x3B
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#define MAX77620_REG_GPIO6 0x3C
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#define MAX77620_REG_GPIO7 0x3D
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#define MAX77620_REG_PUE_GPIO 0x3E
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#define MAX77620_REG_PDE_GPIO 0x3F
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#define MAX77620_REG_AME_GPIO 0x40
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#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0)
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#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0)
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#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN (0 << 0)
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#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
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#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
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#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
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#define MAX77620_GPIO_OUTPUT_DISABLE 0
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#define MAX77620_GPIO_OUTPUT_ENABLE 1
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#define MAX77620_REG_PUE_GPIO 0x3E // Gpio Pullup resistor enable.
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#define MAX77620_REG_PDE_GPIO 0x3F // Gpio Pulldown resistor enable.
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#define MAX77620_REG_AME_GPIO 0x40 // Gpio pinmuxing. Clear bits are Standard GPIO.
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#define MAX77620_REG_ONOFFCNFG1 0x41
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#define MAX20024_ONOFFCNFG1_CLRSE 0x18
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#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
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#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
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#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
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#define MAX77620_ONOFFCNFG1_RSVD BIT(6)
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#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
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#define MAX77620_REG_ONOFFCNFG2 0x42
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#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
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#define MAX77620_ONOFFCNFG2_WK_ALARM2 BIT(1)
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#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
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#define MAX77620_ONOFFCNFG2_WK_MBATT BIT(3) // MBATT event generates a wakeup signal. use it in android/l4t?
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#define MAX77620_ONOFFCNFG2_WK_ACOK BIT(4)
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#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
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#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
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#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
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/* FPS Registers */
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#define MAX77620_REG_FPS_CFG0 0x43
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#define MAX77620_REG_FPS_CFG1 0x44
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#define MAX77620_REG_FPS_CFG2 0x45
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#define MAX77620_REG_FPS_CFG0 0x43 // FPS0.
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#define MAX77620_REG_FPS_CFG1 0x44 // FPS1.
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#define MAX77620_REG_FPS_CFG2 0x45 // FPS2.
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#define MAX77620_FPS_ENFPS_SW_MASK 0x01
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#define MAX77620_FPS_ENFPS_SW 0x01
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#define MAX77620_FPS_EN_SRC_SHIFT 1
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#define MAX77620_FPS_EN_SRC_MASK 0x06
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#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
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#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
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#define MAX77620_REG_FPS_LDO0 0x46
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#define MAX77620_REG_FPS_LDO1 0x47
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#define MAX77620_REG_FPS_LDO2 0x48
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#define MAX77620_REG_FPS_SD2 0x51
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#define MAX77620_REG_FPS_SD3 0x52
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#define MAX77620_REG_FPS_SD4 0x53
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#define MAX77620_REG_FPS_NONE 0
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#define MAX77620_FPS_SRC_MASK 0xC0
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#define MAX77620_FPS_SRC_SHIFT 6
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#define MAX77620_FPS_PU_PERIOD_MASK 0x38
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#define MAX77620_FPS_PU_PERIOD_SHIFT 3
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#define MAX77620_FPS_PD_PERIOD_MASK 0x07
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#define MAX77620_FPS_PD_PERIOD_SHIFT 0
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/* Minimum and maximum FPS period time (in microseconds) are
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* different for MAX77620 and Max20024.
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*/
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#define MAX77620_FPS_COUNT 3
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#define MAX77620_FPS_PERIOD_MIN_US 40
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#define MAX20024_FPS_PERIOD_MIN_US 20
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#define MAX77620_FPS_PERIOD_MAX_US 2560
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#define MAX20024_FPS_PERIOD_MAX_US 5120
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#define MAX77620_REG_FPS_GPIO1 0x54
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#define MAX77620_REG_FPS_GPIO2 0x55
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#define MAX77620_REG_FPS_GPIO3 0x56
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#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
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#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
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#define MAX77620_FPS_EN_SRC_MASK 0x06
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#define MAX77620_FPS_EN_SRC_SHIFT 1
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#define MAX77620_FPS_ENFPS_SW_MASK 0x01
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#define MAX77620_FPS_ENFPS_SW 0x01
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#define MAX77620_REG_FPS_RSO 0x57
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#define MAX77620_FPS_PD_PERIOD_SHIFT 0
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#define MAX77620_FPS_PD_PERIOD_MASK 0x07
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#define MAX77620_FPS_PU_PERIOD_SHIFT 3
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#define MAX77620_FPS_PU_PERIOD_MASK 0x38
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#define MAX77620_FPS_SRC_SHIFT 6
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#define MAX77620_FPS_SRC_MASK 0xC0
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#define MAX77620_FPS_COUNT 3
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#define MAX77620_FPS_PERIOD_MIN_US 40
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#define MAX77620_FPS_PERIOD_MAX_US 2560
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#define MAX77620_REG_CID0 0x58
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#define MAX77620_REG_CID1 0x59
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#define MAX77620_REG_CID2 0x5A
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#define MAX77620_REG_CID3 0x5B
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#define MAX77620_REG_CID4 0x5C
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#define MAX77620_REG_CID4 0x5C // OTP version.
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#define MAX77620_REG_CID5 0x5D
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#define MAX77620_REG_DVSSD4 0x5E
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#define MAX20024_REG_MAX_ADD 0x70
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#define MAX77620_CID_DIDO_MASK 0xF
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#define MAX77620_CID_DIDO_SHIFT 0
|
||||
#define MAX77620_CID_DIDM_MASK 0xF0
|
||||
#define MAX77620_CID_DIDM_SHIFT 4
|
||||
|
||||
/* CNCG2SD */
|
||||
#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
|
||||
#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
|
||||
|
||||
/* Device Identification Metal */
|
||||
#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
|
||||
/* Device Indentification OTP */
|
||||
#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
|
||||
|
||||
/* SD CNFG1 */
|
||||
#define MAX77620_SD_SR_MASK 0xC0
|
||||
#define MAX77620_SD_SR_SHIFT 6
|
||||
#define MAX77620_SD_POWER_MODE_MASK 0x30
|
||||
#define MAX77620_SD_POWER_MODE_SHIFT 4
|
||||
#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
|
||||
#define MAX77620_SD_CFG1_ADE_DISABLE 0
|
||||
#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
|
||||
#define MAX77620_SD_FPWM_MASK 0x04
|
||||
#define MAX77620_SD_FPWM_SHIFT 2
|
||||
#define MAX77620_SD_FSRADE_MASK 0x01
|
||||
#define MAX77620_SD_FSRADE_SHIFT 0
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
|
||||
#define MAX20024_SD_CFG1_MPOK_MASK BIT(1)
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
|
||||
#define MAX77620_REG_DVSSD4 0x5E
|
||||
#define MAX20024_REG_MAX_ADD 0x70
|
||||
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
|
||||
|
|
@ -332,9 +377,4 @@ enum max77620_fps_src {
|
|||
MAX77620_FPS_SRC_DEF,
|
||||
};
|
||||
|
||||
enum max77620_chip_id {
|
||||
MAX77620,
|
||||
MAX20024,
|
||||
};
|
||||
|
||||
#endif /* _MFD_MAX77620_H_ */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2019 CTCaer
|
||||
* Copyright (c) 2019-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
|
@ -63,21 +63,30 @@
|
|||
#define MAX77621_CPU_I2C_ADDR 0x1B
|
||||
#define MAX77621_GPU_I2C_ADDR 0x1C
|
||||
|
||||
#define MAX77621_VOUT_REG 0
|
||||
#define MAX77621_VOUT_DVS_REG 1
|
||||
#define MAX77621_CONTROL1_REG 2
|
||||
#define MAX77621_CONTROL2_REG 3
|
||||
|
||||
/* MAX77621_VOUT */
|
||||
#define MAX77621_VOUT_ENABLE BIT(7)
|
||||
#define MAX77621_VOUT_MASK 0x7F
|
||||
#define MAX77621_VOUT_0_95V 0x37
|
||||
#define MAX77621_VOUT_1_09V 0x4F
|
||||
#define MAX77621_VOUT_REG 0x00
|
||||
#define MAX77621_VOUT_DVS_REG 0x01
|
||||
#define MAX77621_CONTROL1_REG 0x02
|
||||
#define MAX77621_CONTROL2_REG 0x03
|
||||
#define MAX77621_CHIPID1_REG 0x04
|
||||
#define MAX77621_CHIPID2_REG 0x05
|
||||
|
||||
/* MAX77621_VOUT_DVC_DVS */
|
||||
#define MAX77621_DVS_VOUT_MASK 0x7F
|
||||
#define MAX77621_DVC_DVS_VOLT_MASK 0x7F
|
||||
#define MAX77621_DVC_DVS_ENABLE_SHIFT 7
|
||||
#define MAX77621_DVC_DVS_ENABLE_MASK (1 << MAX77621_DVC_DVS_ENABLE_SHIFT)
|
||||
|
||||
/* MAX77621_VOUT */
|
||||
#define MAX77621_VOUT_DISABLE 0
|
||||
#define MAX77621_VOUT_ENABLE 1
|
||||
#define MAX77621_VOUT_ENABLE_MASK (MAX77621_VOUT_ENABLE << MAX77621_DVC_DVS_ENABLE_SHIFT)
|
||||
|
||||
/* MAX77621_CONTROL1 */
|
||||
#define MAX77621_RAMP_12mV_PER_US 0x0
|
||||
#define MAX77621_RAMP_25mV_PER_US 0x1
|
||||
#define MAX77621_RAMP_50mV_PER_US 0x2
|
||||
#define MAX77621_RAMP_200mV_PER_US 0x3
|
||||
#define MAX77621_RAMP_MASK 0x3
|
||||
|
||||
#define MAX77621_FREQSHIFT_9PER BIT(2)
|
||||
#define MAX77621_BIAS_ENABLE BIT(3)
|
||||
#define MAX77621_AD_ENABLE BIT(4)
|
||||
|
|
@ -85,27 +94,41 @@
|
|||
#define MAX77621_FPWM_EN_M BIT(6)
|
||||
#define MAX77621_SNS_ENABLE BIT(7)
|
||||
|
||||
#define MAX77621_RAMP_12mV_PER_US 0x0
|
||||
#define MAX77621_RAMP_25mV_PER_US 0x1
|
||||
#define MAX77621_RAMP_50mV_PER_US 0x2
|
||||
#define MAX77621_RAMP_200mV_PER_US 0x3
|
||||
#define MAX77621_RAMP_MASK 0x3
|
||||
|
||||
/* MAX77621_CONTROL2 */
|
||||
#define MAX77621_INDUCTOR_MIN_30_PER 0
|
||||
#define MAX77621_INDUCTOR_NOMINAL 1
|
||||
#define MAX77621_INDUCTOR_PLUS_30_PER 2
|
||||
#define MAX77621_INDUCTOR_PLUS_60_PER 3
|
||||
#define MAX77621_INDUCTOR_MASK 3
|
||||
|
||||
#define MAX77621_CKKADV_TRIP_75mV_PER_US 0x0
|
||||
#define MAX77621_CKKADV_TRIP_150mV_PER_US BIT(2)
|
||||
#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS BIT(3)
|
||||
#define MAX77621_CKKADV_TRIP_DISABLE (BIT(2) | BIT(3))
|
||||
#define MAX77621_CKKADV_TRIP_MASK (BIT(2) | BIT(3))
|
||||
|
||||
#define MAX77621_FT_ENABLE BIT(4)
|
||||
#define MAX77621_DISCH_ENBABLE BIT(5)
|
||||
#define MAX77621_DISCH_ENABLE BIT(5)
|
||||
#define MAX77621_WDTMR_ENABLE BIT(6)
|
||||
#define MAX77621_T_JUNCTION_120 BIT(7)
|
||||
|
||||
#define MAX77621_CKKADV_TRIP_DISABLE 0xC
|
||||
#define MAX77621_CKKADV_TRIP_75mV_PER_US 0x0
|
||||
#define MAX77621_CKKADV_TRIP_150mV_PER_US 0x4
|
||||
#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS 0x8
|
||||
#define MAX77621_CPU_CTRL1_POR_DEFAULT (MAX77621_RAMP_50mV_PER_US)
|
||||
#define MAX77621_CPU_CTRL1_HOS_DEFAULT (MAX77621_AD_ENABLE | \
|
||||
MAX77621_NFSR_ENABLE | \
|
||||
MAX77621_SNS_ENABLE | \
|
||||
MAX77621_RAMP_12mV_PER_US)
|
||||
#define MAX77621_CPU_CTRL2_POR_DEFAULT (MAX77621_T_JUNCTION_120 | \
|
||||
MAX77621_FT_ENABLE | \
|
||||
MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS | \
|
||||
MAX77621_CKKADV_TRIP_150mV_PER_US | \
|
||||
MAX77621_INDUCTOR_NOMINAL)
|
||||
#define MAX77621_CPU_CTRL2_HOS_DEFAULT (MAX77621_T_JUNCTION_120 | \
|
||||
MAX77621_WDTMR_ENABLE | \
|
||||
MAX77621_CKKADV_TRIP_75mV_PER_US | \
|
||||
MAX77621_INDUCTOR_NOMINAL)
|
||||
|
||||
#define MAX77621_INDUCTOR_MIN_30_PER 0x0
|
||||
#define MAX77621_INDUCTOR_NOMINAL 0x1
|
||||
#define MAX77621_INDUCTOR_PLUS_30_PER 0x2
|
||||
#define MAX77621_INDUCTOR_PLUS_60_PER 0x3
|
||||
#define MAX77621_CTRL_HOS_CFG 0
|
||||
#define MAX77621_CTRL_POR_CFG 1
|
||||
|
||||
int max77620_regulator_get_status(u32 id);
|
||||
int max77620_regulator_config_fps(u32 id);
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@
|
|||
#ifndef _MAX77812_H_
|
||||
#define _MAX77812_H_
|
||||
|
||||
#define MAX77812_PHASE31_CPU_I2C_ADDR 0x31
|
||||
#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33
|
||||
#define MAX77812_PHASE31_CPU_I2C_ADDR 0x31 // 2 Outputs: 3-phase M1 + 1-phase M4.
|
||||
#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
|
||||
|
||||
#define MAX77812_REG_RSET 0x00
|
||||
#define MAX77812_REG_INT_SRC 0x01
|
||||
|
|
@ -27,7 +27,15 @@
|
|||
#define MAX77812_REG_TOPSYS_INT_M 0x04
|
||||
#define MAX77812_REG_TOPSYS_STAT 0x05
|
||||
#define MAX77812_REG_EN_CTRL 0x06
|
||||
#define MAX77812_EN_CTRL_EN_M4 BIT(6)
|
||||
#define MAX77812_EN_CTRL_ENABLE 1
|
||||
#define MAX77812_EN_CTRL_EN_M1_SHIFT 0
|
||||
#define MAX77812_EN_CTRL_EN_M1_MASK (1 << MAX77812_EN_CTRL_EN_M1_SHIFT)
|
||||
#define MAX77812_EN_CTRL_EN_M2_SHIFT 2
|
||||
#define MAX77812_EN_CTRL_EN_M2_MASK (1 << MAX77812_EN_CTRL_EN_M2_SHIFT)
|
||||
#define MAX77812_EN_CTRL_EN_M3_SHIFT 4
|
||||
#define MAX77812_EN_CTRL_EN_M3_MASK (1 << MAX77812_EN_CTRL_EN_M3_SHIFT)
|
||||
#define MAX77812_EN_CTRL_EN_M4_SHIFT 6
|
||||
#define MAX77812_EN_CTRL_EN_M4_MASK (1 << MAX77812_EN_CTRL_EN_M4_SHIFT)
|
||||
#define MAX77812_REG_STUP_DLY2 0x07
|
||||
#define MAX77812_REG_STUP_DLY3 0x08
|
||||
#define MAX77812_REG_STUP_DLY4 0x09
|
||||
|
|
@ -46,11 +54,10 @@
|
|||
#define MAX77812_REG_BUCK_INT 0x20
|
||||
#define MAX77812_REG_BUCK_INT_M 0x21
|
||||
#define MAX77812_REG_BUCK_STAT 0x22
|
||||
#define MAX77812_REG_M1_VOUT 0x23
|
||||
#define MAX77812_REG_M1_VOUT 0x23 // GPU.
|
||||
#define MAX77812_REG_M2_VOUT 0x24
|
||||
#define MAX77812_REG_M3_VOUT 0x25
|
||||
#define MAX77812_REG_M4_VOUT 0x26
|
||||
#define MAX77812_M4_VOUT_0_80V 0x6E
|
||||
#define MAX77812_REG_M3_VOUT 0x25 // DRAM on PHASE211.
|
||||
#define MAX77812_REG_M4_VOUT 0x26 // CPU.
|
||||
#define MAX77812_REG_M1_VOUT_D 0x27
|
||||
#define MAX77812_REG_M2_VOUT_D 0x28
|
||||
#define MAX77812_REG_M3_VOUT_D 0x29
|
||||
|
|
@ -91,10 +98,6 @@
|
|||
#define MAX77812_ES2_VERSION 0x04
|
||||
#define MAX77812_QS_VERSION 0x05
|
||||
|
||||
#define MAX77812_VOUT_MASK 0xFF
|
||||
#define MAX77812_VOUT_N_VOLTAGE 0xFF
|
||||
#define MAX77812_VOUT_VMIN 250000
|
||||
#define MAX77812_VOUT_VMAX 1525000
|
||||
#define MAX77812_VOUT_STEP 5000
|
||||
#define MAX77812_BUCK_VOLT_MASK 0xFF
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue