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https://github.com/CTCaer/hekate
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bdk: hwinit: move LDO8 init in regulators init
And also reorder it above I2C1 init (because of HOAG).
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1 changed files with 10 additions and 10 deletions
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@ -286,7 +286,7 @@ static void _config_se_brom()
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APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
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APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
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}
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}
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static void _config_regulators(bool tegra_t210)
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static void _config_regulators(bool tegra_t210, bool nx_hoag)
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{
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{
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// Set RTC/AO domain to POR voltage.
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// Set RTC/AO domain to POR voltage.
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if (tegra_t210)
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if (tegra_t210)
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@ -345,6 +345,13 @@ static void _config_regulators(bool tegra_t210)
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD2_CFG, (1 << MAX77620_SD_SR_SHIFT) |
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD2_CFG, (1 << MAX77620_SD_SR_SHIFT) |
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(MAX77620_POWER_MODE_NORMAL << MAX77620_SD_POWER_MODE_SHIFT) |
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(MAX77620_POWER_MODE_NORMAL << MAX77620_SD_POWER_MODE_SHIFT) |
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MAX77620_SD_CFG1_FSRADE_SD_ENABLE);
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MAX77620_SD_CFG1_FSRADE_SD_ENABLE);
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// Enable LDO8 on HOAG as it also powers I2C1 IO pads.
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if (nx_hoag)
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{
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max7762x_regulator_set_voltage(REGULATOR_LDO8, 2800000);
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max7762x_regulator_enable(REGULATOR_LDO8, true);
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}
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}
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}
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}
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}
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@ -397,19 +404,12 @@ void hw_init()
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// Initialize I2C5, mandatory for PMIC.
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// Initialize I2C5, mandatory for PMIC.
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i2c_init(I2C_5);
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i2c_init(I2C_5);
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// Enable LDO8 on HOAG as it also powers I2C1 IO pads.
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// Initialize various regulators based on Erista/Mariko platform.
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if (nx_hoag)
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_config_regulators(tegra_t210, nx_hoag);
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{
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max7762x_regulator_set_voltage(REGULATOR_LDO8, 2800000);
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max7762x_regulator_enable(REGULATOR_LDO8, true);
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}
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// Initialize I2C1 for various power related devices.
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// Initialize I2C1 for various power related devices.
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i2c_init(I2C_1);
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i2c_init(I2C_1);
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// Initialize various regulators based on Erista/Mariko platform.
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_config_regulators(tegra_t210);
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_config_pmc_scratch(); // Missing from 4.x+
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_config_pmc_scratch(); // Missing from 4.x+
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// Set BPMP/SCLK to PLLP_OUT (408MHz).
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// Set BPMP/SCLK to PLLP_OUT (408MHz).
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