From 853f10f7743c796f70d84307f378c8c4313bd133 Mon Sep 17 00:00:00 2001
From: CTCaer <ctcaer@gmail.com>
Date: Thu, 20 Jan 2022 12:13:35 +0200
Subject: [PATCH] bdk: pmc: update tzram defines

---
 bdk/soc/hw_init.c | 10 +++++-----
 bdk/soc/pmc.h     |  5 ++++-
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/bdk/soc/hw_init.c b/bdk/soc/hw_init.c
index 1643876..9bb80f5 100644
--- a/bdk/soc/hw_init.c
+++ b/bdk/soc/hw_init.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2021 CTCaer
+ * Copyright (c) 2018-2022 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -399,12 +399,12 @@ void hw_init()
 	// Set BPMP/SCLK to PLLP_OUT (408MHz).
 	CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333;
 
-	// Disable TZRAM shutdown control and lock the regs.
+	// Power on T210B01 shadow TZRAM and lock the reg.
 	if (!tegra_t210)
 	{
-		PMC(APBDEV_PMC_TZRAM_PWR_CNTRL) &= 0xFFFFFFFE;
-		PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE) = 3;
-		PMC(APBDEV_PMC_TZRAM_SEC_DISABLE) = 3;
+		PMC(APBDEV_PMC_TZRAM_PWR_CNTRL) &= ~PMC_TZRAM_PWR_CNTRL_SD;
+		PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ;
+		PMC(APBDEV_PMC_TZRAM_SEC_DISABLE) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ;
 	}
 
 	// Initialize External memory controller and configure DRAM parameters.
diff --git a/bdk/soc/pmc.h b/bdk/soc/pmc.h
index 334517a..c5ad559 100644
--- a/bdk/soc/pmc.h
+++ b/bdk/soc/pmc.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018 naehrwert
  * Copyright (c) 2018 st4rk
- * Copyright (c) 2018-2020 CTCaer
+ * Copyright (c) 2018-2022 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -107,8 +107,11 @@
 #define APBDEV_PMC_SECURE_SCRATCH109 0xB0C
 #define APBDEV_PMC_SECURE_SCRATCH110 0xB10
 #define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8
+#define  PMC_TZRAM_PWR_CNTRL_SD BIT(0)
 #define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
 #define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0
+#define  PMC_TZRAM_DISABLE_REG_WRITE BIT(0)
+#define  PMC_TZRAM_DISABLE_REG_READ  BIT(1)
 
 typedef enum _pmc_sec_lock_t
 {