From 8502731fbdc8c2f6d5c55c6c4b8143bcbecc7ec2 Mon Sep 17 00:00:00 2001 From: CTCaer Date: Fri, 9 Jun 2023 10:28:28 +0300 Subject: [PATCH] bdk: tsec: refactor some register names --- bdk/sec/tsec.c | 36 ++++++++++++++++++++---------------- bdk/sec/tsec_t210.h | 6 +++--- bdk/soc/t210.h | 19 ++++++++++--------- 3 files changed, 33 insertions(+), 28 deletions(-) diff --git a/bdk/sec/tsec.c b/bdk/sec/tsec.c index 306f9dc..3dcf084 100644 --- a/bdk/sec/tsec.c +++ b/bdk/sec/tsec.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2023 CTCaer * Copyright (c) 2018 balika011 * * This program is free software; you can redistribute it and/or modify it @@ -199,10 +199,10 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) // Execute firmware. HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0x34C2E1DA; - TSEC(TSEC_STATUS) = 0; - TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1. - TSEC(TSEC_BOOTVEC) = 0; - TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU; + TSEC(TSEC_MAILBOX1) = 0; + TSEC(TSEC_MAILBOX0) = 1; // Set HOS key version. + TSEC(TSEC_BOOTVEC) = 0; + TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU; if (type == TSEC_FW_TYPE_EMU) { @@ -245,7 +245,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) // for (int i = 0; i < kidx; i++) // gfx_printf("key %08X\n", key[i]); - // gfx_printf("cpuctl (%08X) mbox (%08X)\n", TSEC(TSEC_CPUCTL), TSEC(TSEC_STATUS)); + // gfx_printf("cpuctl (%08X) mbox (%08X)\n", TSEC(TSEC_CPUCTL), TSEC(TSEC_MAILBOX1)); // u32 errst = MC(MC_ERR_STATUS); // gfx_printf(" MC %08X %08X %08X\n", MC(MC_INTSTATUS), errst, MC(MC_ERR_ADR)); @@ -261,14 +261,18 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) res = -3; goto out_free; } + u32 timeout = get_tmr_ms() + 2000; - while (!TSEC(TSEC_STATUS)) + while (!TSEC(TSEC_MAILBOX1)) + { if (get_tmr_ms() > timeout) { res = -4; goto out_free; } - if (TSEC(TSEC_STATUS) != 0xB0B0B0B0) + } + + if (TSEC(TSEC_MAILBOX1) != 0xB0B0B0B0) { res = -5; goto out_free; @@ -277,14 +281,14 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) // Fetch result. HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0; u32 buf[4]; - buf[0] = SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB); - buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB); - buf[2] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB); - buf[3] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB); - SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB) = 0; - SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB) = 0; - SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB) = 0; - SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB) = 0; + buf[0] = SOR1(SOR_DP_HDCP_BKSV_LSB); + buf[1] = SOR1(SOR_TMDS_HDCP_BKSV_LSB); + buf[2] = SOR1(SOR_TMDS_HDCP_CN_MSB); + buf[3] = SOR1(SOR_TMDS_HDCP_CN_LSB); + SOR1(SOR_DP_HDCP_BKSV_LSB) = 0; + SOR1(SOR_TMDS_HDCP_BKSV_LSB) = 0; + SOR1(SOR_TMDS_HDCP_CN_MSB) = 0; + SOR1(SOR_TMDS_HDCP_CN_LSB) = 0; memcpy(tsec_keys, &buf, SE_KEY_128_SIZE); } diff --git a/bdk/sec/tsec_t210.h b/bdk/sec/tsec_t210.h index 889d0d4..96624e2 100644 --- a/bdk/sec/tsec_t210.h +++ b/bdk/sec/tsec_t210.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2018 CTCaer +* Copyright (c) 2018-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,8 +17,8 @@ #ifndef _TSEC_T210_H_ #define _TSEC_T210_H_ -#define TSEC_BOOTKEYVER 0x1040 -#define TSEC_STATUS 0x1044 +#define TSEC_MAILBOX0 0x1040 +#define TSEC_MAILBOX1 0x1044 #define TSEC_ITFEN 0x1048 #define TSEC_ITFEN_CTXEN BIT(0) #define TSEC_ITFEN_MTHDEN BIT(1) diff --git a/bdk/soc/t210.h b/bdk/soc/t210.h index 72a59f9..5de9e53 100644 --- a/bdk/soc/t210.h +++ b/bdk/soc/t210.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert -* Copyright (c) 2018-2022 CTCaer +* Copyright (c) 2018-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -135,10 +135,11 @@ #define USB1(off) _REG(USB1_BASE, off) #define TEST_REG(off) _REG(0x0, off) -/* HOST1X registers. */ -#define HOST1X_CH0_SYNC_BASE 0x2100 -#define HOST1X_CH0_SYNC_SYNCPT_9 (HOST1X_CH0_SYNC_BASE + 0xFA4) -#define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_BASE + 0x1200) +/* HOST1X v3 registers. */ +#define HOST1X_CH0_SYNC_BASE 0x2100 +#define HOST1X_CH0_SYNC_SYNCPT_BASE (HOST1X_CH0_SYNC_BASE + 0xF80) +#define HOST1X_CH0_SYNC_SYNCPT_9 (HOST1X_CH0_SYNC_SYNCPT_BASE + 0x24) +#define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_SYNCPT_BASE + 0x280) /*! EVP registers. */ #define EVP_CPU_RESET_VECTOR 0x100 @@ -223,10 +224,10 @@ #define SB_AA64_RESET_HIGH 0x34 /*! SOR registers. */ -#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB 0x1E8 -#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB 0x21C -#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB 0x208 -#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB 0x20C +#define SOR_DP_HDCP_BKSV_LSB 0x1E8 +#define SOR_TMDS_HDCP_BKSV_LSB 0x21C +#define SOR_TMDS_HDCP_CN_MSB 0x208 +#define SOR_TMDS_HDCP_CN_LSB 0x20C /*! RTC registers. */ #define APBDEV_RTC_SECONDS 0x8