diff --git a/bootloader/gfx/di.c b/bootloader/gfx/di.c index 8ff0293..4dcfe01 100644 --- a/bootloader/gfx/di.c +++ b/bootloader/gfx/di.c @@ -85,7 +85,7 @@ void display_init() exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4); exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94); - exec_cfg((u32 *)DSI_BASE, _display_config_3, 60); + exec_cfg((u32 *)DSI_BASE, _display_config_3, 61); usleep(10000); @@ -121,8 +121,8 @@ void display_init() usleep(20000); - exec_cfg((u32 *)DSI_BASE, _display_config_5, 21); exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3); + exec_cfg((u32 *)DSI_BASE, _display_config_5, 21); DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; exec_cfg((u32 *)DSI_BASE, _display_config_7, 10); diff --git a/bootloader/gfx/di.h b/bootloader/gfx/di.h index abd8197..b3dad4d 100644 --- a/bootloader/gfx/di.h +++ b/bootloader/gfx/di.h @@ -181,6 +181,7 @@ #define DC_WIN_WIN_OPTIONS 0x700 #define H_DIRECTION (1 << 0) #define V_DIRECTION (1 << 2) +#define SCAN_COLUMN (1 << 4) #define COLOR_EXPAND (1 << 6) #define CSC_ENABLE (1 << 18) #define WIN_ENABLE (1 << 30) @@ -228,6 +229,8 @@ #define V_DDA_INC(x) (((x) & 0xffff) << 16) #define DC_WIN_LINE_STRIDE 0x70A +#define LINE_STRIDE(x) (x) +#define UV_LINE_STRIDE(x) (((x) & 0xffff) << 16) #define DC_WIN_DV_CONTROL 0x70E // The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). @@ -340,6 +343,8 @@ #define DSI_PAD_CONTROL_4 0x52 +#define DSI_INIT_SEQ_DATA_15 0x5F + /*! Display backlight related PWM registers. */ #define PWM_CONTROLLER_PWM_CSR 0x00 diff --git a/bootloader/gfx/di.inl b/bootloader/gfx/di.inl index 907b1c0..fb6a93c 100644 --- a/bootloader/gfx/di.inl +++ b/bootloader/gfx/di.inl @@ -128,7 +128,7 @@ static const cfg_op_t _display_config_2[94] = { }; //DSI Init config. -static const cfg_op_t _display_config_3[60] = { +static const cfg_op_t _display_config_3[61] = { {DSI_WR_DATA, 0}, {DSI_INT_ENABLE, 0}, {DSI_INT_STATUS, 0}, @@ -137,6 +137,7 @@ static const cfg_op_t _display_config_3[60] = { {DSI_INIT_SEQ_DATA_1, 0}, {DSI_INIT_SEQ_DATA_2, 0}, {DSI_INIT_SEQ_DATA_3, 0}, + {DSI_INIT_SEQ_DATA_15, 0}, {DSI_DCS_CMDS, 0}, {DSI_PKT_SEQ_0_LO, 0}, {DSI_PKT_SEQ_1_LO, 0}, @@ -288,7 +289,7 @@ static const cfg_op_t _display_config_7[10] = { static const cfg_op_t _display_config_8[6] = { {0x18, 0}, {2, 0xF3F10000}, - {0x16, 1}, + {0x16, 0}, {0x18, 0}, {0x18, 0x10010}, {0x17, 0x300} @@ -474,10 +475,10 @@ static const cfg_op_t _display_config_13[16] = { {DSI_PAD_CONTROL_1, 0}, {DSI_PHY_TIMING_0, 0x6070601}, {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30109}, + {DSI_PHY_TIMING_2, 0x30118}, {DSI_BTA_TIMING, 0x190A14}, {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, {DSI_TO_TALLY, 0}, {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, @@ -544,7 +545,7 @@ static const cfg_op_t cfg_display_framebuffer[32] = { {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. - {DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. {DC_WIN_BUFFER_CONTROL, 0}, {DC_WINBUF_SURFACE_KIND, 0}, //Regular surface. {DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address. diff --git a/bootloader/main.c b/bootloader/main.c index fd56c19..b186a8d 100644 --- a/bootloader/main.c +++ b/bootloader/main.c @@ -370,6 +370,7 @@ void config_se_brom() // Clear the boot reason to avoid problems later PMC(APBDEV_PMC_SCRATCH200) = 0x0; PMC(APBDEV_PMC_RST_STATUS) = 0x0; + APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = 0x1C00; } void config_hw() @@ -419,6 +420,8 @@ void config_hw() i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_SD1, 0x29); i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_SD3, 0x1B); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3, 0x22); // 3.x+ + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD0, 42); //42 = (1125000 - 600000) / 12500 -> 1.125V config_pmc_scratch(); // Missing from 4.x+ diff --git a/bootloader/soc/cluster.c b/bootloader/soc/cluster.c index de3dbdd..857641a 100644 --- a/bootloader/soc/cluster.c +++ b/bootloader/soc/cluster.c @@ -27,11 +27,13 @@ void _cluster_enable_power() { u8 tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO); i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, tmp & 0xDF); - i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 0x09); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH); // Enable cores power. - i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_NFSR_ENABLE); - i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG, MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL); + i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, + MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE); // 1-3.x: MAX77621_NFSR_ENABLE + i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG, + MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL); // 1-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | 0x37); i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | 0x37); } @@ -103,7 +105,7 @@ void cluster_boot_cpu0(u32 entry) // Enable cluster 0 non-CPU. _cluster_pmc_enable_partition(0x8000, 15, true); // Enable CE0. - _cluster_pmc_enable_partition(0x4000, 14); + _cluster_pmc_enable_partition(0x4000, 14, true); // Request and wait for RAM repair. FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1; diff --git a/bootloader/soc/cluster.h b/bootloader/soc/cluster.h index 310ac8b..76e80c0 100644 --- a/bootloader/soc/cluster.h +++ b/bootloader/soc/cluster.h @@ -20,7 +20,15 @@ #include "../utils/types.h" /*! Flow controller registers. */ +#define LOW_CTLR_HALT_CPU0_EVENTS 0x0 +#define LOW_CTLR_HALT_CPU1_EVENTS 0x14 +#define LOW_CTLR_HALT_CPU2_EVENTS 0x1C +#define LOW_CTLR_HALT_CPU3_EVENTS 0x24 #define FLOW_CTLR_HALT_COP_EVENTS 0x4 +#define FLOW_CTLR_CPU0_CSR 0x8 +#define FLOW_CTLR_CPU1_CSR 0x18 +#define FLOW_CTLR_CPU2_CSR 0x20 +#define FLOW_CTLR_CPU3_CSR 0x28 #define FLOW_CTLR_RAM_REPAIR 0x40 #define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98 diff --git a/bootloader/soc/i2c.c b/bootloader/soc/i2c.c index df1c09d..e845693 100644 --- a/bootloader/soc/i2c.c +++ b/bootloader/soc/i2c.c @@ -61,7 +61,7 @@ static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size) static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x) { - if (size > 4) + if (size > 8) return 0; vu32 *base = (vu32 *)i2c_addrs[idx]; @@ -77,7 +77,14 @@ static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x) return 0; u32 tmp = base[I2C_CMD_DATA1]; // Get LS value. - memcpy(buf, &tmp, size); + if (size > 4) + { + memcpy(buf, &tmp, 4); + tmp = base[I2C_CMD_DATA2]; // Get MS value. + memcpy(buf + 4, &tmp, size - 4); + } + else + memcpy(buf, &tmp, size); return 1; } diff --git a/bootloader/soc/t210.h b/bootloader/soc/t210.h index 39bf1b4..5c45907 100644 --- a/bootloader/soc/t210.h +++ b/bootloader/soc/t210.h @@ -101,6 +101,7 @@ #define TEST_REG(off) _REG(0x0, off) /*! Misc registers. */ +#define APB_MISC_PP_STRAPPING_OPT_A 0x08 #define APB_MISC_PP_PINMUX_GLOBAL 0x40 #define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34 #define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64