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[DC/DSI] Replace hardcoded values with named values

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To better understand the procedure.
This commit is contained in:
Kostas Missos 2018-05-14 01:59:45 +03:00 committed by nwert
parent 7a771f4855
commit 7a22dddb01
3 changed files with 770 additions and 481 deletions
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46
ipl/di.c
View file

@ -87,31 +87,31 @@ void display_init()
sleep(60000); sleep(60000);
DSI(_DSIREG(DSI_DSI_BTA_TIMING)) = 0x50204; DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x337; DSI(_DSIREG(DSI_WR_DATA)) = 0x337;
DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
_display_dsi_wait(250000, _DSIREG(DSI_DSI_TRIGGER), 3); _display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x406; DSI(_DSIREG(DSI_WR_DATA)) = 0x406;
DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
_display_dsi_wait(250000, _DSIREG(DSI_DSI_TRIGGER), 3); _display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
DSI(_DSIREG(DSI_HOST_DSI_CONTROL)) = 0x200B; DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
_display_dsi_wait(150000, _DSIREG(DSI_HOST_DSI_CONTROL), 8); _display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
sleep(5000); sleep(5000);
_display_ver = DSI(_DSIREG(DSI_DSI_RD_DATA)); _display_ver = DSI(_DSIREG(DSI_RD_DATA));
if (_display_ver == 0x10) if (_display_ver == 0x10)
exec_cfg((u32 *)DSI_BASE, _display_config_4, 43); exec_cfg((u32 *)DSI_BASE, _display_config_4, 43);
DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x1105; DSI(_DSIREG(DSI_WR_DATA)) = 0x1105;
DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
sleep(180000); sleep(180000);
DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x2905; DSI(_DSIREG(DSI_WR_DATA)) = 0x2905;
DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
sleep(20000); sleep(20000);
@ -134,15 +134,15 @@ void display_init()
void display_end() void display_end()
{ {
GPIO_6(0x24) &= 0xFFFFFFFE; GPIO_6(0x24) &= 0xFFFFFFFE;
DSI(_DSIREG(DSI_DSI_VID_MODE_CONTROL)) = 1; DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 1;
DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x2805; DSI(_DSIREG(DSI_WR_DATA)) = 0x2805;
u32 end = HOST1X(0x30A4) + 5; u32 end = HOST1X(0x30A4) + 5;
while (HOST1X(0x30A4) < end) while (HOST1X(0x30A4) < end)
; ;
DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = 5; DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
DSI(_DSIREG(DSI_DSI_VID_MODE_CONTROL)) = 0; DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17); exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17);
exec_cfg((u32 *)DSI_BASE, _display_config_13, 16); exec_cfg((u32 *)DSI_BASE, _display_config_13, 16);
@ -152,8 +152,8 @@ void display_end()
if (_display_ver == 0x10) if (_display_ver == 0x10)
exec_cfg((u32 *)DSI_BASE, _display_config_14, 22); exec_cfg((u32 *)DSI_BASE, _display_config_14, 22);
DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x1005; DSI(_DSIREG(DSI_WR_DATA)) = 0x1005;
DSI(_DSIREG(DSI_DSI_TRIGGER)) = 2; DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
sleep(50000); sleep(50000);
@ -175,8 +175,8 @@ void display_end()
CLOCK(0x300) = 0x18000000; CLOCK(0x300) = 0x18000000;
CLOCK(0x324) = 0x18000000; CLOCK(0x324) = 0x18000000;
DSI(_DSIREG(DSI_PAD_CONTROL)) = 0x10F010F; DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
DSI(_DSIREG(DSI_DSI_POWER_CONTROL)) = 0; DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
GPIO_6(0x04) &= 0xFFFFFFFE; GPIO_6(0x04) &= 0xFFFFFFFE;
@ -193,7 +193,7 @@ void display_color_screen(u32 color)
DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0; DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0;
DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0; DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color; DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE | 1; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE | GENERAL_ACT_REQ;
sleep(35000); sleep(35000);

317
ipl/di.h
View file

@ -21,44 +21,319 @@
/*! Display registers. */ /*! Display registers. */
#define _DIREG(reg) ((reg) * 4) #define _DIREG(reg) ((reg) * 4)
#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
#define SYNCPT_CNTRL_NO_STALL (1 << 8)
#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
#define SYNCPT_VSYNC_ENABLE (1 << 8)
#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
#define DC_CMD_DISPLAY_COMMAND 0x32 #define DC_CMD_DISPLAY_COMMAND 0x32
#define DISP_CTRL_MODE_STOP (0 << 5)
#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
#define DISP_CTRL_MODE_MASK (3 << 5)
#define DC_CMD_DISPLAY_POWER_CONTROL 0x36
#define PW0_ENABLE (1 << 0)
#define PW1_ENABLE (1 << 2)
#define PW2_ENABLE (1 << 4)
#define PW3_ENABLE (1 << 6)
#define PW4_ENABLE (1 << 8)
#define PM0_ENABLE (1 << 16)
#define PM1_ENABLE (1 << 18)
#define DC_CMD_INT_MASK 0x38
#define DC_CMD_INT_ENABLE 0x39
#define DC_CMD_STATE_ACCESS 0x40 #define DC_CMD_STATE_ACCESS 0x40
#define READ_MUX (1 << 0)
#define WRITE_MUX (1 << 2)
#define DC_CMD_STATE_CONTROL 0x41 #define DC_CMD_STATE_CONTROL 0x41
#define GENERAL_ACT_REQ (1 << 0)
#define WIN_A_ACT_REQ (1 << 1)
#define WIN_B_ACT_REQ (1 << 2)
#define WIN_C_ACT_REQ (1 << 3)
#define CURSOR_ACT_REQ (1 << 7)
#define GENERAL_UPDATE (1 << 8)
#define WIN_A_UPDATE (1 << 9)
#define WIN_B_UPDATE (1 << 10)
#define WIN_C_UPDATE (1 << 11)
#define CURSOR_UPDATE (1 << 15)
#define NC_HOST_TRIG (1 << 24)
#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
#define WINDOW_A_SELECT (1 << 4)
#define WINDOW_B_SELECT (1 << 5)
#define WINDOW_C_SELECT (1 << 6)
#define DC_CMD_REG_ACT_CONTROL 0x043
#define DC_COM_CRC_CONTROL 0x300
#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
#define DC_DISP_DISP_WIN_OPTIONS 0x402 #define DC_DISP_DISP_WIN_OPTIONS 0x402
#define HDMI_ENABLE (1 << 30)
#define DSI_ENABLE (1 << 29)
#define SOR1_TIMING_CYA (1 << 27)
#define SOR1_ENABLE (1 << 26)
#define SOR_ENABLE (1 << 25)
#define CURSOR_ENABLE (1 << 16)
#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
#define DC_DISP_DISP_TIMING_OPTIONS 0x405
#define DC_DISP_REF_TO_SYNC 0x406
#define DC_DISP_SYNC_WIDTH 0x407
#define DC_DISP_BACK_PORCH 0x408
#define DC_DISP_ACTIVE 0x409
#define DC_DISP_FRONT_PORCH 0x40A
#define DC_DISP_DISP_CLOCK_CONTROL 0x42E #define DC_DISP_DISP_CLOCK_CONTROL 0x42E
#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F
#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
#define DISP_DATA_FORMAT_DF2S (4 << 0)
#define DISP_DATA_FORMAT_DF3S (5 << 0)
#define DISP_DATA_FORMAT_DFSPI (6 << 0)
#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
#define DISP_ALIGNMENT_MSB (0 << 8)
#define DISP_ALIGNMENT_LSB (1 << 8)
#define DISP_ORDER_RED_BLUE (0 << 9)
#define DISP_ORDER_BLUE_RED (1 << 9)
#define DC_DISP_DISP_COLOR_CONTROL 0x430
#define DITHER_CONTROL_MASK (3 << 8)
#define DITHER_CONTROL_DISABLE (0 << 8)
#define DITHER_CONTROL_ORDERED (2 << 8)
#define DITHER_CONTROL_ERRDIFF (3 << 8)
#define BASE_COLOR_SIZE_MASK (0xf << 0)
#define BASE_COLOR_SIZE_666 (0 << 0)
#define BASE_COLOR_SIZE_111 (1 << 0)
#define BASE_COLOR_SIZE_222 (2 << 0)
#define BASE_COLOR_SIZE_333 (3 << 0)
#define BASE_COLOR_SIZE_444 (4 << 0)
#define BASE_COLOR_SIZE_555 (5 << 0)
#define BASE_COLOR_SIZE_565 (6 << 0)
#define BASE_COLOR_SIZE_332 (7 << 0)
#define BASE_COLOR_SIZE_888 (8 << 0)
#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
#define SC1_H_QUALIFIER_NONE (1 << 16)
#define SC0_H_QUALIFIER_NONE (1 << 0)
#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
#define DE_SELECT_ACTIVE_BLANK (0 << 0)
#define DE_SELECT_ACTIVE (1 << 0)
#define DE_SELECT_ACTIVE_IS (2 << 0)
#define DE_CONTROL_ONECLK (0 << 2)
#define DE_CONTROL_NORMAL (1 << 2)
#define DE_CONTROL_EARLY_EXT (2 << 2)
#define DE_CONTROL_EARLY (3 << 2)
#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4 #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
#define DC_WIN_CSC_YOF 0x611
#define DC_WIN_CSC_KYRGB 0x612
#define DC_WIN_CSC_KUR 0x613
#define DC_WIN_CSC_KVR 0x614
#define DC_WIN_CSC_KUG 0x615
#define DC_WIN_CSC_KVG 0x616
#define DC_WIN_CSC_KUB 0x617
#define DC_WIN_CSC_KVB 0x618
#define DC_WIN_AD_WIN_OPTIONS 0xB80 #define DC_WIN_AD_WIN_OPTIONS 0xB80
#define DC_WIN_BD_WIN_OPTIONS 0xD80 #define DC_WIN_BD_WIN_OPTIONS 0xD80
#define DC_WIN_CD_WIN_OPTIONS 0xF80 #define DC_WIN_CD_WIN_OPTIONS 0xF80
//The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER). //The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER).
#define DC_X_WIN_XD_WIN_OPTIONS 0x700 #define DC_WIN_WIN_OPTIONS 0x700
#define DC_X_WIN_XD_COLOR_DEPTH 0x703 #define H_DIRECTION (1 << 0)
#define DC_X_WIN_XD_POSITION 0x704 #define V_DIRECTION (1 << 2)
#define DC_X_WIN_XD_SIZE 0x705 #define COLOR_EXPAND (1 << 6)
#define DC_X_WIN_XD_PRESCALED_SIZE 0x706 #define CSC_ENABLE (1 << 18)
#define DC_X_WIN_XD_H_INITIAL_DDA 0x707 #define WIN_ENABLE (1 << 30)
#define DC_X_WIN_XD_V_INITIAL_DDA 0x708
#define DC_X_WIN_XD_DDA_INCREMENT 0x709 #define DC_WIN_COLOR_DEPTH 0x703
#define DC_X_WIN_XD_LINE_STRIDE 0x70A #define WIN_COLOR_DEPTH_P1 0x0
#define WIN_COLOR_DEPTH_P2 0x1
#define WIN_COLOR_DEPTH_P4 0x2
#define WIN_COLOR_DEPTH_P8 0x3
#define WIN_COLOR_DEPTH_B4G4R4A4 0x4
#define WIN_COLOR_DEPTH_B5G5R5A 0x5
#define WIN_COLOR_DEPTH_B5G6R5 0x6
#define WIN_COLOR_DEPTH_AB5G5R5 0x7
#define WIN_COLOR_DEPTH_B8G8R8A8 0xC
#define WIN_COLOR_DEPTH_R8G8B8A8 0xD
#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE
#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF
#define WIN_COLOR_DEPTH_YCbCr422 0x10
#define WIN_COLOR_DEPTH_YUV422 0x11
#define WIN_COLOR_DEPTH_YCbCr420P 0x12
#define WIN_COLOR_DEPTH_YUV420P 0x13
#define WIN_COLOR_DEPTH_YCbCr422P 0x14
#define WIN_COLOR_DEPTH_YUV422P 0x15
#define WIN_COLOR_DEPTH_YCbCr422R 0x16
#define WIN_COLOR_DEPTH_YUV422R 0x17
#define WIN_COLOR_DEPTH_YCbCr422RA 0x18
#define WIN_COLOR_DEPTH_YUV422RA 0x19
#define DC_WIN_BUFFER_CONTROL 0x702
#define DC_WIN_POSITION 0x704
#define DC_WIN_SIZE 0x705
#define H_SIZE(x) (((x) & 0x1fff) << 0)
#define V_SIZE(x) (((x) & 0x1fff) << 16)
#define DC_WIN_PRESCALED_SIZE 0x706
#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
#define DC_WIN_H_INITIAL_DDA 0x707
#define DC_WIN_V_INITIAL_DDA 0x708
#define DC_WIN_DDA_INC 0x709
#define H_DDA_INC(x) (((x) & 0xffff) << 0)
#define V_DDA_INC(x) (((x) & 0xffff) << 16)
#define DC_WIN_LINE_STRIDE 0x70A
#define DC_WIN_DV_CONTROL 0x70E
//The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). //The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER).
#define DC_X_WINBUF_XD_START_ADDR 0x800 #define DC_WINBUF_START_ADDR 0x800
#define DC_X_WINBUF_XD_ADDR_H_OFFSET 0x806 #define DC_WINBUF_ADDR_H_OFFSET 0x806
#define DC_X_WINBUF_XD_ADDR_V_OFFSET 0x808 #define DC_WINBUF_ADDR_V_OFFSET 0x808
#define DC_X_WINBUF_XD_SURFACE_KIND 0x80B #define DC_WINBUF_SURFACE_KIND 0x80B
/*! Display serial interface registers. */ /*! Display serial interface registers. */
#define _DSIREG(reg) ((reg) * 4) #define _DSIREG(reg) ((reg) * 4)
#define DSI_DSI_RD_DATA 0x9
#define DSI_DSI_WR_DATA 0xA #define DSI_RD_DATA 0x9
#define DSI_DSI_POWER_CONTROL 0xB #define DSI_WR_DATA 0xA
#define DSI_HOST_DSI_CONTROL 0xF
#define DSI_DSI_TRIGGER 0x13 #define DSI_POWER_CONTROL 0xB
#define DSI_DSI_BTA_TIMING 0x3F #define DSI_POWER_CONTROL_ENABLE 1
#define DSI_PAD_CONTROL 0x4B
#define DSI_DSI_VID_MODE_CONTROL 0x4E #define DSI_INT_ENABLE 0xC
#define DSI_INT_STATUS 0xD
#define DSI_INT_MASK 0xE
#define DSI_HOST_CONTROL 0xF
#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
#define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
#define DSI_HOST_CONTROL_RAW (1 << 6)
#define DSI_HOST_CONTROL_HS (1 << 5)
#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
#define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
#define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
#define DSI_HOST_CONTROL_CS (1 << 1)
#define DSI_HOST_CONTROL_ECC (1 << 0)
#define DSI_CONTROL 0x10
#define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
#define DSI_CONTROL_DCS_ENABLE (1 << 3)
#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
#define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
#define DSI_CONTROL_HOST_ENABLE (1 << 0)
#define DSI_SOL_DELAY 0x11
#define DSI_MAX_THRESHOLD 0x12
#define DSI_TRIGGER 0x13
#define DSI_TRIGGER_HOST (1 << 1)
#define DSI_TRIGGER_VIDEO (1 << 0)
#define DSI_TX_CRC 0x14
#define DSI_STATUS 0x15
#define DSI_INIT_SEQ_CONTROL 0x1A
#define DSI_INIT_SEQ_DATA_0 0x1B
#define DSI_INIT_SEQ_DATA_1 0x1C
#define DSI_INIT_SEQ_DATA_2 0x1D
#define DSI_INIT_SEQ_DATA_3 0x1E
#define DSI_PKT_SEQ_0_LO 0x23
#define DSI_PKT_SEQ_0_HI 0x24
#define DSI_PKT_SEQ_1_LO 0x25
#define DSI_PKT_SEQ_1_HI 0x26
#define DSI_PKT_SEQ_2_LO 0x27
#define DSI_PKT_SEQ_2_HI 0x28
#define DSI_PKT_SEQ_3_LO 0x29
#define DSI_PKT_SEQ_3_HI 0x2A
#define DSI_PKT_SEQ_4_LO 0x2B
#define DSI_PKT_SEQ_4_HI 0x2C
#define DSI_PKT_SEQ_5_LO 0x2D
#define DSI_PKT_SEQ_5_HI 0x2E
#define DSI_DCS_CMDS 0x33
#define DSI_PKT_LEN_0_1 0x34
#define DSI_PKT_LEN_2_3 0x35
#define DSI_PKT_LEN_4_5 0x36
#define DSI_PKT_LEN_6_7 0x37
#define DSI_PHY_TIMING_0 0x3C
#define DSI_PHY_TIMING_1 0x3D
#define DSI_PHY_TIMING_2 0x3E
#define DSI_BTA_TIMING 0x3F
#define DSI_TIMEOUT_0 0x44
#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
#define DSI_TIMEOUT_1 0x45
#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
#define DSI_TO_TALLY 0x46
#define DSI_PAD_CONTROL_0 0x4B
#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
#define DSI_PAD_CONTROL_CD 0x4c
#define DSI_VIDEO_MODE_CONTROL 0x4E
#define DSI_PAD_CONTROL_1 0x4F
#define DSI_PAD_CONTROL_2 0x50
#define DSI_PAD_CONTROL_3 0x51
#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
#define DSI_PAD_CONTROL_4 0x52
void display_init(); void display_init();
void display_end(); void display_end();

888
ipl/di.inl
View file

@ -18,263 +18,269 @@
static const cfg_op_t _display_config_1[4] = { static const cfg_op_t _display_config_1[4] = {
{0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 {0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1
{0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE {0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE
{0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1
{0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC {0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC
}; };
//Display A config. //Display A config.
static const cfg_op_t _display_config_2[94] = { static const cfg_op_t _display_config_2[94] = {
{0x40, 0}, {DC_CMD_STATE_ACCESS, 0},
{DC_CMD_STATE_CONTROL, 0x100}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{DC_CMD_STATE_CONTROL, 1}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{0x43, 0x54}, {DC_CMD_REG_ACT_CONTROL, 0x54},
{DC_CMD_STATE_CONTROL, 0x100}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{DC_CMD_STATE_CONTROL, 1}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x42, 0x20}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x42, 0x40}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x480, 0}, {DC_DISP_DC_MCCIF_FIFOCTRL, 0},
{0x403, 0}, {DC_DISP_DISP_MEM_HIGH_PRIORITY, 0},
{0x404, 0}, {DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0},
{0x36, 0x50155}, {DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE},
{1, 0x100}, {DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL},
{0x28, 0x109}, {DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT
{DC_CMD_STATE_CONTROL, 0xF00}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{DC_CMD_STATE_CONTROL, 0xF}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{0x40, 0}, {DC_CMD_STATE_ACCESS, 0},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x70E, 0}, {DC_WIN_DV_CONTROL, 0},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x611, 0xF0}, /* Setup default YUV colorspace conversion coefficients */
{0x612, 0x12A}, {DC_WIN_CSC_YOF, 0xF0},
{0x613, 0}, {DC_WIN_CSC_KYRGB, 0x12A},
{0x614, 0x198}, {DC_WIN_CSC_KUR, 0},
{0x615, 0x39B}, {DC_WIN_CSC_KVR, 0x198},
{0x616, 0x32F}, {DC_WIN_CSC_KUG, 0x39B},
{0x617, 0x204}, {DC_WIN_CSC_KVG, 0x32F},
{0x618, 0}, {DC_WIN_CSC_KUB, 0x204},
{0x42, 0x20}, {DC_WIN_CSC_KVB, 0},
{0x700, 0}, /* End of color coefficients */
{0x42, 0x20}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x70E, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x700, 0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x42, 0x20}, {DC_WIN_DV_CONTROL, 0},
{0x42, 0x20}, {DC_WIN_WIN_OPTIONS, 0},
{0x611, 0xF0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x612, 0x12A}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x613, 0}, /* Setup default YUV colorspace conversion coefficients */
{0x614, 0x198}, {DC_WIN_CSC_YOF, 0xF0},
{0x615, 0x39B}, {DC_WIN_CSC_KYRGB, 0x12A},
{0x616, 0x32F}, {DC_WIN_CSC_KUR, 0},
{0x617, 0x204}, {DC_WIN_CSC_KVR, 0x198},
{0x618, 0}, {DC_WIN_CSC_KUG, 0x39B},
{0x42, 0x40}, {DC_WIN_CSC_KVG, 0x32F},
{0x700, 0}, {DC_WIN_CSC_KUB, 0x204},
{0x42, 0x40}, {DC_WIN_CSC_KVB, 0},
{0x70E, 0}, /* End of color coefficients */
{0x700, 0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x42, 0x40}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x40}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x611, 0xF0}, {DC_WIN_DV_CONTROL, 0},
{0x612, 0x12A}, {DC_WIN_WIN_OPTIONS, 0},
{0x613, 0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x614, 0x198}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x615, 0x39B}, /* Setup default YUV colorspace conversion coefficients */
{0x616, 0x32F}, {DC_WIN_CSC_YOF, 0xF0},
{0x617, 0x204}, {DC_WIN_CSC_KYRGB, 0x12A},
{0x618, 0}, {DC_WIN_CSC_KUR, 0},
{0x42, 0x10}, {DC_WIN_CSC_KVR, 0x198},
{0x700, 0}, {DC_WIN_CSC_KUG, 0x39B},
{0x42, 0x20}, {DC_WIN_CSC_KVG, 0x32F},
{0x700, 0}, {DC_WIN_CSC_KUB, 0x204},
{0x42, 0x40}, {DC_WIN_CSC_KVB, 0},
{0x700, 0}, /* End of color coefficients */
{0x430, 8}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x42F, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x307, 0x1000000}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x309, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{DC_WIN_WIN_OPTIONS, 0},
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
{0x4E4, 0}, {0x4E4, 0},
{0x300, 0}, {DC_COM_CRC_CONTROL, 0},
{DC_CMD_STATE_CONTROL, 0xF00}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{DC_CMD_STATE_CONTROL, 0xF}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x716, 0x10000FF}, {0x716, 0x10000FF},
{0x42, 0x20}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x716, 0x10000FF}, {0x716, 0x10000FF},
{0x42, 0x40}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x716, 0x10000FF}, {0x716, 0x10000FF},
{0x31, 0}, {DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x20}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x40}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x402, 0}, {DC_DISP_DISP_WIN_OPTIONS, 0},
{0x32, 0}, {DC_CMD_DISPLAY_COMMAND, 0},
{DC_CMD_STATE_CONTROL, 0xF00}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{DC_CMD_STATE_CONTROL, 0xF} {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}
}; };
//DSI config. //DSI Init config.
static const cfg_op_t _display_config_3[60] = { static const cfg_op_t _display_config_3[60] = {
{0xA, 0}, {DSI_WR_DATA, 0},
{0xC, 0}, {DSI_INT_ENABLE, 0},
{0xD, 0}, {DSI_INT_STATUS, 0},
{0xE, 0}, {DSI_INT_MASK, 0},
{0x1B, 0}, {DSI_INIT_SEQ_DATA_0, 0},
{0x1C, 0}, {DSI_INIT_SEQ_DATA_1, 0},
{0x1D, 0}, {DSI_INIT_SEQ_DATA_2, 0},
{0x1E, 0}, {DSI_INIT_SEQ_DATA_3, 0},
{0x33, 0}, {DSI_DCS_CMDS, 0},
{0x23, 0}, {DSI_PKT_SEQ_0_LO, 0},
{0x25, 0}, {DSI_PKT_SEQ_1_LO, 0},
{0x27, 0}, {DSI_PKT_SEQ_2_LO, 0},
{0x29, 0}, {DSI_PKT_SEQ_3_LO, 0},
{0x2B, 0}, {DSI_PKT_SEQ_4_LO, 0},
{0x2D, 0}, {DSI_PKT_SEQ_5_LO, 0},
{0x24, 0}, {DSI_PKT_SEQ_0_HI, 0},
{0x26, 0}, {DSI_PKT_SEQ_1_HI, 0},
{0x28, 0}, {DSI_PKT_SEQ_2_HI, 0},
{0x2A, 0}, {DSI_PKT_SEQ_3_HI, 0},
{0x2C, 0}, {DSI_PKT_SEQ_4_HI, 0},
{0x2E, 0}, {DSI_PKT_SEQ_5_HI, 0},
{0x10, 0}, {DSI_CONTROL, 0},
{0x4C, 0}, {DSI_PAD_CONTROL_CD, 0},
{0x11, 0x18}, {DSI_SOL_DELAY, 0x18},
{0x12, 0x1E0}, {DSI_MAX_THRESHOLD, 0x1E0},
{0x13, 0}, {DSI_TRIGGER, 0},
{0x1A, 0}, {DSI_INIT_SEQ_CONTROL, 0},
{0x34, 0}, {DSI_PKT_LEN_0_1, 0},
{0x35, 0}, {DSI_PKT_LEN_2_3, 0},
{0x36, 0}, {DSI_PKT_LEN_4_5, 0},
{0x37, 0}, {DSI_PKT_LEN_6_7, 0},
{0x4F, 0}, {DSI_PAD_CONTROL_1, 0},
{0x3C, 0x6070601}, {DSI_PHY_TIMING_0, 0x6070601},
{0x3D, 0x40A0E05}, {DSI_PHY_TIMING_1, 0x40A0E05},
{0x3E, 0x30109}, {DSI_PHY_TIMING_2, 0x30109},
{0x3F, 0x190A14}, {DSI_BTA_TIMING, 0x190A14},
{0x44, 0x2000FFFF}, {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
{0x45, 0x7652000}, {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
{0x46, 0}, {DSI_TO_TALLY, 0},
{0x4B, 0}, {DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable
{DSI_DSI_POWER_CONTROL, 1}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{DSI_DSI_POWER_CONTROL, 1}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{DSI_DSI_POWER_CONTROL, 0}, {DSI_POWER_CONTROL, 0},
{DSI_DSI_POWER_CONTROL, 0}, {DSI_POWER_CONTROL, 0},
{0x4F, 0}, {DSI_PAD_CONTROL_1, 0},
{0x3C, 0x6070601}, {DSI_PHY_TIMING_0, 0x6070601},
{0x3D, 0x40A0E05}, {DSI_PHY_TIMING_1, 0x40A0E05},
{0x3E, 0x30118}, {DSI_PHY_TIMING_2, 0x30118},
{0x3F, 0x190A14}, {DSI_BTA_TIMING, 0x190A14},
{0x44, 0x2000FFFF}, {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
{0x45, 0x13432000}, {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
{0x46, 0}, {DSI_TO_TALLY, 0},
{0xF, 0x102003}, {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{0x10, 0x31}, {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
{DSI_DSI_POWER_CONTROL, 1}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{DSI_DSI_POWER_CONTROL, 1}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{0x12, 0x40}, {DSI_MAX_THRESHOLD, 0x40},
{0x13, 0}, {DSI_TRIGGER, 0},
{0x14, 0}, {DSI_TX_CRC, 0},
{0x1A, 0} {DSI_INIT_SEQ_CONTROL, 0}
}; };
//DSI config (if ver == 0x10). //DSI config (if ver == 0x10).
static const cfg_op_t _display_config_4[43] = { static const cfg_op_t _display_config_4[43] = {
{DSI_DSI_WR_DATA, 0x439}, {DSI_WR_DATA, 0x439},
{DSI_DSI_WR_DATA, 0x9483FFB9}, {DSI_WR_DATA, 0x9483FFB9},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0xBD15}, {DSI_WR_DATA, 0xBD15},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0x1939}, {DSI_WR_DATA, 0x1939},
{DSI_DSI_WR_DATA, 0xAAAAAAD8}, {DSI_WR_DATA, 0xAAAAAAD8},
{DSI_DSI_WR_DATA, 0xAAAAAAEB}, {DSI_WR_DATA, 0xAAAAAAEB},
{DSI_DSI_WR_DATA, 0xAAEBAAAA}, {DSI_WR_DATA, 0xAAEBAAAA},
{DSI_DSI_WR_DATA, 0xAAAAAAAA}, {DSI_WR_DATA, 0xAAAAAAAA},
{DSI_DSI_WR_DATA, 0xAAAAAAEB}, {DSI_WR_DATA, 0xAAAAAAEB},
{DSI_DSI_WR_DATA, 0xAAEBAAAA}, {DSI_WR_DATA, 0xAAEBAAAA},
{DSI_DSI_WR_DATA, 0xAA}, {DSI_WR_DATA, 0xAA},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0x1BD15}, {DSI_WR_DATA, 0x1BD15},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0x2739}, {DSI_WR_DATA, 0x2739},
{DSI_DSI_WR_DATA, 0xFFFFFFD8}, {DSI_WR_DATA, 0xFFFFFFD8},
{DSI_DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF},
{DSI_DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF},
{DSI_DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF},
{DSI_DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF},
{DSI_DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF},
{DSI_DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF},
{DSI_DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF},
{DSI_DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF},
{DSI_DSI_WR_DATA, 0xFFFFFF}, {DSI_WR_DATA, 0xFFFFFF},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0x2BD15}, {DSI_WR_DATA, 0x2BD15},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0xF39}, {DSI_WR_DATA, 0xF39},
{DSI_DSI_WR_DATA, 0xFFFFFFD8}, {DSI_WR_DATA, 0xFFFFFFD8},
{DSI_DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF},
{DSI_DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF},
{DSI_DSI_WR_DATA, 0xFFFFFF}, {DSI_WR_DATA, 0xFFFFFF},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0xBD15}, {DSI_WR_DATA, 0xBD15},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0x6D915}, {DSI_WR_DATA, 0x6D915},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0x439}, {DSI_WR_DATA, 0x439},
{DSI_DSI_WR_DATA, 0xB9}, {DSI_WR_DATA, 0xB9},
{DSI_DSI_TRIGGER, 2} {DSI_TRIGGER, DSI_TRIGGER_HOST}
}; };
//DSI config. //DSI config.
static const cfg_op_t _display_config_5[21] = { static const cfg_op_t _display_config_5[21] = {
{0x4F, 0}, {DSI_PAD_CONTROL_1, 0},
{0x3C, 0x6070601}, {DSI_PHY_TIMING_0, 0x6070601},
{0x3D, 0x40A0E05}, {DSI_PHY_TIMING_1, 0x40A0E05},
{0x3E, 0x30172}, {DSI_PHY_TIMING_2, 0x30172},
{0x3F, 0x190A14}, {DSI_BTA_TIMING, 0x190A14},
{0x44, 0x20000A40}, {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
{0x45, 0x5A2F2000}, {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
{0x46, 0}, {DSI_TO_TALLY, 0},
{0x23, 0x40000208}, {DSI_PKT_SEQ_0_LO, 0x40000208},
{0x27, 0x40000308}, {DSI_PKT_SEQ_2_LO, 0x40000308},
{0x2B, 0x40000308}, {DSI_PKT_SEQ_4_LO, 0x40000308},
{0x25, 0x40000308}, {DSI_PKT_SEQ_1_LO, 0x40000308},
{0x29, 0x3F3B2B08}, {DSI_PKT_SEQ_3_LO, 0x3F3B2B08},
{0x2A, 0x2CC}, {DSI_PKT_SEQ_3_HI, 0x2CC},
{0x2D, 0x3F3B2B08}, {DSI_PKT_SEQ_5_LO, 0x3F3B2B08},
{0x2E, 0x2CC}, {DSI_PKT_SEQ_5_HI, 0x2CC},
{0x34, 0xCE0000}, {DSI_PKT_LEN_0_1, 0xCE0000},
{0x35, 0x87001A2}, {DSI_PKT_LEN_2_3, 0x87001A2},
{0x36, 0x190}, {DSI_PKT_LEN_4_5, 0x190},
{0x37, 0x190}, {DSI_PKT_LEN_6_7, 0x190},
{0xF, 0}, {DSI_HOST_CONTROL, 0},
}; };
//Clock config. //Clock config.
static const cfg_op_t _display_config_6[3] = { static const cfg_op_t _display_config_6[3] = {
{0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE {0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE
{0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1
{0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC {0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC
}; };
//DSI config. //DSI config.
static const cfg_op_t _display_config_7[10] = { static const cfg_op_t _display_config_7[10] = {
{0x13, 0}, {DSI_TRIGGER, 0},
{0x10, 0}, {DSI_CONTROL, 0},
{0x11, 6}, {DSI_SOL_DELAY, 6},
{0x12, 0x1E0}, {DSI_MAX_THRESHOLD, 0x1E0},
{DSI_DSI_POWER_CONTROL, 1}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{0x10, 0x103032}, {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
{0xF, 0x33}, {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{0x10, 0x103032}, {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
{0xF, 3}, {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{0xF, 0x23} {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
}; };
//MIPI CAL config. //MIPI CAL config.
@ -289,10 +295,10 @@ static const cfg_op_t _display_config_8[6] = {
//DSI config. //DSI config.
static const cfg_op_t _display_config_9[4] = { static const cfg_op_t _display_config_9[4] = {
{0x4F, 0}, {DSI_PAD_CONTROL_1, 0},
{0x50, 0}, {DSI_PAD_CONTROL_2, 0},
{0x51, 0x3333}, {DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
{0x52, 0} {DSI_PAD_CONTROL_4, 0}
}; };
//MIPI CAL config. //MIPI CAL config.
@ -317,232 +323,240 @@ static const cfg_op_t _display_config_10[16] = {
//Display A config. //Display A config.
static const cfg_op_t _display_config_11[113] = { static const cfg_op_t _display_config_11[113] = {
{0x40, 0}, {DC_CMD_STATE_ACCESS, 0},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x70E, 0}, {DC_WIN_DV_CONTROL, 0},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x611, 0xF0}, /* Setup default YUV colorspace conversion coefficients */
{0x612, 0x12A}, {DC_WIN_CSC_YOF, 0xF0},
{0x613, 0}, {DC_WIN_CSC_KYRGB, 0x12A},
{0x614, 0x198}, {DC_WIN_CSC_KUR, 0},
{0x615, 0x39B}, {DC_WIN_CSC_KVR, 0x198},
{0x616, 0x32F}, {DC_WIN_CSC_KUG, 0x39B},
{0x617, 0x204}, {DC_WIN_CSC_KVG, 0x32F},
{0x618, 0}, {DC_WIN_CSC_KUB, 0x204},
{0x42, 0x20}, {DC_WIN_CSC_KVB, 0},
{0x700, 0}, /* End of color coefficients */
{0x42, 0x20}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x70E, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x700, 0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x42, 0x20}, {DC_WIN_DV_CONTROL, 0},
{0x42, 0x20}, {DC_WIN_WIN_OPTIONS, 0},
{0x611, 0xF0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x612, 0x12A}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x613, 0}, /* Setup default YUV colorspace conversion coefficients */
{0x614, 0x198}, {DC_WIN_CSC_YOF, 0xF0},
{0x615, 0x39B}, {DC_WIN_CSC_KYRGB, 0x12A},
{0x616, 0x32F}, {DC_WIN_CSC_KUR, 0},
{0x617, 0x204}, {DC_WIN_CSC_KVR, 0x198},
{0x618, 0}, {DC_WIN_CSC_KUG, 0x39B},
{0x42, 0x40}, {DC_WIN_CSC_KVG, 0x32F},
{0x700, 0}, {DC_WIN_CSC_KUB, 0x204},
{0x42, 0x40}, {DC_WIN_CSC_KVB, 0},
{0x70E, 0}, /* End of color coefficients */
{0x700, 0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x42, 0x40}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x40}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x611, 0xF0}, {DC_WIN_DV_CONTROL, 0},
{0x612, 0x12A}, {DC_WIN_WIN_OPTIONS, 0},
{0x613, 0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x614, 0x198}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x615, 0x39B}, /* Setup default YUV colorspace conversion coefficients */
{0x616, 0x32F}, {DC_WIN_CSC_YOF, 0xF0},
{0x617, 0x204}, {DC_WIN_CSC_KYRGB, 0x12A},
{0x618, 0}, {DC_WIN_CSC_KUR, 0},
{0x42, 0x10}, {DC_WIN_CSC_KVR, 0x198},
{0x700, 0}, {DC_WIN_CSC_KUG, 0x39B},
{0x42, 0x20}, {DC_WIN_CSC_KVG, 0x32F},
{0x700, 0}, {DC_WIN_CSC_KUB, 0x204},
{0x42, 0x40}, {DC_WIN_CSC_KVB, 0},
{0x700, 0}, /* End of color coefficients */
{0x430, 8}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x42F, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x307, 0x1000000}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x309, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{DC_WIN_WIN_OPTIONS, 0},
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
{0x4E4, 0}, {0x4E4, 0},
{0x300, 0}, {DC_COM_CRC_CONTROL, 0},
{DC_CMD_STATE_CONTROL, 0xF00}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{DC_CMD_STATE_CONTROL, 0xF}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x716, 0x10000FF}, {0x716, 0x10000FF},
{0x42, 0x20}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x716, 0x10000FF}, {0x716, 0x10000FF},
{0x42, 0x40}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x716, 0x10000FF}, {0x716, 0x10000FF},
{0x31, 0}, {DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
{0x42, 0x10}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x20}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x40}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x402, 0}, {DC_DISP_DISP_WIN_OPTIONS, 0},
{0x32, 0}, {DC_CMD_DISPLAY_COMMAND, 0},
{DC_CMD_STATE_CONTROL, 0xF00}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{DC_CMD_STATE_CONTROL, 0xF}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{0x40, 0}, {DC_CMD_STATE_ACCESS, 0},
{0x405, 0}, /* Set Display timings */
{0x406, 0x10000}, {DC_DISP_DISP_TIMING_OPTIONS, 0},
{0x407, 0x10048}, {DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1.
{0x408, 0x90048}, {DC_DISP_SYNC_WIDTH, 0x10048},
{0x409, 0x50002D0}, {DC_DISP_BACK_PORCH, 0x90048},
{0x40A, 0xA0088}, {DC_DISP_ACTIVE, 0x50002D0},
{0x431, 0x10001}, {DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd.
{0x303, 0}, /* End of Display timings */
{0x432, 5}, {DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
{0x42F, 0}, {DC_COM_PIN_OUTPUT_ENABLE(1), 0},
{0x42E, 0}, {DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
{0x31, 0}, {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
{0x42, 0x10}, {DC_DISP_DISP_CLOCK_CONTROL, 0},
{0x700, 0}, {DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
{0x42, 0x20}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x42, 0x40}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{0x700, 0}, {DC_WIN_WIN_OPTIONS, 0},
{0x402, 0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{0x32, 0x20}, {DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_STATE_CONTROL, 0x100}, {DC_DISP_DISP_WIN_OPTIONS, 0},
{DC_CMD_STATE_CONTROL, 1}, {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
{0x40, 5}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{0x40A, 0xA0088}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{0x40, 0}, {DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX},
{DC_CMD_STATE_CONTROL, 0x100}, {DC_DISP_FRONT_PORCH, 0xA0088},
{DC_CMD_STATE_CONTROL, 1}, {DC_CMD_STATE_ACCESS, 0},
{0, 0x301}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{0, 0x301}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{DC_CMD_STATE_CONTROL, 0x100}, {DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
{DC_CMD_STATE_CONTROL, 1}, {DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
{0x40, 0}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{0x42E, 4}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{0x430, 8}, {DC_CMD_STATE_ACCESS, 0},
{0x31, 0} {DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)},
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0}
}; };
////Display A config. ////Display A config.
static const cfg_op_t _display_config_12[17] = { static const cfg_op_t _display_config_12[17] = {
{0x40A, 0xA0088}, {DC_DISP_FRONT_PORCH, 0xA0088},
{0x38, 0}, {DC_CMD_INT_MASK, 0},
{0x40, 0}, {DC_CMD_STATE_ACCESS, 0},
{0x39, 0}, {DC_CMD_INT_ENABLE, 0},
{0x28, 0}, {DC_CMD_CONT_SYNCPT_VSYNC, 0},
{0x32, 0}, {DC_CMD_DISPLAY_COMMAND, 0},
{DC_CMD_STATE_CONTROL, 0x100}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{DC_CMD_STATE_CONTROL, 1}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{DC_CMD_STATE_CONTROL, 0x100}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{DC_CMD_STATE_CONTROL, 1}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{0, 0x301}, {DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
{0, 0x301}, {DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
{DC_CMD_STATE_CONTROL, 0x100}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{DC_CMD_STATE_CONTROL, 1}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{0x36, 0}, {DC_CMD_DISPLAY_POWER_CONTROL, 0},
{DC_CMD_STATE_CONTROL, 0x100}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{DC_CMD_STATE_CONTROL, 1} {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
}; };
//DSI config. //DSI config.
static const cfg_op_t _display_config_13[16] = { static const cfg_op_t _display_config_13[16] = {
{DSI_DSI_POWER_CONTROL, 0}, {DSI_POWER_CONTROL, 0},
{0x4F, 0}, {DSI_PAD_CONTROL_1, 0},
{0x3C, 0x6070601}, {DSI_PHY_TIMING_0, 0x6070601},
{0x3D, 0x40A0E05}, {DSI_PHY_TIMING_1, 0x40A0E05},
{0x3E, 0x30109}, {DSI_PHY_TIMING_2, 0x30109},
{0x3F, 0x190A14}, {DSI_BTA_TIMING, 0x190A14},
{0x44, 0x2000FFFF}, {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) },
{0x45, 0x7652000}, {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
{0x46, 0}, {DSI_TO_TALLY, 0},
{0xF, 0x102003}, {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{0x10, 0x31}, {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
{DSI_DSI_POWER_CONTROL, 1}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{0x12, 0x40}, {DSI_MAX_THRESHOLD, 0x40},
{0x13, 0}, {DSI_TRIGGER, 0},
{0x14, 0}, {DSI_TX_CRC, 0},
{0x1A, 0} {DSI_INIT_SEQ_CONTROL, 0}
}; };
//DSI config (if ver == 0x10). //DSI config (if ver == 0x10).
static const cfg_op_t _display_config_14[22] = { static const cfg_op_t _display_config_14[22] = {
{DSI_DSI_WR_DATA, 0x439}, {DSI_WR_DATA, 0x439},
{DSI_DSI_WR_DATA, 0x9483FFB9}, {DSI_WR_DATA, 0x9483FFB9},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0x2139}, {DSI_WR_DATA, 0x2139},
{DSI_DSI_WR_DATA, 0x191919D5}, {DSI_WR_DATA, 0x191919D5},
{DSI_DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19191919},
{DSI_DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19191919},
{DSI_DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19191919},
{DSI_DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19191919},
{DSI_DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19191919},
{DSI_DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19191919},
{DSI_DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19191919},
{DSI_DSI_WR_DATA, 0x19}, {DSI_WR_DATA, 0x19},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0xB39}, {DSI_WR_DATA, 0xB39},
{DSI_DSI_WR_DATA, 0x4F0F41B1}, {DSI_WR_DATA, 0x4F0F41B1},
{DSI_DSI_WR_DATA, 0xF179A433}, {DSI_WR_DATA, 0xF179A433},
{DSI_DSI_WR_DATA, 0x2D81}, {DSI_WR_DATA, 0x2D81},
{DSI_DSI_TRIGGER, 2}, {DSI_TRIGGER, DSI_TRIGGER_HOST},
{DSI_DSI_WR_DATA, 0x439}, {DSI_WR_DATA, 0x439},
{DSI_DSI_WR_DATA, 0xB9}, {DSI_WR_DATA, 0xB9},
{DSI_DSI_TRIGGER, 2} {DSI_TRIGGER, DSI_TRIGGER_HOST}
}; };
//Display A config. //Display A config.
static const cfg_op_t cfg_display_one_color[8] = { static const cfg_op_t cfg_display_one_color[8] = {
{DC_CMD_DISPLAY_WINDOW_HEADER, 0x10}, //Enable window A. {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, 0x20}, //Enable window B. {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, 0x40}, //Enable window C. {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
{DC_CMD_DISPLAY_COMMAND, 0x20} //DISPLAY_CTRL_MODE: continuous display. {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display.
}; };
//Display A config. //Display A config.
static const cfg_op_t cfg_display_framebuffer[32] = { static const cfg_op_t cfg_display_framebuffer[32] = {
{DC_CMD_DISPLAY_WINDOW_HEADER, 0x40}, //Enable window C. {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, 0x20}, //Enable window B. {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, 0x10}, //Enable window A. {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
{DC_X_WIN_XD_COLOR_DEPTH, 0xD}, //T_A8B8G8R8 {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_R8G8B8A8}, //T_A8B8G8R8
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_X_WIN_XD_POSITION, 0}, //(0,0) {DC_WIN_POSITION, 0}, //(0,0)
{DC_X_WIN_XD_H_INITIAL_DDA, 0}, {DC_WIN_H_INITIAL_DDA, 0},
{DC_X_WIN_XD_V_INITIAL_DDA, 0}, {DC_WIN_V_INITIAL_DDA, 0},
{DC_X_WIN_XD_PRESCALED_SIZE, 0x5000B40}, //Pre-scaled size: 1280x2880 bytes (= 0x500 vertical lines x 0xB40 bytes). {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes.
{DC_X_WIN_XD_DDA_INCREMENT, 0x10001000}, {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)},
{DC_X_WIN_XD_SIZE, 0x50002D0}, //Window size: 1280x720 (= 0x500 vertical lines x 0x2D0 horizontal pixels). {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels.
{DC_X_WIN_XD_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. {DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
{0x702, 0}, {DC_WIN_BUFFER_CONTROL, 0},
{DC_X_WINBUF_XD_SURFACE_KIND, 0}, //Regular surface. {DC_WINBUF_SURFACE_KIND, 0}, //Regular surface.
{DC_X_WINBUF_XD_START_ADDR, 0xC0000000}, //Framebuffer address. {DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address.
{DC_X_WINBUF_XD_ADDR_H_OFFSET, 0}, {DC_WINBUF_ADDR_H_OFFSET, 0},
{DC_X_WINBUF_XD_ADDR_V_OFFSET, 0}, {DC_WINBUF_ADDR_V_OFFSET, 0},
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
{DC_X_WIN_XD_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0},
{DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
{DC_X_WIN_XD_WIN_OPTIONS, 0x40000000}, //Enable window AD. {DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD.
{DC_CMD_DISPLAY_COMMAND, 0x20}, //DISPLAY_CTRL_MODE: continuous display. {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display.
{DC_CMD_STATE_CONTROL, 0x300}, //General update; window A update. {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update.
{DC_CMD_STATE_CONTROL, 3} //General activation request; window A activation request. {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request.
}; };