From 795b4ad26ed4cb8229e2e3ea2fd670b1d6a3d9f8 Mon Sep 17 00:00:00 2001
From: CTCaer <ctcaer@gmail.com>
Date: Thu, 6 Apr 2023 17:30:01 +0300
Subject: [PATCH] bdk: sdmmc: increase bw priority to SDMMC1 for L4T

---
 bdk/mem/minerva.c | 18 ++++++++++++++++++
 bdk/mem/minerva.h |  1 +
 2 files changed, 19 insertions(+)

diff --git a/bdk/mem/minerva.c b/bdk/mem/minerva.c
index e4f1130..992882f 100644
--- a/bdk/mem/minerva.c
+++ b/bdk/mem/minerva.c
@@ -27,6 +27,11 @@
 #include <soc/t210.h>
 #include <utils/util.h>
 
+#define LA_REGS_OFFSET_T210    0x1284
+#define LA_REGS_OFFSET_T210B01 0xFA4
+#define LA_SDMMC1_INDEX 6
+#define LA_SDMMC4_INDEX 9
+
 extern volatile nyx_storage_t *nyx_str;
 
 void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
@@ -140,6 +145,15 @@ void minerva_change_freq(minerva_freq_t freq)
 	}
 }
 
+void minerva_sdmmc_la_program(void *table, bool t210b01)
+{
+
+	u32 *la_scale_regs = (u32 *)(table + (t210b01 ? LA_REGS_OFFSET_T210B01 : LA_REGS_OFFSET_T210));
+
+	// Promote SDMMC1 latency allowance to SDMMC4 (SD to eMMC).
+	la_scale_regs[LA_SDMMC1_INDEX] = la_scale_regs[LA_SDMMC4_INDEX];
+}
+
 void minerva_prep_boot_freq()
 {
 	if (!minerva_cfg)
@@ -164,6 +178,10 @@ void minerva_prep_boot_l4t(int oc_freq)
 
 	mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
 
+	// Program SDMMC LA regs.
+	for (u32 i = 0; i < mtc_cfg->table_entries; i++)
+		minerva_sdmmc_la_program(&mtc_cfg->mtc_table[i], false);
+
 	// Add OC frequency.
 	if (oc_freq && mtc_cfg->mtc_table[mtc_cfg->table_entries - 1].rate_khz == FREQ_1600)
 	{
diff --git a/bdk/mem/minerva.h b/bdk/mem/minerva.h
index 9320ecb..9f71e83 100644
--- a/bdk/mem/minerva.h
+++ b/bdk/mem/minerva.h
@@ -61,6 +61,7 @@ typedef enum
 extern void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
 u32  minerva_init();
 void minerva_change_freq(minerva_freq_t freq);
+void minerva_sdmmc_la_program(void *table, bool t210b01);
 void minerva_prep_boot_freq();
 void minerva_prep_boot_l4t(int oc_freq);
 void minerva_periodic_training();