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bdk: sdmmc: refactor defines

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And fix a bug with tuning trim values
This commit is contained in:
CTCaer 2022-05-08 05:21:29 +03:00
parent 4a1cb1f2ea
commit 76d1b4e221
4 changed files with 216 additions and 176 deletions
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5
bdk/storage/mmc.h
View file

@ -408,7 +408,10 @@
/* /*
* BKOPS status level * BKOPS status level
*/ */
#define EXT_CSD_BKOPS_LEVEL_2 0x2 #define EXT_CSD_BKOPS_OK 0x0
#define EXT_CSD_BKOPS_NON_CRITICAL 0x1
#define EXT_CSD_BKOPS_PERF_IMPACTED 0x2
#define EXT_CSD_BKOPS_CRITICAL 0x3
/* /*
* BKOPS modes * BKOPS modes

45
bdk/storage/sdmmc_driver.c
View file

@ -88,9 +88,9 @@ static int _sdmmc_set_io_power(sdmmc_t *sdmmc, u32 power)
u32 sdmmc_get_bus_width(sdmmc_t *sdmmc) u32 sdmmc_get_bus_width(sdmmc_t *sdmmc)
{ {
u32 h = sdmmc->regs->hostctl; u32 h = sdmmc->regs->hostctl;
if (h & SDHCI_CTRL_8BITBUS) if (h & SDHCI_CTRL_8BITBUS) // eMMC only (or UHS-II).
return SDMMC_BUS_WIDTH_8; return SDMMC_BUS_WIDTH_8;
if (h & SDHCI_CTRL_4BITBUS) if (h & SDHCI_CTRL_4BITBUS) // SD only.
return SDMMC_BUS_WIDTH_4; return SDMMC_BUS_WIDTH_4;
return SDMMC_BUS_WIDTH_1; return SDMMC_BUS_WIDTH_1;
} }
@ -102,9 +102,9 @@ void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width)
if (bus_width == SDMMC_BUS_WIDTH_1) if (bus_width == SDMMC_BUS_WIDTH_1)
sdmmc->regs->hostctl = host_control; sdmmc->regs->hostctl = host_control;
else if (bus_width == SDMMC_BUS_WIDTH_4) else if (bus_width == SDMMC_BUS_WIDTH_4)
sdmmc->regs->hostctl = host_control | SDHCI_CTRL_4BITBUS; sdmmc->regs->hostctl = host_control | SDHCI_CTRL_4BITBUS; // SD only.
else if (bus_width == SDMMC_BUS_WIDTH_8) else if (bus_width == SDMMC_BUS_WIDTH_8)
sdmmc->regs->hostctl = host_control | SDHCI_CTRL_8BITBUS; sdmmc->regs->hostctl = host_control | SDHCI_CTRL_8BITBUS; // eMMC only (or UHS-II).
} }
void sdmmc_save_tap_value(sdmmc_t *sdmmc) void sdmmc_save_tap_value(sdmmc_t *sdmmc)
@ -140,9 +140,9 @@ static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type)
return 1; return 1;
} }
static int _sdmmc_commit_changes(sdmmc_t *sdmmc) static void _sdmmc_commit_changes(sdmmc_t *sdmmc)
{ {
return sdmmc->regs->clkcon; (void)sdmmc->regs->clkcon;
} }
static void _sdmmc_pad_config_fallback(sdmmc_t *sdmmc, u32 power) static void _sdmmc_pad_config_fallback(sdmmc_t *sdmmc, u32 power)
@ -330,7 +330,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
case SDHCI_TIMING_MMC_HS52: case SDHCI_TIMING_MMC_HS52:
case SDHCI_TIMING_SD_HS25: case SDHCI_TIMING_SD_HS25:
sdmmc->regs->hostctl |= SDHCI_CTRL_HISPD; sdmmc->regs->hostctl |= SDHCI_CTRL_HISPD; // SD only?
sdmmc->regs->hostctl2 &= ~SDHCI_CTRL_VDD_180; sdmmc->regs->hostctl2 &= ~SDHCI_CTRL_VDD_180;
break; break;
@ -340,23 +340,23 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
case SDHCI_TIMING_UHS_SDR82: case SDHCI_TIMING_UHS_SDR82:
case SDHCI_TIMING_UHS_DDR50: case SDHCI_TIMING_UHS_DDR50:
case SDHCI_TIMING_MMC_HS102: case SDHCI_TIMING_MMC_HS102:
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR104_BUS_SPEED; sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR104_BUS_SPEED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180; sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
break; break;
case SDHCI_TIMING_MMC_HS400: case SDHCI_TIMING_MMC_HS400:
// Non standard. // Non standard.
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | HS400_BUS_SPEED; sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | HS400_BUS_SPEED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180; sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
break; break;
case SDHCI_TIMING_UHS_SDR25: case SDHCI_TIMING_UHS_SDR25:
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR25_BUS_SPEED; sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR25_BUS_SPEED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180; sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
break; break;
case SDHCI_TIMING_UHS_SDR12: case SDHCI_TIMING_UHS_SDR12:
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR12_BUS_SPEED; sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR12_BUS_SPEED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180; sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
break; break;
} }
@ -547,7 +547,7 @@ static int _sdmmc_wait_card_busy(sdmmc_t *sdmmc)
_sdmmc_commit_changes(sdmmc); _sdmmc_commit_changes(sdmmc);
u32 timeout = get_tmr_ms() + 2000; u32 timeout = get_tmr_ms() + 2000;
while (!(sdmmc->regs->prnsts & SDHCI_DATA_0_LVL_MASK)) while (!(sdmmc->regs->prnsts & SDHCI_DATA_0_LVL))
if (get_tmr_ms() > timeout) if (get_tmr_ms() > timeout)
{ {
_sdmmc_reset(sdmmc); _sdmmc_reset(sdmmc);
@ -734,6 +734,7 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc)
sdmmc->regs->hostctl2 &= ~SDHCI_CTRL_PRESET_VAL_EN; sdmmc->regs->hostctl2 &= ~SDHCI_CTRL_PRESET_VAL_EN;
sdmmc->regs->clkcon &= ~SDHCI_PROG_CLOCK_MODE; sdmmc->regs->clkcon &= ~SDHCI_PROG_CLOCK_MODE;
// Enable 32bit addressing if used (sysad. if blkcnt it fallbacks to 16bit).
sdmmc->regs->hostctl2 |= SDHCI_HOST_VERSION_4_EN; sdmmc->regs->hostctl2 |= SDHCI_HOST_VERSION_4_EN;
if (!(sdmmc->regs->capareg & SDHCI_CAN_64BIT)) if (!(sdmmc->regs->capareg & SDHCI_CAN_64BIT))
@ -741,7 +742,7 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc)
sdmmc->regs->hostctl2 |= SDHCI_ADDRESSING_64BIT_EN; sdmmc->regs->hostctl2 |= SDHCI_ADDRESSING_64BIT_EN;
sdmmc->regs->hostctl &= ~SDHCI_CTRL_DMA_MASK; sdmmc->regs->hostctl &= ~SDHCI_CTRL_DMA_MASK;
sdmmc->regs->timeoutcon = (sdmmc->regs->timeoutcon & 0xF0) | 0xE; sdmmc->regs->timeoutcon = (sdmmc->regs->timeoutcon & 0xF0) | 14; // TMCLK * 2^27.
return 1; return 1;
} }
@ -806,7 +807,7 @@ static void _sdmmc_mask_interrupts(sdmmc_t *sdmmc)
sdmmc->regs->norintstsen &= ~(SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); sdmmc->regs->norintstsen &= ~(SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
} }
static int _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask) static u32 _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask)
{ {
u16 norintsts = sdmmc->regs->norintsts; u16 norintsts = sdmmc->regs->norintsts;
u16 errintsts = sdmmc->regs->errintsts; u16 errintsts = sdmmc->regs->errintsts;
@ -841,7 +842,7 @@ static int _sdmmc_wait_response(sdmmc_t *sdmmc)
u32 timeout = get_tmr_ms() + 2000; u32 timeout = get_tmr_ms() + 2000;
while (true) while (true)
{ {
int result = _sdmmc_check_mask_interrupt(sdmmc, NULL, SDHCI_INT_RESPONSE); u32 result = _sdmmc_check_mask_interrupt(sdmmc, NULL, SDHCI_INT_RESPONSE);
if (result == SDMMC_MASKINT_MASKED) if (result == SDMMC_MASKINT_MASKED)
break; break;
if (result != SDMMC_MASKINT_NOERROR || get_tmr_ms() > timeout) if (result != SDMMC_MASKINT_NOERROR || get_tmr_ms() > timeout)
@ -937,7 +938,7 @@ static int _sdmmc_config_dma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req)
// Set mulitblock request. // Set mulitblock request.
if (req->is_multi_block) if (req->is_multi_block)
trnmode = SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_DMA; trnmode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;
// Set request direction. // Set request direction.
if (!req->is_write) if (!req->is_write)
@ -963,13 +964,13 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc)
u32 timeout = get_tmr_ms() + 1500; u32 timeout = get_tmr_ms() + 1500;
do do
{ {
int result = 0; u32 result = SDMMC_MASKINT_MASKED;
while (true) while (true)
{ {
u16 intr = 0; u16 intr = 0;
result = _sdmmc_check_mask_interrupt(sdmmc, &intr, result = _sdmmc_check_mask_interrupt(sdmmc, &intr,
SDHCI_INT_DATA_END | SDHCI_INT_DMA_END); SDHCI_INT_DATA_END | SDHCI_INT_DMA_END);
if (result < 0) if (result != SDMMC_MASKINT_MASKED)
break; break;
if (intr & SDHCI_INT_DATA_END) if (intr & SDHCI_INT_DATA_END)
@ -1186,6 +1187,8 @@ static int _sdmmc_config_sdmmc1(bool t210b01)
_sdmmc_config_sdmmc1_schmitt(); _sdmmc_config_sdmmc1_schmitt();
// Make sure the SDMMC1 controller is powered. // Make sure the SDMMC1 controller is powered.
PMC(APBDEV_PMC_NO_IOPOWER) |= PMC_NO_IOPOWER_SDMMC1_IO_EN;
usleep(1000);
PMC(APBDEV_PMC_NO_IOPOWER) &= ~(PMC_NO_IOPOWER_SDMMC1_IO_EN); PMC(APBDEV_PMC_NO_IOPOWER) &= ~(PMC_NO_IOPOWER_SDMMC1_IO_EN);
(void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write. (void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write.
@ -1194,7 +1197,7 @@ static int _sdmmc_config_sdmmc1(bool t210b01)
(void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write. (void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write.
// Set enable SD card power. // Set enable SD card power.
PINMUX_AUX(PINMUX_AUX_DMIC3_CLK) = PINMUX_PULL_DOWN | 2; // Pull down. PINMUX_AUX(PINMUX_AUX_DMIC3_CLK) = PINMUX_PULL_DOWN | 2;
gpio_config(GPIO_PORT_E, GPIO_PIN_4, GPIO_MODE_GPIO); gpio_config(GPIO_PORT_E, GPIO_PIN_4, GPIO_MODE_GPIO);
gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_HIGH); gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_HIGH);
gpio_output_enable(GPIO_PORT_E, GPIO_PIN_4, GPIO_OUTPUT_ENABLE); gpio_output_enable(GPIO_PORT_E, GPIO_PIN_4, GPIO_OUTPUT_ENABLE);
@ -1252,7 +1255,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p
const u32 trim_values_t210[] = { 2, 8, 3, 8 }; const u32 trim_values_t210[] = { 2, 8, 3, 8 };
const u32 trim_values_t210b01[] = { 14, 13, 15, 13 }; const u32 trim_values_t210b01[] = { 14, 13, 15, 13 };
const u32 *trim_values = sdmmc->t210b01 ? trim_values_t210b01 : trim_values_t210; const u32 *trim_values;
if (id > SDMMC_4 || id == SDMMC_3) if (id > SDMMC_4 || id == SDMMC_3)
return 0; return 0;
@ -1264,6 +1267,8 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p
sdmmc->clock_stopped = 1; sdmmc->clock_stopped = 1;
sdmmc->t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01; sdmmc->t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01;
trim_values = sdmmc->t210b01 ? trim_values_t210b01 : trim_values_t210;
// Do specific SDMMC HW configuration. // Do specific SDMMC HW configuration.
switch (id) switch (id)
{ {

177
bdk/storage/sdmmc_driver.h
View file

@ -22,10 +22,10 @@
#include <storage/sdmmc_t210.h> #include <storage/sdmmc_t210.h>
/*! SDMMC controller IDs. */ /*! SDMMC controller IDs. */
#define SDMMC_1 0 #define SDMMC_1 0 // Version 4.00.
#define SDMMC_2 1 #define SDMMC_2 1 // Version 5.1.
#define SDMMC_3 2 #define SDMMC_3 2 // Version 4.00.
#define SDMMC_4 3 #define SDMMC_4 3 // Version 5.1.
/*! SDMMC power types. */ /*! SDMMC power types. */
#define SDMMC_POWER_OFF 0 #define SDMMC_POWER_OFF 0
@ -47,33 +47,43 @@
/*! SDMMC mask interrupt status. */ /*! SDMMC mask interrupt status. */
#define SDMMC_MASKINT_MASKED 0 #define SDMMC_MASKINT_MASKED 0
#define SDMMC_MASKINT_NOERROR -1 #define SDMMC_MASKINT_NOERROR 1
#define SDMMC_MASKINT_ERROR -2 #define SDMMC_MASKINT_ERROR 2
/*! SDMMC present state. */ /*! SDMMC present state. */
#define SDHCI_CMD_INHIBIT 0x1 #define SDHCI_CMD_INHIBIT BIT(0)
#define SDHCI_DATA_INHIBIT 0x2 #define SDHCI_DATA_INHIBIT BIT(1)
#define SDHCI_DOING_WRITE 0x100 #define SDHCI_DAT_LINE_ACTIVE BIT(2)
#define SDHCI_DOING_READ 0x200 #define SDHCI_RETUNING_REQUEST BIT(3)
#define SDHCI_SPACE_AVAILABLE 0x400 #define SDHCI_EMMC_LINE_LVL_MASK 0xF0
#define SDHCI_DATA_AVAILABLE 0x800 #define SDHCI_DATA_4_LVL BIT(4) // eMMC only.
#define SDHCI_CARD_PRESENT 0x10000 #define SDHCI_DATA_5_LVL BIT(5) // eMMC only.
#define SDHCI_CD_STABLE 0x20000 #define SDHCI_DATA_6_LVL BIT(6) // eMMC only.
#define SDHCI_CD_LVL 0x40000 #define SDHCI_DATA_7_LVL BIT(7) // eMMC only.
#define SDHCI_WRITE_PROTECT 0x80000 #define SDHCI_DOING_WRITE BIT(8)
#define SDHCI_DOING_READ BIT(9) // SD only.
#define SDHCI_SPACE_AVAILABLE BIT(10)
#define SDHCI_DATA_AVAILABLE BIT(11)
#define SDHCI_CARD_PRESENT BIT(16)
#define SDHCI_CD_STABLE BIT(17)
#define SDHCI_CD_LVL BIT(18)
#define SDHCI_WRITE_PROTECT BIT(19)
#define SDHCI_DATA_LVL_MASK 0xF00000 #define SDHCI_DATA_LVL_MASK 0xF00000
#define SDHCI_DATA_0_LVL_MASK 0x100000 #define SDHCI_DATA_0_LVL BIT(20)
#define SDHCI_CMD_LVL 0x1000000 #define SDHCI_DATA_1_LVL BIT(21)
#define SDHCI_DATA_2_LVL BIT(22)
#define SDHCI_DATA_3_LVL BIT(23)
#define SDHCI_CMD_LVL BIT(24)
#define SDHCI_CMD_NOT_ISSUED BIT(27)
/*! SDMMC transfer mode. */ /*! SDMMC transfer mode. */
#define SDHCI_TRNS_DMA 0x01 #define SDHCI_TRNS_DMA BIT(0)
#define SDHCI_TRNS_BLK_CNT_EN 0x02 #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
#define SDHCI_TRNS_AUTO_CMD12 0x04 #define SDHCI_TRNS_AUTO_CMD12 BIT(2)
#define SDHCI_TRNS_AUTO_CMD23 0x08 #define SDHCI_TRNS_AUTO_CMD23 BIT(3)
#define SDHCI_TRNS_AUTO_SEL 0x0C #define SDHCI_TRNS_WRITE 0x00 // Bit4.
#define SDHCI_TRNS_WRITE 0x00 #define SDHCI_TRNS_READ BIT(4)
#define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI BIT(5)
#define SDHCI_TRNS_MULTI 0x20
/*! SDMMC command. */ /*! SDMMC command. */
#define SDHCI_CMD_RESP_MASK 0x3 #define SDHCI_CMD_RESP_MASK 0x3
@ -81,43 +91,43 @@
#define SDHCI_CMD_RESP_LEN136 0x1 #define SDHCI_CMD_RESP_LEN136 0x1
#define SDHCI_CMD_RESP_LEN48 0x2 #define SDHCI_CMD_RESP_LEN48 0x2
#define SDHCI_CMD_RESP_LEN48_BUSY 0x3 #define SDHCI_CMD_RESP_LEN48_BUSY 0x3
#define SDHCI_CMD_CRC 0x08 #define SDHCI_CMD_CRC BIT(3)
#define SDHCI_CMD_INDEX 0x10 #define SDHCI_CMD_INDEX BIT(4)
#define SDHCI_CMD_DATA 0x20 #define SDHCI_CMD_DATA BIT(5)
#define SDHCI_CMD_ABORTCMD 0xC0 #define SDHCI_CMD_ABORTCMD 0xC0
/*! SDMMC host control. */ /*! SDMMC host control. */
#define SDHCI_CTRL_LED 0x01 #define SDHCI_CTRL_LED BIT(0)
#define SDHCI_CTRL_4BITBUS 0x02 #define SDHCI_CTRL_4BITBUS BIT(1) // SD only.
#define SDHCI_CTRL_HISPD 0x04 #define SDHCI_CTRL_HISPD BIT(2) // SD only.
#define SDHCI_CTRL_DMA_MASK 0x18 #define SDHCI_CTRL_DMA_MASK 0x18
#define SDHCI_CTRL_SDMA 0x00 #define SDHCI_CTRL_SDMA 0x00
#define SDHCI_CTRL_ADMA1 0x08 #define SDHCI_CTRL_ADMA1 0x08
#define SDHCI_CTRL_ADMA32 0x10 #define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18 #define SDHCI_CTRL_ADMA64 0x18
#define SDHCI_CTRL_8BITBUS 0x20 #define SDHCI_CTRL_8BITBUS BIT(5) // eMMC only (or UHS-II).
#define SDHCI_CTRL_CDTEST_INS 0x40 #define SDHCI_CTRL_CDTEST_INS BIT(6)
#define SDHCI_CTRL_CDTEST_EN 0x80 #define SDHCI_CTRL_CDTEST_EN BIT(7)
/*! SDMMC host control 2. */ /*! SDMMC host control 2. */
#define SDHCI_CTRL_UHS_MASK 0xFFF8 #define SDHCI_CTRL_UHS_MASK 0x7
#define SDHCI_CTRL_VDD_180 8 #define SDHCI_CTRL_VDD_180 BIT(3)
#define SDHCI_CTRL_DRV_TYPE_B 0x00 #define SDHCI_CTRL_DRV_TYPE_B (0U << 4)
#define SDHCI_CTRL_DRV_TYPE_A 0x10 #define SDHCI_CTRL_DRV_TYPE_A (1U << 4)
#define SDHCI_CTRL_DRV_TYPE_C 0x20 #define SDHCI_CTRL_DRV_TYPE_C (2U << 4)
#define SDHCI_CTRL_DRV_TYPE_D 0x30 #define SDHCI_CTRL_DRV_TYPE_D (3U << 4)
#define SDHCI_CTRL_EXEC_TUNING 0x40 #define SDHCI_CTRL_EXEC_TUNING BIT(6)
#define SDHCI_CTRL_TUNED_CLK 0x80 #define SDHCI_CTRL_TUNED_CLK BIT(7)
#define SDHCI_HOST_VERSION_4_EN 0x1000 #define SDHCI_HOST_VERSION_4_EN BIT(12)
#define SDHCI_ADDRESSING_64BIT_EN 0x2000 #define SDHCI_ADDRESSING_64BIT_EN BIT(13)
#define SDHCI_CTRL_PRESET_VAL_EN 0x8000 #define SDHCI_CTRL_PRESET_VAL_EN BIT(15)
/*! SDMMC power control. */ /*! SDMMC power control. */
#define SDHCI_POWER_ON 0x01 #define SDHCI_POWER_ON BIT(0)
#define SDHCI_POWER_180 0x0A #define SDHCI_POWER_180 0x0A
#define SDHCI_POWER_300 0x0C #define SDHCI_POWER_300 0x0C
#define SDHCI_POWER_330 0x0E #define SDHCI_POWER_330 0x0E
#define SDHCI_POWER_MASK 0xF1 #define SDHCI_POWER_MASK 0xF1 // UHS-II only.
// /*! SDMMC max current. */ // /*! SDMMC max current. */
// #define SDHCI_MAX_CURRENT_330_MASK 0xFF // #define SDHCI_MAX_CURRENT_330_MASK 0xFF
@ -125,45 +135,48 @@
// #define SDHCI_MAX_CURRENT_MULTIPLIER 4 // #define SDHCI_MAX_CURRENT_MULTIPLIER 4
/*! SDMMC clock control. */ /*! SDMMC clock control. */
#define SDHCI_DIVIDER_SHIFT 8 #define SDHCI_CLOCK_INT_EN BIT(0)
#define SDHCI_CLOCK_INT_STABLE BIT(1)
#define SDHCI_CLOCK_CARD_EN BIT(2)
#define SDHCI_PROG_CLOCK_MODE BIT(5)
#define SDHCI_DIVIDER_HI_SHIFT 6 #define SDHCI_DIVIDER_HI_SHIFT 6
#define SDHCI_DIV_MASK 0xFF00 #define SDHCI_DIV_HI_MASK (3U << SDHCI_DIVIDER_HI_SHIFT)
#define SDHCI_DIV_HI_MASK 0xC0 #define SDHCI_DIVIDER_SHIFT 8
#define SDHCI_PROG_CLOCK_MODE 0x20 #define SDHCI_DIV_MASK (0xFFU << SDHCI_DIVIDER_SHIFT)
#define SDHCI_CLOCK_CARD_EN 0x4
#define SDHCI_CLOCK_INT_STABLE 0x2
#define SDHCI_CLOCK_INT_EN 0x1
/*! SDMMC software reset. */ /*! SDMMC software reset. */
#define SDHCI_RESET_ALL 0x01 #define SDHCI_RESET_ALL BIT(0)
#define SDHCI_RESET_CMD 0x02 #define SDHCI_RESET_CMD BIT(1)
#define SDHCI_RESET_DATA 0x04 #define SDHCI_RESET_DATA BIT(2)
/*! SDMMC interrupt status and control. */ /*! SDMMC interrupt status and control. */
#define SDHCI_INT_RESPONSE 0x1 #define SDHCI_INT_RESPONSE BIT(0)
#define SDHCI_INT_DATA_END 0x2 #define SDHCI_INT_DATA_END BIT(1)
#define SDHCI_INT_BLK_GAP 0x4 #define SDHCI_INT_BLK_GAP BIT(2)
#define SDHCI_INT_DMA_END 0x8 #define SDHCI_INT_DMA_END BIT(3)
#define SDHCI_INT_SPACE_AVAIL 0x10 #define SDHCI_INT_SPACE_AVAIL BIT(4)
#define SDHCI_INT_DATA_AVAIL 0x20 #define SDHCI_INT_DATA_AVAIL BIT(5)
#define SDHCI_INT_CARD_INSERT 0x40 #define SDHCI_INT_CARD_INSERT BIT(6)
#define SDHCI_INT_CARD_REMOVE 0x80 #define SDHCI_INT_CARD_REMOVE BIT(7)
#define SDHCI_INT_CARD_INT 0x100 #define SDHCI_INT_CARD_INT BIT(8)
#define SDHCI_INT_RETUNE 0x1000 #define SDHCI_INT_RETUNE BIT(12)
#define SDHCI_INT_CQE 0x4000 #define SDHCI_INT_CQE BIT(14)
#define SDHCI_INT_ERROR 0x8000 #define SDHCI_INT_ERROR BIT(15)
/*! SDMMC error interrupt status and control. */ /*! SDMMC error interrupt status and control. */
#define SDHCI_ERR_INT_TIMEOUT 0x1 #define SDHCI_ERR_INT_TIMEOUT BIT(0)
#define SDHCI_ERR_INT_CRC 0x2 #define SDHCI_ERR_INT_CRC BIT(1)
#define SDHCI_ERR_INT_END_BIT 0x4 #define SDHCI_ERR_INT_END_BIT BIT(2)
#define SDHCI_ERR_INT_INDEX 0x8 #define SDHCI_ERR_INT_INDEX BIT(3)
#define SDHCI_ERR_INT_DATA_TIMEOUT 0x10 #define SDHCI_ERR_INT_DATA_TIMEOUT BIT(4)
#define SDHCI_ERR_INT_DATA_CRC 0x20 #define SDHCI_ERR_INT_DATA_CRC BIT(5)
#define SDHCI_ERR_INT_DATA_END_BIT 0x40 #define SDHCI_ERR_INT_DATA_END_BIT BIT(6)
#define SDHCI_ERR_INT_BUS_POWER 0x80 #define SDHCI_ERR_INT_BUS_POWER BIT(7)
#define SDHCI_ERR_INT_AUTO_CMD_ERR 0x100 #define SDHCI_ERR_INT_AUTO_CMD_ERR BIT(8)
#define SDHCI_ERR_INT_ADMA_ERROR 0x200 #define SDHCI_ERR_INT_ADMA_ERROR BIT(9)
#define SDHCI_ERR_INT_TUNE_ERROR BIT(10)
#define SDHCI_ERR_INT_RSP_ERROR BIT(11)
#define SDHCI_ERR_INT_ALL_EXCEPT_ADMA_BUSPWR \ #define SDHCI_ERR_INT_ALL_EXCEPT_ADMA_BUSPWR \
(SDHCI_ERR_INT_AUTO_CMD_ERR | SDHCI_ERR_INT_DATA_END_BIT | \ (SDHCI_ERR_INT_AUTO_CMD_ERR | SDHCI_ERR_INT_DATA_END_BIT | \
@ -197,7 +210,7 @@
#define SDHCI_TIMING_UHS_DDR50 13 #define SDHCI_TIMING_UHS_DDR50 13
#define SDHCI_TIMING_MMC_HS102 14 #define SDHCI_TIMING_MMC_HS102 14
#define SDHCI_CAN_64BIT 0x10000000 #define SDHCI_CAN_64BIT BIT(28)
/*! SDMMC Low power features. */ /*! SDMMC Low power features. */
#define SDMMC_POWER_SAVE_DISABLE 0 #define SDMMC_POWER_SAVE_DISABLE 0

165
bdk/storage/sdmmc_t210.h
View file

@ -18,6 +18,7 @@
#ifndef _SDMMC_T210_H_ #ifndef _SDMMC_T210_H_
#define _SDMMC_T210_H_ #define _SDMMC_T210_H_
#include <assert.h>
#include <utils/types.h> #include <utils/types.h>
#define TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW 0x20000 #define TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW 0x20000
@ -31,79 +32,97 @@
typedef struct _t210_sdmmc_t typedef struct _t210_sdmmc_t
{ {
vu32 sysad; /* 0x00 */ vu32 sysad; // sdma system address.
vu16 blksize; /* 0x04 */ vu16 blksize;
vu16 blkcnt; /* 0x06 */ vu16 blkcnt;
vu32 argument; /* 0x08 */ vu32 argument;
vu16 trnmod; /* 0x0C */ vu16 trnmod;
vu16 cmdreg; /* 0x0E */ vu16 cmdreg;
vu32 rspreg0; /* 0x10 */ vu32 rspreg0;
vu32 rspreg1; /* 0x14 */ vu32 rspreg1;
vu32 rspreg2; /* 0x18 */ vu32 rspreg2;
vu32 rspreg3; /* 0x1C */ vu32 rspreg3;
vu32 bdata; /* 0x20 */ vu32 bdata; // Buffer data port.
vu32 prnsts; /* 0x24 */ vu32 prnsts;
vu8 hostctl; /* 0x28 */ vu8 hostctl;
vu8 pwrcon; /* 0x29 */ vu8 pwrcon;
vu8 blkgap; /* 0x2A */ vu8 blkgap;
vu8 wakcon; /* 0x2B */ vu8 wakcon;
vu16 clkcon; /* 0x2C */ vu16 clkcon;
vu8 timeoutcon; /* 0x2E */ vu8 timeoutcon;
vu8 swrst; /* 0x2F */ vu8 swrst;
vu16 norintsts; /* 0x30 */ vu16 norintsts; // Normal interrupt status.
vu16 errintsts; /* 0x32 */ vu16 errintsts; // Error interrupt status.
vu16 norintstsen; // Enable irq status. /* 0x34 */ vu16 norintstsen; // Enable irq status.
vu16 errintstsen; // Enable irq status. /* 0x36 */ vu16 errintstsen; // Enable irq status.
vu16 norintsigen; // Enable irq signal to LIC/GIC. /* 0x38 */ vu16 norintsigen; // Enable irq signal to LIC/GIC.
vu16 errintsigen; // Enable irq signal to LIC/GIC. /* 0x3A */ vu16 errintsigen; // Enable irq signal to LIC/GIC.
vu16 acmd12errsts; /* 0x3C */ vu16 acmd12errsts;
vu16 hostctl2; /* 0x3E */ vu16 hostctl2;
vu32 capareg;
vu32 capareg_1; // CAP0: 0x376CD08C.
vu32 maxcurr; // 12 MHz timeout clock. 208 MHz max base clock. 512B max block length. 8-bit support.
vu8 rsvd0[4]; // 4C-4F reserved for more max current. // ADMA2 support. HS25 support. SDMA support. No suspend/resume support. 3.3/3.0/1.8V support.
vu16 setacmd12err; // 64bit addressing for V3/V4 support. Async IRQ support. All report as removable.
vu16 setinterr; /* 0x40 */ vu32 capareg;
vu8 admaerr; // CAP1: 0x10002F73.
vu8 rsvd1[3]; // 55-57 reserved. // SDR50/SDR104 support. No DDR50 support. Drive A/B/C/D support.
vu32 admaaddr; // Timer re-tuning info from other source. SDR50 requires re-tuning.
vu32 admaaddr_hi; // Tuning uses timer and transfers should be 4MB limited.
vu8 rsvd2[156]; // 60-FB reserved. // ADMA3 not supported. 1.8V VDD2 supported.
vu16 slotintsts; /* 0x44 */ vu32 capareg_hi;
vu16 hcver;
vu32 venclkctl; /* 0x48 */ vu32 maxcurr; // Get information by another method. Can be overriden via maxcurrover and maxcurrover_hi.
vu32 vensysswctl; /* 0x4C */ vu8 rsvd0[4]; // 4C-4F reserved for more max current.
vu32 venerrintsts; /* 0x50 */ vu16 setacmd12err;
vu32 vencapover; /* 0x52 */ vu16 setinterr;
vu32 venbootctl; /* 0x54 */ vu8 admaerr;
vu32 venbootacktout; /* 0x55 */ vu8 rsvd1[3]; // 55-57 reserved.
vu32 venbootdattout; /* 0x58 */ vu32 admaaddr;
vu32 vendebouncecnt; /* 0x5C */ vu32 admaaddr_hi;
vu32 venmiscctl; /* 0x60 */ vu16 presets[11];
vu32 maxcurrover; /* 0x76 */ vu16 rsvd2;
vu32 maxcurrover_hi; /* 0x78 */ vu32 adma3addr;
vu32 unk0[32]; // 0x12C /* 0x7C */ vu32 adma3addr_hi;
vu32 veniotrimctl; /* 0x80 */ vu8 uhs2[124]; // 80-FB UHS-II.
vu32 vendllcalcfg; /* 0xFC */ vu16 slotintsts;
vu32 vendllctl0; /* 0xFE */ vu16 hcver; // 0x303 (4.00).
vu32 vendllctl1;
vu32 vendllcalcfgsts; /* UHS-II range. Used for Vendor registers here */
vu32 ventunctl0; /* 0x100 */ vu32 venclkctl;
vu32 ventunctl1; /* 0x104 */ vu32 vensysswctl;
vu32 ventunsts0; /* 0x108 */ vu32 venerrintsts;
vu32 ventunsts1; /* 0x10C */ vu32 vencapover;
vu32 venclkgatehystcnt; /* 0x110 */ vu32 venbootctl;
vu32 venpresetval0; /* 0x114 */ vu32 venbootacktout;
vu32 venpresetval1; /* 0x118 */ vu32 venbootdattout;
vu32 venpresetval2; /* 0x11C */ vu32 vendebouncecnt;
vu32 sdmemcmppadctl; /* 0x120 */ vu32 venmiscctl;
vu32 autocalcfg; /* 0x124 */ vu32 maxcurrover;
vu32 autocalintval; /* 0x128 */ vu32 maxcurrover_hi;
vu32 autocalsts; /* 0x12C */ vu32 unk0[32]; // 0x12C
vu32 iospare; /* 0x1AC */ vu32 veniotrimctl;
vu32 mcciffifoctl; /* 0x1B0 */ vu32 vendllcalcfg;
vu32 timeoutwcoal; /* 0x1B4 */ vu32 vendllctl0;
vu32 unk1; /* 0x1B8 */ vu32 vendllctl1;
/* 0x1BC */ vu32 vendllcalcfgsts;
/* 0x1C0 */ vu32 ventunctl0;
/* 0x1C4 */ vu32 ventunctl1;
/* 0x1C8 */ vu32 ventunsts0;
/* 0x1CC */ vu32 ventunsts1;
/* 0x1D0 */ vu32 venclkgatehystcnt;
/* 0x1D4 */ vu32 venpresetval0;
/* 0x1D8 */ vu32 venpresetval1;
/* 0x1DC */ vu32 venpresetval2;
/* 0x1E0 */ vu32 sdmemcmppadctl;
/* 0x1E4 */ vu32 autocalcfg;
/* 0x1E8 */ vu32 autocalintval;
/* 0x1EC */ vu32 autocalsts;
/* 0x1F0 */ vu32 iospare;
/* 0x1F4 */ vu32 mcciffifoctl;
/* 0x1F8 */ vu32 timeoutwcoal;
} t210_sdmmc_t; } t210_sdmmc_t;
static_assert(sizeof(t210_sdmmc_t) == 0x1FC, "T210 SDMMC REG size is wrong!");
#endif #endif