From 7652d9cdb1f75529292a978937d44ab7c5c5fa97 Mon Sep 17 00:00:00 2001 From: CTCaer Date: Wed, 5 Jun 2024 01:11:04 +0300 Subject: [PATCH] bdk: display: use mipi cal sw war on T210 also As per Nvidia, the pad brick separates clock and data terminations. This necessitates doing the calibration twice. Nvidia/Nintendo probably never updated that part on T210 since it's from around 2015/2016. T210B01 is based on 2017 codebase so it has it. HOS (nvservices, not boot) is probably updated to also do that. If not, then they should fix it. There are 0 known issue reports with that on T210, but well. --- bdk/display/di.c | 26 +++++++++++++++++--------- bdk/display/di.inl | 9 ++++----- 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/bdk/display/di.c b/bdk/display/di.c index 8b60fc7..c1f1e0e 100644 --- a/bdk/display/di.c +++ b/bdk/display/di.c @@ -580,10 +580,15 @@ void display_init() reg_write_array((u32 *)DSI_BASE, _di_dsi_mode_config, ARRAY_SIZE(_di_dsi_mode_config)); usleep(10000); - // Calibrate display communication pads. - const u32 loops = tegra_t210 ? 1 : 2; // Calibrate pads 2 times on T210B01. + /* + * Calibrate display communication pads. + * When switching to the 16ff pad brick, the clock lane termination control + * is separated from data lane termination. This change of the mipi cal + * brings in a bug that the DSI pad clock termination code can't be loaded + * in one time calibration. Trigger calibration twice. + */ reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_pad_cal_config, ARRAY_SIZE(_di_mipi_pad_cal_config)); - for (u32 i = 0; i < loops; i++) + for (u32 i = 0; i < 2; i++) { // Set MIPI bias pad config. MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0x10010; @@ -592,17 +597,20 @@ void display_init() // Set pad trimmers and set MIPI DSI cal offsets. if (tegra_t210) { - reg_write_array((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, ARRAY_SIZE(_di_dsi_pad_cal_config_t210)); - reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210, ARRAY_SIZE(_di_mipi_dsi_cal_offsets_config_t210)); + reg_write_array((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, ARRAY_SIZE(_di_dsi_pad_cal_config_t210)); + reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_prod_config_t210, ARRAY_SIZE(_di_mipi_dsi_cal_prod_config_t210)); } else { - reg_write_array((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210b01, ARRAY_SIZE(_di_dsi_pad_cal_config_t210b01)); - reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210b01, ARRAY_SIZE(_di_mipi_dsi_cal_offsets_config_t210b01)); + reg_write_array((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210b01, ARRAY_SIZE(_di_dsi_pad_cal_config_t210b01)); + reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_prod_config_t210b01, ARRAY_SIZE(_di_mipi_dsi_cal_prod_config_t210b01)); } - // Reset all MIPI cal offsets and start calibration. - reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_start_dsi_cal_config, ARRAY_SIZE(_di_mipi_start_dsi_cal_config)); + // Reset all unused MIPI cal offsets. + reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_unused_config, ARRAY_SIZE(_di_mipi_dsi_cal_unused_config)); + + // Set Prescale/filter and start calibration. + MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_CAL_CTRL)) = 0x2A000001; } usleep(10000); diff --git a/bdk/display/di.inl b/bdk/display/di.inl index aa2e920..415b0d7 100644 --- a/bdk/display/di.inl +++ b/bdk/display/di.inl @@ -252,19 +252,19 @@ static const reg_cfg_t _di_dsi_pad_cal_config_t210b01[] = { }; // MIPI CAL config. -static const reg_cfg_t _di_mipi_dsi_cal_offsets_config_t210[] = { +static const reg_cfg_t _di_mipi_dsi_cal_prod_config_t210[] = { {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200}, {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200}, {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002}, {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002} }; -static const reg_cfg_t _di_mipi_dsi_cal_offsets_config_t210b01[] = { +static const reg_cfg_t _di_mipi_dsi_cal_prod_config_t210b01[] = { {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200006}, {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200006}, {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000}, {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000} }; -static const reg_cfg_t _di_mipi_start_dsi_cal_config[] = { +static const reg_cfg_t _di_mipi_dsi_cal_unused_config[] = { {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, {MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0}, @@ -275,8 +275,7 @@ static const reg_cfg_t _di_mipi_start_dsi_cal_config[] = { {MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0}, {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0}, {MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0}, - {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0}, - {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001} // Set Prescale and filter and start calibration. + {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0} }; // Display A enable config.