diff --git a/bdk/soc/hw_init.c b/bdk/soc/hw_init.c
index b520b01..40b77ff 100644
--- a/bdk/soc/hw_init.c
+++ b/bdk/soc/hw_init.c
@@ -472,14 +472,4 @@ void hw_reinit_workaround(bool coreboot, u32 bl_magic)
 		display_end();
 		clock_disable_host1x();
 	}
-
-	// Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits.
-	if (bl_magic == BL_MAGIC_BROKEN_HWI)
-	{
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_USBD);
-		sdmmc_init(&sd_sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, 0);
-		clock_disable_cl_dvfs();
-
-		msleep(200);
-	}
 }
diff --git a/bdk/soc/hw_init.h b/bdk/soc/hw_init.h
index 06b40ac..aebb021 100644
--- a/bdk/soc/hw_init.h
+++ b/bdk/soc/hw_init.h
@@ -22,7 +22,6 @@
 
 #define BL_MAGIC_CRBOOT_SLD 0x30444C53 // SLD0, seamless display type 0.
 #define BL_MAGIC_L4TLDR_SLD 0x31444C53 // SLD1, seamless display type 1.
-#define BL_MAGIC_BROKEN_HWI 0xBAADF00D // Broken hwinit.
 
 extern u32 hw_rst_status;
 extern u32 hw_rst_reason;