diff --git a/bootloader/config/config.h b/bootloader/config/config.h index c972765..14851a3 100644 --- a/bootloader/config/config.h +++ b/bootloader/config/config.h @@ -33,12 +33,12 @@ typedef struct _hekate_config char *tagline; // Global temporary config. bool se_keygen_done; - u32 sbar_time_keeping; - u32 errors; - int sept_run; - bool rcm_patched; - u32 sd_timeoff; + bool sept_run; bool emummc_force_disable; + bool rcm_patched; + u32 sbar_time_keeping; + u32 sd_timeoff; + u32 errors; } hekate_config; typedef enum diff --git a/bootloader/hos/hos.c b/bootloader/hos/hos.c index 2e05086..c360590 100644 --- a/bootloader/hos/hos.c +++ b/bootloader/hos/hos.c @@ -122,7 +122,7 @@ static void _se_lock(bool lock_se) } memset((void *)IPATCH_BASE, 0, 14 * sizeof(u32)); - SB(SB_CSR) = 0x10; // Protected IROM enable. + SB(SB_CSR) = SB_CSR_PIROM_DISABLE; // This is useful for documenting the bits in the SE config registers, so we can keep it around. /*gfx_printf("SE(SE_SECURITY_0) = %08X\n", SE(SE_SECURITY_0)); @@ -167,7 +167,6 @@ void _pmc_scratch_lock(u32 kb) void _sysctr0_reset() { - SYSCTR0(SYSCTR0_CNTFID0) = 19200000; SYSCTR0(SYSCTR0_CNTCR) = 0; SYSCTR0(SYSCTR0_COUNTERID0) = 0; SYSCTR0(SYSCTR0_COUNTERID1) = 0; @@ -185,7 +184,7 @@ void _sysctr0_reset() int keygen(u8 *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, launch_ctxt_t *hos_ctxt) { - u8 tmp[0x30]; + u8 tmp[0x20]; u32 retries = 0; if (kb > KB_FIRMWARE_VERSION_MAX) @@ -729,7 +728,7 @@ int hos_launch(ini_sec_t *cfg) else cluster_boot_cpu0(ctxt.pkg1_id->secmon_base); while (!secmon_mb->out) - usleep(1); // This only works when in IRAM or with a trained DRAM. + ; // A usleep(1) only works when in IRAM or with a trained DRAM. // Signal pkg2 ready and continue boot. secmon_mb->in = bootStatePkg2Continue; diff --git a/bootloader/main.c b/bootloader/main.c index 3ab5597..2096c31 100644 --- a/bootloader/main.c +++ b/bootloader/main.c @@ -321,12 +321,12 @@ int launch_payload(char *path, bool update) reconfig_hw_workaround(true, 0); } - void (*ext_payload_ptr)() = (void *)EXT_PAYLOAD_ADDR; - void (*update_ptr)() = (void *)RCM_PAYLOAD_ADDR; - // Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. sdmmc_storage_init_wait_sd(); + void (*ext_payload_ptr)() = (void *)EXT_PAYLOAD_ADDR; + void (*update_ptr)() = (void *)RCM_PAYLOAD_ADDR; + // Launch our payload. if (!update) (*ext_payload_ptr)(); diff --git a/bootloader/mem/sdram.c b/bootloader/mem/sdram.c index 96e1792..e9a2219 100644 --- a/bootloader/mem/sdram.c +++ b/bootloader/mem/sdram.c @@ -539,7 +539,7 @@ void sdram_init() const sdram_params_t *params = (const sdram_params_t *)sdram_get_params(); i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, 0x05); - max77620_regulator_set_voltage(REGULATOR_SD1, 1100000); + max77620_regulator_set_voltage(REGULATOR_SD1, 1100000); // Set DRAM voltage. PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel; usleep(params->pmc_vddp_sel_wait); diff --git a/bootloader/power/max77620.h b/bootloader/power/max77620.h index fcce309..479661d 100644 --- a/bootloader/power/max77620.h +++ b/bootloader/power/max77620.h @@ -130,7 +130,7 @@ #define MAX77620_POWER_MODE_DISABLE 0 #define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2) #define MAX77620_LDO_CFG2_ADE_MASK (1 << 1) -#define MAX77620_LDO_CFG2_ADE_DISABLE 0 +#define MAX77620_LDO_CFG2_ADE_DISABLE (0 << 1) #define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1) #define MAX77620_LDO_CFG2_SS_MASK (1 << 0) #define MAX77620_LDO_CFG2_SS_FAST (1 << 0) @@ -153,6 +153,24 @@ #define MAX77620_REG_PUE_GPIO 0x3E #define MAX77620_REG_PDE_GPIO 0x3F #define MAX77620_REG_AME_GPIO 0x40 +#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0) +#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0) +#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN (0 << 0) +#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1) +#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1) +#define MAX77620_CNFG_GPIO_DIR_OUTPUT (0 << 1) +#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW (0 << 3) +#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4) +#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4) +#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5) +#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6) +#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6) +#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6) +#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6) +#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6) #define MAX77620_REG_ONOFFCNFG1 0x41 #define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7) @@ -259,25 +277,6 @@ #define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0 #define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0 -#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1) -#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1) -#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0 -#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0 -#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4) -#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4) -#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5) -#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6) -#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6) -#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6) -#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6) -#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6) - #define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0) #define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1) #define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2) diff --git a/bootloader/power/max7762x.h b/bootloader/power/max7762x.h index 2a146c7..3a0afe3 100644 --- a/bootloader/power/max7762x.h +++ b/bootloader/power/max7762x.h @@ -24,16 +24,16 @@ * Switch Power domains (max77620): * Name | Usage | uV step | uV min | uV default | uV max | Init *-------+---------------+---------+--------+------------+---------+------------------ -* sd0 | core | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1) +* sd0 | SoC | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1) * sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1) * sd2 | ldo{0-1, 7-8} | 12500 | 600000 | 1325000 | 1350000 | 1.325V (pcv) * sd3 | 1.8V general | 12500 | 600000 | 1800000 | 1800000 | * ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1) * ldo1 | XUSB, PCIE | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv) * ldo2 | SDMMC1 | 50000 | 800000 | 1800000 | 3300000 | -* ldo3 | GC ASIC | 50000 | 800000 | 3100000 | 3100000 | 3.1V (pcv) +* ldo3 | GC ASIC | 50000 | 800000 | 3100000 | 3100000 | 3.1V (pcv) * ldo4 | RTC | 12500 | 800000 | 850000 | 850000 | -* ldo5 | GC ASIC | 50000 | 800000 | 1800000 | 1800000 | 1.8V (pcv) +* ldo5 | GC ASIC | 50000 | 800000 | 1800000 | 1800000 | 1.8V (pcv) * ldo6 | Touch, ALS | 50000 | 800000 | 2900000 | 2900000 | 2.9V * ldo7 | XUSB | 50000 | 800000 | 1050000 | 1050000 | * ldo8 | XUSB, DC | 50000 | 800000 | 1050000 | 1050000 | diff --git a/bootloader/soc/bpmp.c b/bootloader/soc/bpmp.c index cc20d89..a142b8e 100644 --- a/bootloader/soc/bpmp.c +++ b/bootloader/soc/bpmp.c @@ -179,39 +179,36 @@ void bpmp_clk_rate_set(bpmp_freq_t fid) if (bpmp_clock_set) { // Restore to PLLP source during PLLC4 configuration. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = - (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; // PLLP_OUT. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // PLLP_OUT. // Wait a bit for clock source change. msleep(10); } - CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = (1 << 30); - CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = 4 | (pllc4_divn[fid] << 8) | (1 << 30); // DIVM: 4, DIVP: 1. + CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = PLLC4_MISC_EN_LCKDET; + CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = 4 | (pllc4_divn[fid] << 8) | PLL_BASE_ENABLE; // DIVM: 4, DIVP: 1. - while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & (1 << 27))) + while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & PLLC4_BASE_LOCK)) ; - CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) = (1 << 8) | (1 << 1); // 1.5 div. - CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) |= 1; // Get divider out of reset. + CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) = (1 << 8) | PLLC4_OUT3_CLKEN; // 1.5 div. + CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) |= PLLC4_OUT3_RSTN_CLR; // Get divider out of reset. // Wait a bit for PLLC4 to stabilize. msleep(10); CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / 4. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = - (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3323; // PLLC4_OUT3. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003323; // PLLC4_OUT3. bpmp_clock_set = fid; } else { - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = - (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; // PLLP_OUT. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // PLLP_OUT. // Wait a bit for clock source change. msleep(10); CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / 3. - CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~(1<<30); + CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLL_BASE_ENABLE; bpmp_clock_set = BPMP_CLK_NORMAL; } } diff --git a/bootloader/soc/clock.c b/bootloader/soc/clock.c index 12776eb..7e824b5 100644 --- a/bootloader/soc/clock.c +++ b/bootloader/soc/clock.c @@ -22,58 +22,58 @@ /* clock_t: reset, enable, source, index, clk_src, clk_div */ static const clock_t _clock_uart[] = { -/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 0 }, -/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 0 }, -/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 0x17, 0, 0 }, -/* UART D */ { 0 }, -/* UART E */ { 0 } +/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 2 }, +/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 2 }, +/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 23, 0, 2 }, +/* UART D */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD, 1, 0, 2 }, +/* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 } }; static const clock_t _clock_i2c[] = { -/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 0xC, 6, 0 }, // 0, 19 }, // 100KHz +/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 6, 0 }, // 0, 19 }, // 100KHz /* I2C2 */ { 0 }, /* I2C3 */ { 0 }, /* I2C4 */ { 0 }, -/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 6, 0 }, // 0, 4 }, // 400KHz +/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 15, 6, 0 }, // 0, 4 }, // 400KHz /* I2C6 */ { 0 } }; static clock_t _clock_se = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 0x1F, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 31, 0, 0 }; static clock_t _clock_tzram = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, 0x1E, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, 30, 0, 0 }; static clock_t _clock_host1x = { - CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3 + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 28, 4, 3 }; static clock_t _clock_tsec = { - CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2 + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 19, 0, 2 }; static clock_t _clock_sor_safe = { - CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, 0x1E, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, 30, 0, 0 }; static clock_t _clock_sor0 = { - CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, 0x16, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, 22, 0, 0 }; static clock_t _clock_sor1 = { - CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 0x17, 0, 2 + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 23, 0, 2 }; static clock_t _clock_kfuse = { - CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, 8, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, 8, 0, 0 }; static clock_t _clock_cl_dvfs = { - CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, 0x1B, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, 27, 0, 0 }; static clock_t _clock_coresight = { - CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4 + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4 }; static clock_t _clock_pwm = { - CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 0x11, 6, 4 + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Freference: 6.2MHz. }; void clock_enable(const clock_t *clk) @@ -372,43 +372,44 @@ static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val) u32 divisor = 0; u32 source = PLLP_OUT0; + // Get IO clock divisor. switch (val) { case 25000: *pout = 24728; - divisor = 31; + divisor = 31; // 16.5 div. break; case 26000: *pout = 25500; - divisor = 30; + divisor = 30; // 16 div. break; case 40800: *pout = 40800; - divisor = 18; + divisor = 18; // 10 div. break; case 50000: *pout = 48000; - divisor = 15; + divisor = 15; // 8.5 div. break; case 52000: *pout = 51000; - divisor = 14; + divisor = 14; // 8 div. break; case 100000: *pout = 90667; - divisor = 7; + divisor = 7; // 4.5 div. break; case 200000: *pout = 163200; - divisor = 3; + divisor = 3; // 2.5 div. break; case 208000: *pout = 204000; - divisor = 2; + divisor = 2; // 2 div. break; default: *pout = 24728; - divisor = 31; + divisor = 31; // 16.5 div. } _clock_sdmmc_table[2 * id] = val; diff --git a/bootloader/soc/clock.h b/bootloader/soc/clock.h index e7891b5..754608f 100644 --- a/bootloader/soc/clock.h +++ b/bootloader/soc/clock.h @@ -41,6 +41,8 @@ #define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C #define CLK_RST_CONTROLLER_PLLP_BASE 0xA0 #define CLK_RST_CONTROLLER_PLLD_BASE 0xD0 +#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8 +#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC #define CLK_RST_CONTROLLER_PLLX_BASE 0xE0 #define CLK_RST_CONTROLLER_PLLX_MISC 0xE4 #define CLK_RST_CONTROLLER_PLLE_BASE 0xE8 @@ -50,6 +52,7 @@ #define CLK_RST_CONTROLLER_CLK_SOURCE_PWM 0x110 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128 +#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138 #define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154 @@ -57,11 +60,13 @@ #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178 #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C #define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180 +#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 0x198 +#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 0x1B8 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC +#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD 0x1C0 #define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4 -#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C #define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280 #define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284 @@ -95,9 +100,12 @@ #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0 #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4 #define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4 +#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4 +#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400 #define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410 #define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C #define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440 +#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444 #define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448 #define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C #define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450 @@ -113,14 +121,25 @@ #define CLK_RST_CONTROLLER_PLLC4_OUT 0x5E4 #define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8 #define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620 +#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 0x65C #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664 #define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL 0x66C #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694 #define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0 #define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704 +#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710 #define CLK_NO_SOURCE 0x0 +/*! PLL control and status bits */ +#define PLL_BASE_ENABLE (1 << 30) + +#define PLLC4_MISC_EN_LCKDET (1 << 30) +#define PLLC4_BASE_LOCK (1 << 27) +#define PLLC4_BASE_IDDQ (1 << 18) +#define PLLC4_OUT3_CLKEN (1 << 1) +#define PLLC4_OUT3_RSTN_CLR (1 << 0) + /*! Generic clock descriptor. */ typedef struct _clock_t { diff --git a/bootloader/soc/cluster.c b/bootloader/soc/cluster.c index 0d00129..c12c4c0 100644 --- a/bootloader/soc/cluster.c +++ b/bootloader/soc/cluster.c @@ -117,10 +117,10 @@ void cluster_boot_cpu0(u32 entry) EXCP_VEC(EVP_CPU_RESET_VECTOR) = 0; // Set reset vector. - SB(SB_AA64_RESET_LOW) = entry | 1; + SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN; SB(SB_AA64_RESET_HIGH) = 0; // Non-secure reset vector write disable. - SB(SB_CSR) = 2; + SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS; (void)SB(SB_CSR); // Clear MSELECT reset. diff --git a/bootloader/soc/hw_init.c b/bootloader/soc/hw_init.c index a27d5a6..5ae20d3 100644 --- a/bootloader/soc/hw_init.c +++ b/bootloader/soc/hw_init.c @@ -41,22 +41,36 @@ extern sdmmc_t sd_sdmmc; extern boot_cfg_t b_cfg; +/* + * CLK_OSC - 38.4 MHz crystal. + * CLK_M - 19.2 MHz (osc/2). + * CLK_S - 32.768 KHz (from PMIC). + * SCLK - 204MHz init (-> 408MHz -> OC). + * HCLK - 204MHz init (-> 408MHz -> OC). + * PCLK - 68MHz init (-> 136MHz -> OC/4). + */ + void _config_oscillators() { - CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; - SYSCTR0(SYSCTR0_CNTFID0) = 19200000; + CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2. + SYSCTR0(SYSCTR0_CNTFID0) = 19200000; // Set counter frequency. TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m. - CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; - PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; - PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | 0x400000; - PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | 0x1000; - PMC(APBDEV_PMC_SCRATCH188) = (PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF) | 0x2000000; - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; - CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; + CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; // Set OSC to 38.4MHz and drive strength. + + PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; // Set LP0 OSC drive strength. + PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | PMC_OSC_EDPD_OVER_OSC_CTRL_OVER; + PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN; + PMC(APBDEV_PMC_SCRATCH188) = (PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF) | (4 << 23); // LP0 EMC2TMC_CFG_XM2COMP_PU_VREF_SEL_RANGE. + + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable. + PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz) - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; - CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; + + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set SCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set clk source to Run and PLLP_OUT2 (204MHz). + CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1. + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3. } void _config_gpios() @@ -89,13 +103,17 @@ void _config_gpios() gpio_config(GPIO_PORT_X, GPIO_PIN_7, GPIO_MODE_GPIO); gpio_output_enable(GPIO_PORT_X, GPIO_PIN_6, GPIO_OUTPUT_DISABLE); gpio_output_enable(GPIO_PORT_X, GPIO_PIN_7, GPIO_OUTPUT_DISABLE); + + // Configure HOME as inputs. + // PINMUX_AUX(PINMUX_AUX_BUTTON_HOME) = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE; + // gpio_config(GPIO_PORT_Y, GPIO_PIN_1, GPIO_MODE_GPIO); } void _config_pmc_scratch() { - PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; - PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; - PMC(APBDEV_PMC_SECURE_SCRATCH21) |= 0x10; + PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option. + PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL + PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT; } void _mbist_workaround() @@ -104,7 +122,7 @@ void _mbist_workaround() CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) | 0x8000) & 0xFFFFBFFF; - CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000u; + CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000; CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40; CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000; CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; @@ -120,7 +138,7 @@ void _mbist_workaround() I2S(I2S4_CG) &= ~I2S_CG_SLCG_ENABLE; I2S(I2S5_CTRL) |= I2S_CTRL_MASTER_EN; I2S(I2S5_CG) &= ~I2S_CG_SLCG_ENABLE; - DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4; + DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4; // DSC_SLCG_OVERRIDE. VIC(0x8C) = 0xFFFFFFFF; usleep(2); @@ -184,8 +202,8 @@ void config_hw() // Bootrom stuff we skipped by going through rcm. _config_se_brom(); //FUSE(FUSE_PRIVATEKEYDISABLE) = 0x11; - SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F; - PMC(APBDEV_PMC_SCRATCH49) = ((PMC(APBDEV_PMC_SCRATCH49) >> 1) << 1) & 0xFFFFFFFD; + SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F; // Unset APB2JTAG_OVERRIDE_EN and OBS_OVERRIDE_EN. + PMC(APBDEV_PMC_SCRATCH49) = PMC(APBDEV_PMC_SCRATCH49) & 0xFFFFFFFC; _mbist_workaround(); clock_enable_se(); @@ -258,7 +276,7 @@ void config_hw() _config_pmc_scratch(); // Missing from 4.x+ - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz). sdram_init(); diff --git a/bootloader/soc/pinmux.h b/bootloader/soc/pinmux.h index b9433a7..2db4a75 100644 --- a/bootloader/soc/pinmux.h +++ b/bootloader/soc/pinmux.h @@ -40,19 +40,32 @@ #define PINMUX_AUX_SDMMC3_DAT3 0x30 #define PINMUX_AUX_SATA_LED_ACTIVE 0x4C #define PINMUX_AUX_DMIC3_CLK 0xB4 +#define PINMUX_AUX_DMIC3_DAT 0xB8 +#define PINMUX_AUX_CAM_I2C_SCL 0xD4 +#define PINMUX_AUX_CAM_I2C_SDA 0xD8 #define PINMUX_AUX_UART2_TX 0xF4 #define PINMUX_AUX_UART3_TX 0x104 +#define PINMUX_AUX_DAP4_DIN 0x148 +#define PINMUX_AUX_DAP4_SCLK 0x150 +#define PINMUX_AUX_GPIO_X1_AUD 0x18C +#define PINMUX_AUX_GPIO_X3_AUD 0x190 #define PINMUX_AUX_SPDIF_IN 0x1A4 #define PINMUX_AUX_USB_VBUS_EN0 0x1A8 +#define PINMUX_AUX_USB_VBUS_EN1 0x1AC #define PINMUX_AUX_WIFI_EN 0x1B4 #define PINMUX_AUX_WIFI_RST 0x1B8 +#define PINMUX_AUX_AP_WAKE_NFC 0x1CC #define PINMUX_AUX_NFC_EN 0x1D0 #define PINMUX_AUX_NFC_INT 0x1D4 #define PINMUX_AUX_CAM1_PWDN 0x1EC +#define PINMUX_AUX_CAM2_PWDN 0x1F0 #define PINMUX_AUX_LCD_BL_PWM 0x1FC #define PINMUX_AUX_LCD_BL_EN 0x200 #define PINMUX_AUX_LCD_RST 0x204 #define PINMUX_AUX_LCD_GPIO2 0x20C +#define PINMUX_AUX_TOUCH_INT 0x220 +#define PINMUX_AUX_MOTION_INT 0x224 +#define PINMUX_AUX_BUTTON_HOME 0x240 #define PINMUX_AUX_GPIO_PE6 0x248 #define PINMUX_AUX_GPIO_PH6 0x250 #define PINMUX_AUX_GPIO_PK3 0x260 diff --git a/bootloader/soc/pmc.h b/bootloader/soc/pmc.h index ec8eb99..8cd9161 100644 --- a/bootloader/soc/pmc.h +++ b/bootloader/soc/pmc.h @@ -25,6 +25,7 @@ #define APBDEV_PMC_PWRGATE_TOGGLE 0x30 #define APBDEV_PMC_PWRGATE_STATUS 0x38 #define APBDEV_PMC_NO_IOPOWER 0x44 +#define PMC_NO_IOPOWER_SDMMC1_IO_EN (1 << 12) #define APBDEV_PMC_SCRATCH0 0x50 #define APBDEV_PMC_SCRATCH1 0x54 #define APBDEV_PMC_SCRATCH20 0xA0 @@ -37,6 +38,7 @@ #define APBDEV_PMC_SCRATCH33 0x120 #define APBDEV_PMC_SCRATCH40 0x13C #define APBDEV_PMC_OSC_EDPD_OVER 0x1A4 +#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000 #define APBDEV_PMC_RST_STATUS 0x1B4 #define APBDEV_PMC_IO_DPD_REQ 0x1B8 #define APBDEV_PMC_IO_DPD2_REQ 0x1C0 @@ -51,9 +53,11 @@ #define APBDEV_PMC_REG_SHORT 0x2CC #define APBDEV_PMC_SEC_DISABLE3 0x2D8 #define APBDEV_PMC_SECURE_SCRATCH21 0x334 +#define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT 0x10 #define APBDEV_PMC_SECURE_SCRATCH32 0x360 #define APBDEV_PMC_SECURE_SCRATCH49 0x3A4 #define APBDEV_PMC_CNTRL2 0x440 +#define PMC_CNTRL2_HOLD_CKE_LOW_EN 0x1000 #define APBDEV_PMC_IO_DPD3_REQ 0x45C #define APBDEV_PMC_IO_DPD4_REQ 0x464 #define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4 diff --git a/bootloader/soc/t210.h b/bootloader/soc/t210.h index d5a526b..5d372a8 100644 --- a/bootloader/soc/t210.h +++ b/bootloader/soc/t210.h @@ -107,9 +107,11 @@ /*! Misc registers. */ #define APB_MISC_PP_STRAPPING_OPT_A 0x08 #define APB_MISC_PP_PINMUX_GLOBAL 0x40 +#define APB_MISC_GP_HIDREV 0x804 #define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34 #define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98 #define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4 +#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC #define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64 #define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68 @@ -119,7 +121,10 @@ /*! Secure boot registers. */ #define SB_CSR 0x0 +#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) +#define SB_CSR_PIROM_DISABLE (1 << 4) #define SB_AA64_RESET_LOW 0x30 +#define SB_AA64_RST_AARCH64_MODE_EN (1 << 0) #define SB_AA64_RESET_HIGH 0x34 /*! SOR registers. */ @@ -183,6 +188,7 @@ /*! PWM registers. */ #define PWM_CONTROLLER_PWM_CSR_0 0x00 #define PWM_CONTROLLER_PWM_CSR_1 0x10 +#define PWM_CSR_EN (1 << 31) /*! Special registers. */ #define EMC_SCRATCH0 0x324 diff --git a/bootloader/soc/uart.h b/bootloader/soc/uart.h index 78f3c15..808232d 100644 --- a/bootloader/soc/uart.h +++ b/bootloader/soc/uart.h @@ -22,9 +22,8 @@ #define UART_A 0 #define UART_B 1 #define UART_C 2 -//TODO: define clock inits for those. -/*#define UART_D 3 -#define UART_E 4*/ +#define UART_D 3 +#define UART_E 4 #define BAUD_115200 115200 @@ -34,15 +33,29 @@ #define UART_TX_FIFO_FULL 0x100 #define UART_RX_FIFO_EMPTY 0x200 +#define UART_INVERT_RXD 0x01 +#define UART_INVERT_TXD 0x02 +#define UART_INVERT_CTS 0x04 +#define UART_INVERT_RTS 0x08 + +#define UART_IER_DLAB_IE_EORD 0x20 + #define UART_LCR_DLAB 0x80 +#define UART_LCR_STOP 0x4 #define UART_LCR_WORD_LENGTH_8 0x3 + #define UART_LSR_RDR 0x1 #define UART_LSR_THRE 0x20 #define UART_LSR_TMTY 0x40 +#define UART_LSR_FIFOE 0x80 + #define UART_IIR_FCR_TX_CLR 0x4 #define UART_IIR_FCR_RX_CLR 0x2 #define UART_IIR_FCR_EN_FIFO 0x1 +#define UART_MCR_RTS 0x2 +#define UART_MCR_DTR 0x1 + typedef struct _uart_t { /* 0x00 */ vu32 UART_THR_DLAB; diff --git a/bootloader/storage/emummc.h b/bootloader/storage/emummc.h index 437d3ed..0804ea6 100644 --- a/bootloader/storage/emummc.h +++ b/bootloader/storage/emummc.h @@ -35,7 +35,7 @@ typedef enum { typedef struct _emummc_cfg_t { - int enabled; + int enabled; u64 sector; u16 id; char *path; diff --git a/bootloader/storage/mmc.h b/bootloader/storage/mmc.h index dddb956..0d87e35 100644 --- a/bootloader/storage/mmc.h +++ b/bootloader/storage/mmc.h @@ -31,7 +31,7 @@ #define MMC_ALL_SEND_CID 2 /* bcr R2 */ #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ #define MMC_SET_DSR 4 /* bc [31:16] RCA */ -#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ +#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ #define MMC_SWITCH 6 /* ac [31:0] See below R1b */ #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ #define MMC_SEND_EXT_CSD 8 /* adtc R1 */ @@ -51,7 +51,7 @@ #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */ -#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ +#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ /* class 3 */ #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ diff --git a/nyx/nyx_gui/config/config.c b/nyx/nyx_gui/config/config.c index 210f062..152295d 100644 --- a/nyx/nyx_gui/config/config.c +++ b/nyx/nyx_gui/config/config.c @@ -44,11 +44,14 @@ void set_default_configuration() h_cfg.sbar_time_keeping = 0; h_cfg.backlight = 100; h_cfg.autohosoff = 0; - h_cfg.errors = 0; h_cfg.autonogc = 1; + h_cfg.brand = NULL; + h_cfg.tagline = NULL; + h_cfg.errors = 0; h_cfg.sept_run = EMC(EMC_SCRATCH0) & EMC_SEPT_RUN; h_cfg.rcm_patched = fuse_check_patched_rcm(); h_cfg.sd_timeoff = 0; + h_cfg.emummc_force_disable = false; } int create_config_entry() diff --git a/nyx/nyx_gui/config/config.h b/nyx/nyx_gui/config/config.h index a0719c4..f588eeb 100644 --- a/nyx/nyx_gui/config/config.h +++ b/nyx/nyx_gui/config/config.h @@ -33,12 +33,12 @@ typedef struct _hekate_config char *tagline; // Global temporary config. bool se_keygen_done; - u32 sbar_time_keeping; - u32 errors; - int sept_run; - bool rcm_patched; - u32 sd_timeoff; + bool sept_run; bool emummc_force_disable; + bool rcm_patched; + u32 sbar_time_keeping; + u32 sd_timeoff; + u32 errors; } hekate_config; typedef enum diff --git a/nyx/nyx_gui/hos/hos.c b/nyx/nyx_gui/hos/hos.c index 9166e4d..f01de85 100644 --- a/nyx/nyx_gui/hos/hos.c +++ b/nyx/nyx_gui/hos/hos.c @@ -126,7 +126,10 @@ int keygen(u8 *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt) // We rely on racing conditions, make sure we cover even the unluckiest cases. if (retries > 15) + { + EPRINTF("\nFailed to get TSEC keys. Please try again.\n"); return 0; + } } } diff --git a/nyx/nyx_gui/hos/hos.h b/nyx/nyx_gui/hos/hos.h index 3a4fe2f..f0c8501 100644 --- a/nyx/nyx_gui/hos/hos.h +++ b/nyx/nyx_gui/hos/hos.h @@ -61,6 +61,8 @@ typedef struct _launch_ctxt_t bool debugmode; bool stock; bool atmosphere; + bool exo_no_user_exceptions; + bool emuMMC; ini_sec_t *cfg; } launch_ctxt_t; diff --git a/nyx/nyx_gui/input/touch.c b/nyx/nyx_gui/input/touch.c index a3f7540..5d2d22e 100644 --- a/nyx/nyx_gui/input/touch.c +++ b/nyx/nyx_gui/input/touch.c @@ -93,7 +93,7 @@ static void _touch_parse_event(touch_event *event) } // gfx_con_setpos(&gfx_con, 0, 300); - // DPRINTF("x = %d \ny = %d \nz: %d \n", event->x, event->y, event->z); + // DPRINTF("x = %d \ny = %d \nz = %d \n", event->x, event->y, event->z); // DPRINTF("0 = %02X\n1 = %02x\n2 = %02x\n3 = %02x\n", event->raw[0], event->raw[1], event->raw[2], event->raw[3]); // DPRINTF("4 = %02X\n5 = %02x\n6 = %02x\n7 = %02x\n", event->raw[4], event->raw[5], event->raw[6], event->raw[7]); } diff --git a/nyx/nyx_gui/input/touch.h b/nyx/nyx_gui/input/touch.h index 7816a71..f38d41e 100644 --- a/nyx/nyx_gui/input/touch.h +++ b/nyx/nyx_gui/input/touch.h @@ -70,6 +70,8 @@ #define STMFTS_EV_HOVER_MOTION 0x09 #define STMFTS_EV_KEY_STATUS 0x0e #define STMFTS_EV_ERROR 0x0f +#define STMFTS_EV_NOISE_READ 0x17 +#define STMFTS_EV_NOISE_WRITE 0x18 #define STMFTS_EV_CONTROLLER_READY 0x10 #define STMFTS_EV_SLEEP_OUT_CONTROLLER_READY 0x11 diff --git a/nyx/nyx_gui/mem/sdram.c b/nyx/nyx_gui/mem/sdram.c index b809d08..27ef83a 100644 --- a/nyx/nyx_gui/mem/sdram.c +++ b/nyx/nyx_gui/mem/sdram.c @@ -549,7 +549,7 @@ void sdram_init() const sdram_params_t *params = (const sdram_params_t *)sdram_get_params(); i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, 0x05); - max77620_regulator_set_voltage(REGULATOR_SD1, 1100000); + max77620_regulator_set_voltage(REGULATOR_SD1, 1100000); // Set DRAM voltage. PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel; usleep(params->pmc_vddp_sel_wait); diff --git a/nyx/nyx_gui/power/max77620.h b/nyx/nyx_gui/power/max77620.h index fcce309..479661d 100644 --- a/nyx/nyx_gui/power/max77620.h +++ b/nyx/nyx_gui/power/max77620.h @@ -130,7 +130,7 @@ #define MAX77620_POWER_MODE_DISABLE 0 #define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2) #define MAX77620_LDO_CFG2_ADE_MASK (1 << 1) -#define MAX77620_LDO_CFG2_ADE_DISABLE 0 +#define MAX77620_LDO_CFG2_ADE_DISABLE (0 << 1) #define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1) #define MAX77620_LDO_CFG2_SS_MASK (1 << 0) #define MAX77620_LDO_CFG2_SS_FAST (1 << 0) @@ -153,6 +153,24 @@ #define MAX77620_REG_PUE_GPIO 0x3E #define MAX77620_REG_PDE_GPIO 0x3F #define MAX77620_REG_AME_GPIO 0x40 +#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0) +#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0) +#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN (0 << 0) +#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1) +#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1) +#define MAX77620_CNFG_GPIO_DIR_OUTPUT (0 << 1) +#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW (0 << 3) +#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4) +#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4) +#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5) +#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6) +#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6) +#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6) +#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6) +#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6) #define MAX77620_REG_ONOFFCNFG1 0x41 #define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7) @@ -259,25 +277,6 @@ #define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0 #define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0 -#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1) -#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1) -#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0 -#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0 -#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4) -#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4) -#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5) -#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6) -#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6) -#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6) -#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6) -#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6) - #define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0) #define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1) #define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2) diff --git a/nyx/nyx_gui/power/max7762x.h b/nyx/nyx_gui/power/max7762x.h index 2a146c7..3a0afe3 100644 --- a/nyx/nyx_gui/power/max7762x.h +++ b/nyx/nyx_gui/power/max7762x.h @@ -24,16 +24,16 @@ * Switch Power domains (max77620): * Name | Usage | uV step | uV min | uV default | uV max | Init *-------+---------------+---------+--------+------------+---------+------------------ -* sd0 | core | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1) +* sd0 | SoC | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1) * sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1) * sd2 | ldo{0-1, 7-8} | 12500 | 600000 | 1325000 | 1350000 | 1.325V (pcv) * sd3 | 1.8V general | 12500 | 600000 | 1800000 | 1800000 | * ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1) * ldo1 | XUSB, PCIE | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv) * ldo2 | SDMMC1 | 50000 | 800000 | 1800000 | 3300000 | -* ldo3 | GC ASIC | 50000 | 800000 | 3100000 | 3100000 | 3.1V (pcv) +* ldo3 | GC ASIC | 50000 | 800000 | 3100000 | 3100000 | 3.1V (pcv) * ldo4 | RTC | 12500 | 800000 | 850000 | 850000 | -* ldo5 | GC ASIC | 50000 | 800000 | 1800000 | 1800000 | 1.8V (pcv) +* ldo5 | GC ASIC | 50000 | 800000 | 1800000 | 1800000 | 1.8V (pcv) * ldo6 | Touch, ALS | 50000 | 800000 | 2900000 | 2900000 | 2.9V * ldo7 | XUSB | 50000 | 800000 | 1050000 | 1050000 | * ldo8 | XUSB, DC | 50000 | 800000 | 1050000 | 1050000 | diff --git a/nyx/nyx_gui/soc/bpmp.c b/nyx/nyx_gui/soc/bpmp.c index 45a4a0c..16367f2 100644 --- a/nyx/nyx_gui/soc/bpmp.c +++ b/nyx/nyx_gui/soc/bpmp.c @@ -182,39 +182,36 @@ void bpmp_clk_rate_set(bpmp_freq_t fid) if (bpmp_clock_set) { // Restore to PLLP source during PLLC4 configuration. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = - (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; // PLLP_OUT. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // PLLP_OUT. // Wait a bit for clock source change. msleep(10); } - CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = (1 << 30); - CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = 4 | (pllc4_divn[fid] << 8) | (1 << 30); // DIVM: 4, DIVP: 1. + CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = PLLC4_MISC_EN_LCKDET; + CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = 4 | (pllc4_divn[fid] << 8) | PLL_BASE_ENABLE; // DIVM: 4, DIVP: 1. - while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & (1 << 27))) + while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & PLLC4_BASE_LOCK)) ; - CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) = (1 << 8) | (1 << 1); // 1.5 div. - CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) |= 1; // Get divider out of reset. + CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) = (1 << 8) | PLLC4_OUT3_CLKEN; // 1.5 div. + CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) |= PLLC4_OUT3_RSTN_CLR; // Get divider out of reset. // Wait a bit for PLLC4 to stabilize. msleep(10); CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / 4. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = - (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3323; // PLLC4_OUT3. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003323; // PLLC4_OUT3. bpmp_clock_set = fid; } else { - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = - (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; // PLLP_OUT. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // PLLP_OUT. // Wait a bit for clock source change. msleep(10); CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / 3. - CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~(1<<30); + CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLL_BASE_ENABLE; bpmp_clock_set = BPMP_CLK_NORMAL; } } diff --git a/nyx/nyx_gui/soc/clock.c b/nyx/nyx_gui/soc/clock.c index df9634d..5ebdaea 100644 --- a/nyx/nyx_gui/soc/clock.c +++ b/nyx/nyx_gui/soc/clock.c @@ -25,58 +25,58 @@ /* clock_t: reset, enable, source, index, clk_src, clk_div */ static const clock_t _clock_uart[] = { -/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 0 }, -/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 0 }, -/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 0x17, 0, 0 }, -/* UART D */ { 0 }, -/* UART E */ { 0 } +/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 2 }, +/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 2 }, +/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 23, 0, 2 }, +/* UART D */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD, 1, 0, 2 }, +/* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 } }; static const clock_t _clock_i2c[] = { -/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 0xC, 0, 19 }, //20.4MHz -> 100KHz +/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz /* I2C2 */ { 0 }, -/* I2C3 */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, 3, 0, 4 }, //81.6MHz -> 400KHz +/* I2C3 */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, 3, 0, 4 }, //81.6MHz -> 400KHz /* I2C4 */ { 0 }, -/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 0, 4 }, //81.6MHz -> 400KHz +/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 15, 0, 4 }, //81.6MHz -> 400KHz /* I2C6 */ { 0 } }; static clock_t _clock_se = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 0x1F, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 31, 0, 0 }; static clock_t _clock_tzram = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, 0x1E, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, 30, 0, 0 }; static clock_t _clock_host1x = { - CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3 + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 28, 4, 3 }; static clock_t _clock_tsec = { - CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2 + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 19, 0, 2 }; static clock_t _clock_sor_safe = { - CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, 0x1E, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, 30, 0, 0 }; static clock_t _clock_sor0 = { - CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, 0x16, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, 22, 0, 0 }; static clock_t _clock_sor1 = { - CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 0x17, 0, 2 + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 23, 0, 2 }; static clock_t _clock_kfuse = { - CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, 8, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, 8, 0, 0 }; static clock_t _clock_cl_dvfs = { - CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, 0x1B, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, 27, 0, 0 }; static clock_t _clock_coresight = { - CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4 + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4 }; static clock_t _clock_pwm = { - CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 0x11, 6, 4 + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Freference: 6.2MHz. }; void clock_enable(const clock_t *clk) @@ -375,43 +375,44 @@ static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val) u32 divisor = 0; u32 source = PLLP_OUT0; + // Get IO clock divisor. switch (val) { case 25000: *pout = 24728; - divisor = 31; + divisor = 31; // 16.5 div. break; case 26000: *pout = 25500; - divisor = 30; + divisor = 30; // 16 div. break; case 40800: *pout = 40800; - divisor = 18; + divisor = 18; // 10 div. break; case 50000: *pout = 48000; - divisor = 15; + divisor = 15; // 8.5 div. break; case 52000: *pout = 51000; - divisor = 14; + divisor = 14; // 8 div. break; case 100000: *pout = 90667; - divisor = 7; + divisor = 7; // 4.5 div. break; case 200000: *pout = 163200; - divisor = 3; + divisor = 3; // 2.5 div. break; case 208000: *pout = 204000; - divisor = 2; + divisor = 2; // 2 div. break; default: *pout = 24728; - divisor = 31; + divisor = 31; // 16.5 div. } _clock_sdmmc_table[2 * id] = val; diff --git a/nyx/nyx_gui/soc/clock.h b/nyx/nyx_gui/soc/clock.h index e4d6a05..754608f 100644 --- a/nyx/nyx_gui/soc/clock.h +++ b/nyx/nyx_gui/soc/clock.h @@ -41,6 +41,8 @@ #define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C #define CLK_RST_CONTROLLER_PLLP_BASE 0xA0 #define CLK_RST_CONTROLLER_PLLD_BASE 0xD0 +#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8 +#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC #define CLK_RST_CONTROLLER_PLLX_BASE 0xE0 #define CLK_RST_CONTROLLER_PLLX_MISC 0xE4 #define CLK_RST_CONTROLLER_PLLE_BASE 0xE8 @@ -50,6 +52,7 @@ #define CLK_RST_CONTROLLER_CLK_SOURCE_PWM 0x110 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128 +#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138 #define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154 @@ -57,11 +60,13 @@ #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178 #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C #define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180 +#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 0x198 +#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 0x1B8 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC +#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD 0x1C0 #define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4 -#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C #define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280 #define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284 @@ -95,10 +100,12 @@ #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0 #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4 #define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4 +#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4 +#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400 #define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410 #define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C #define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440 -//#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444 +#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444 #define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448 #define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C #define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450 @@ -114,15 +121,25 @@ #define CLK_RST_CONTROLLER_PLLC4_OUT 0x5E4 #define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8 #define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620 -//#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 0x65C +#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 0x65C #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664 #define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL 0x66C #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694 #define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0 #define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704 +#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710 #define CLK_NO_SOURCE 0x0 +/*! PLL control and status bits */ +#define PLL_BASE_ENABLE (1 << 30) + +#define PLLC4_MISC_EN_LCKDET (1 << 30) +#define PLLC4_BASE_LOCK (1 << 27) +#define PLLC4_BASE_IDDQ (1 << 18) +#define PLLC4_OUT3_CLKEN (1 << 1) +#define PLLC4_OUT3_RSTN_CLR (1 << 0) + /*! Generic clock descriptor. */ typedef struct _clock_t { diff --git a/nyx/nyx_gui/soc/cluster.c b/nyx/nyx_gui/soc/cluster.c index 4633bae..50ec0ae 100644 --- a/nyx/nyx_gui/soc/cluster.c +++ b/nyx/nyx_gui/soc/cluster.c @@ -35,12 +35,12 @@ void _cluster_enable_power() // Enable cores power. // 1-3.x: MAX77621_NFSR_ENABLE. i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, - MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE); + MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE | MAX77621_RAMP_12mV_PER_US); // 1.0.0-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL. i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG, MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL); - i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | 0x37); - i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | 0x37); + i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_0_95V); + i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_0_95V); } int _cluster_pmc_enable_partition(u32 part, u32 toggle, bool enable) @@ -120,10 +120,10 @@ void cluster_boot_cpu0(u32 entry) EXCP_VEC(EVP_CPU_RESET_VECTOR) = 0; // Set reset vector. - SB(SB_AA64_RESET_LOW) = entry | 1; + SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN; SB(SB_AA64_RESET_HIGH) = 0; // Non-secure reset vector write disable. - SB(SB_CSR) = 2; + SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS; (void)SB(SB_CSR); // Clear MSELECT reset. diff --git a/nyx/nyx_gui/soc/i2c.c b/nyx/nyx_gui/soc/i2c.c index e845693..d06d64a 100644 --- a/nyx/nyx_gui/soc/i2c.c +++ b/nyx/nyx_gui/soc/i2c.c @@ -44,10 +44,10 @@ static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size) memcpy(&tmp, buf, size); vu32 *base = (vu32 *)i2c_addrs[idx]; - base[I2C_CMD_ADDR0] = x << 1; //Set x (send mode). - base[I2C_CMD_DATA1] = tmp; //Set value. - base[I2C_CNFG] = (2 * size - 2) | 0x2800; //Set size and send mode. - _i2c_wait(base); //Kick transaction. + base[I2C_CMD_ADDR0] = x << 1; //Set x (send mode). + base[I2C_CMD_DATA1] = tmp; //Set value. + base[I2C_CNFG] = ((size - 1) << 1) | 0x2800; //Set size and send mode. + _i2c_wait(base); //Kick transaction. base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200; while (base[I2C_STATUS] & 0x100) @@ -65,9 +65,9 @@ static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x) return 0; vu32 *base = (vu32 *)i2c_addrs[idx]; - base[I2C_CMD_ADDR0] = (x << 1) | 1; // Set x (recv mode). - base[I2C_CNFG] = (size - 1) << 1 | 0x2840; // Set size and recv mode. - _i2c_wait(base); // Kick transaction. + base[I2C_CMD_ADDR0] = (x << 1) | 1; // Set x (recv mode). + base[I2C_CNFG] = ((size - 1) << 1) | 0x2840; // Set size and recv mode. + _i2c_wait(base); // Kick transaction. base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200; while (base[I2C_STATUS] & 0x100) diff --git a/nyx/nyx_gui/soc/pinmux.h b/nyx/nyx_gui/soc/pinmux.h index a2d20b8..2db4a75 100644 --- a/nyx/nyx_gui/soc/pinmux.h +++ b/nyx/nyx_gui/soc/pinmux.h @@ -51,20 +51,24 @@ #define PINMUX_AUX_GPIO_X3_AUD 0x190 #define PINMUX_AUX_SPDIF_IN 0x1A4 #define PINMUX_AUX_USB_VBUS_EN0 0x1A8 +#define PINMUX_AUX_USB_VBUS_EN1 0x1AC #define PINMUX_AUX_WIFI_EN 0x1B4 #define PINMUX_AUX_WIFI_RST 0x1B8 #define PINMUX_AUX_AP_WAKE_NFC 0x1CC #define PINMUX_AUX_NFC_EN 0x1D0 #define PINMUX_AUX_NFC_INT 0x1D4 #define PINMUX_AUX_CAM1_PWDN 0x1EC +#define PINMUX_AUX_CAM2_PWDN 0x1F0 #define PINMUX_AUX_LCD_BL_PWM 0x1FC #define PINMUX_AUX_LCD_BL_EN 0x200 #define PINMUX_AUX_LCD_RST 0x204 #define PINMUX_AUX_LCD_GPIO2 0x20C #define PINMUX_AUX_TOUCH_INT 0x220 #define PINMUX_AUX_MOTION_INT 0x224 +#define PINMUX_AUX_BUTTON_HOME 0x240 #define PINMUX_AUX_GPIO_PE6 0x248 #define PINMUX_AUX_GPIO_PH6 0x250 +#define PINMUX_AUX_GPIO_PK3 0x260 #define PINMUX_AUX_GPIO_PZ1 0x280 /*! 0:UART-A, 1:UART-B, 3:UART-C, 3:UART-D */ #define PINMUX_AUX_UARTX_TX(x) (0xE4 + 0x10 * (x)) diff --git a/nyx/nyx_gui/soc/pmc.h b/nyx/nyx_gui/soc/pmc.h index ec8eb99..8cd9161 100644 --- a/nyx/nyx_gui/soc/pmc.h +++ b/nyx/nyx_gui/soc/pmc.h @@ -25,6 +25,7 @@ #define APBDEV_PMC_PWRGATE_TOGGLE 0x30 #define APBDEV_PMC_PWRGATE_STATUS 0x38 #define APBDEV_PMC_NO_IOPOWER 0x44 +#define PMC_NO_IOPOWER_SDMMC1_IO_EN (1 << 12) #define APBDEV_PMC_SCRATCH0 0x50 #define APBDEV_PMC_SCRATCH1 0x54 #define APBDEV_PMC_SCRATCH20 0xA0 @@ -37,6 +38,7 @@ #define APBDEV_PMC_SCRATCH33 0x120 #define APBDEV_PMC_SCRATCH40 0x13C #define APBDEV_PMC_OSC_EDPD_OVER 0x1A4 +#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000 #define APBDEV_PMC_RST_STATUS 0x1B4 #define APBDEV_PMC_IO_DPD_REQ 0x1B8 #define APBDEV_PMC_IO_DPD2_REQ 0x1C0 @@ -51,9 +53,11 @@ #define APBDEV_PMC_REG_SHORT 0x2CC #define APBDEV_PMC_SEC_DISABLE3 0x2D8 #define APBDEV_PMC_SECURE_SCRATCH21 0x334 +#define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT 0x10 #define APBDEV_PMC_SECURE_SCRATCH32 0x360 #define APBDEV_PMC_SECURE_SCRATCH49 0x3A4 #define APBDEV_PMC_CNTRL2 0x440 +#define PMC_CNTRL2_HOLD_CKE_LOW_EN 0x1000 #define APBDEV_PMC_IO_DPD3_REQ 0x45C #define APBDEV_PMC_IO_DPD4_REQ 0x464 #define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4 diff --git a/nyx/nyx_gui/soc/t210.h b/nyx/nyx_gui/soc/t210.h index 5aa266f..5d372a8 100644 --- a/nyx/nyx_gui/soc/t210.h +++ b/nyx/nyx_gui/soc/t210.h @@ -20,6 +20,7 @@ #include "../utils/types.h" #define BOOTROM_BASE 0x100000 +#define IRAM_BASE 0x40000000 #define HOST1X_BASE 0x50000000 #define BPMP_CACHE_BASE 0x50040000 #define DISPLAY_A_BASE 0x54200000 @@ -106,9 +107,11 @@ /*! Misc registers. */ #define APB_MISC_PP_STRAPPING_OPT_A 0x08 #define APB_MISC_PP_PINMUX_GLOBAL 0x40 +#define APB_MISC_GP_HIDREV 0x804 #define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34 #define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98 #define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4 +#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC #define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64 #define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68 @@ -118,7 +121,10 @@ /*! Secure boot registers. */ #define SB_CSR 0x0 +#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) +#define SB_CSR_PIROM_DISABLE (1 << 4) #define SB_AA64_RESET_LOW 0x30 +#define SB_AA64_RST_AARCH64_MODE_EN (1 << 0) #define SB_AA64_RESET_HIGH 0x34 /*! SOR registers. */ @@ -182,6 +188,7 @@ /*! PWM registers. */ #define PWM_CONTROLLER_PWM_CSR_0 0x00 #define PWM_CONTROLLER_PWM_CSR_1 0x10 +#define PWM_CSR_EN (1 << 31) /*! Special registers. */ #define EMC_SCRATCH0 0x324 diff --git a/nyx/nyx_gui/soc/uart.h b/nyx/nyx_gui/soc/uart.h index 78f3c15..808232d 100644 --- a/nyx/nyx_gui/soc/uart.h +++ b/nyx/nyx_gui/soc/uart.h @@ -22,9 +22,8 @@ #define UART_A 0 #define UART_B 1 #define UART_C 2 -//TODO: define clock inits for those. -/*#define UART_D 3 -#define UART_E 4*/ +#define UART_D 3 +#define UART_E 4 #define BAUD_115200 115200 @@ -34,15 +33,29 @@ #define UART_TX_FIFO_FULL 0x100 #define UART_RX_FIFO_EMPTY 0x200 +#define UART_INVERT_RXD 0x01 +#define UART_INVERT_TXD 0x02 +#define UART_INVERT_CTS 0x04 +#define UART_INVERT_RTS 0x08 + +#define UART_IER_DLAB_IE_EORD 0x20 + #define UART_LCR_DLAB 0x80 +#define UART_LCR_STOP 0x4 #define UART_LCR_WORD_LENGTH_8 0x3 + #define UART_LSR_RDR 0x1 #define UART_LSR_THRE 0x20 #define UART_LSR_TMTY 0x40 +#define UART_LSR_FIFOE 0x80 + #define UART_IIR_FCR_TX_CLR 0x4 #define UART_IIR_FCR_RX_CLR 0x2 #define UART_IIR_FCR_EN_FIFO 0x1 +#define UART_MCR_RTS 0x2 +#define UART_MCR_DTR 0x1 + typedef struct _uart_t { /* 0x00 */ vu32 UART_THR_DLAB; diff --git a/nyx/nyx_gui/storage/mmc.h b/nyx/nyx_gui/storage/mmc.h index dddb956..0d87e35 100644 --- a/nyx/nyx_gui/storage/mmc.h +++ b/nyx/nyx_gui/storage/mmc.h @@ -31,7 +31,7 @@ #define MMC_ALL_SEND_CID 2 /* bcr R2 */ #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ #define MMC_SET_DSR 4 /* bc [31:16] RCA */ -#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ +#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ #define MMC_SWITCH 6 /* ac [31:0] See below R1b */ #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ #define MMC_SEND_EXT_CSD 8 /* adtc R1 */ @@ -51,7 +51,7 @@ #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */ -#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ +#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ /* class 3 */ #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ diff --git a/nyx/nyx_gui/thermal/tmp451.c b/nyx/nyx_gui/thermal/tmp451.c index 79c503d..018cf6f 100644 --- a/nyx/nyx_gui/thermal/tmp451.c +++ b/nyx/nyx_gui/thermal/tmp451.c @@ -53,7 +53,7 @@ u16 tmp451_get_pcb_temp(bool intenger) void tmp451_init() { - // Disable ALARM. + // Disable ALARM and Range to 0 - 127 oC. i2c_send_byte(I2C_1, TMP451_I2C_ADDR, TMP451_CONFIG_REG, 0x80); // Set conversion rate to 32/s and make a read to update the reg. diff --git a/nyx/nyx_gui/utils/types.h b/nyx/nyx_gui/utils/types.h index bbddae0..577f24f 100644 --- a/nyx/nyx_gui/utils/types.h +++ b/nyx/nyx_gui/utils/types.h @@ -53,6 +53,7 @@ typedef int bool; #define BOOT_CFG_AUTOBOOT_EN (1 << 0) #define BOOT_CFG_FROM_LAUNCH (1 << 1) +#define BOOT_CFG_FROM_ID (1 << 2) #define BOOT_CFG_SEPT_RUN (1 << 7) #define EXTRA_CFG_KEYS (1 << 0) @@ -64,11 +65,18 @@ typedef int bool; typedef struct __attribute__((__packed__)) _boot_cfg_t { - u8 boot_cfg; - u8 autoboot; - u8 autoboot_list; - u8 extra_cfg; - u8 rsvd[128]; + u8 boot_cfg; + u8 autoboot; + u8 autoboot_list; + u8 extra_cfg; + union + { + struct + { + char id[8]; + }; + u8 xt_str[0x80]; + }; } boot_cfg_t; typedef struct __attribute__((__packed__)) _ipl_ver_meta_t