From 70523e404f62a21d149be21f6f8156dffb55cbcd Mon Sep 17 00:00:00 2001 From: CTCaer Date: Mon, 11 Jul 2022 22:10:11 +0300 Subject: [PATCH] bdk: whitespace refactor --- bdk/display/di.c | 86 +++-- bdk/input/als.c | 18 +- bdk/input/joycon.c | 41 +- bdk/input/touch.c | 15 +- bdk/mem/heap.c | 2 + bdk/mem/sdram.c | 769 +++++++++++++++++++------------------ bdk/mem/smmu.c | 13 +- bdk/rtc/max77620-rtc.c | 12 +- bdk/sec/se.c | 42 +- bdk/sec/tsec.c | 43 ++- bdk/soc/bpmp.c | 8 +- bdk/soc/ccplex.c | 6 +- bdk/soc/clock.c | 32 +- bdk/soc/clock.h | 2 + bdk/soc/hw_init.c | 28 +- bdk/soc/irq.c | 20 +- bdk/soc/pinmux.c | 4 +- bdk/soc/uart.c | 14 +- bdk/storage/emmc.c | 6 +- bdk/storage/sdmmc.c | 151 ++++---- bdk/storage/sdmmc_driver.c | 4 +- bdk/thermal/fan.c | 4 +- bdk/usb/usb_gadget_ums.c | 237 ++++++------ bdk/usb/usbd.c | 69 ++-- bdk/usb/xusbd.c | 99 ++--- bdk/utils/ini.c | 8 +- 26 files changed, 898 insertions(+), 835 deletions(-) diff --git a/bdk/display/di.c b/bdk/display/di.c index 12f6b0c..19d1557 100644 --- a/bdk/display/di.c +++ b/bdk/display/di.c @@ -444,12 +444,12 @@ void display_init() exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_setup_win_config, CFG_SIZE(_di_dc_setup_win_config)); // Setup dsi init sequence packets. - exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config0, CFG_SIZE(_di_dsi_init_irq_pkt_config0)); + exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config0, CFG_SIZE(_di_dsi_init_irq_pkt_config0)); if (tegra_t210) DSI(_DSIREG(DSI_INIT_SEQ_DATA_15)) = 0; else DSI(_DSIREG(DSI_INIT_SEQ_DATA_15_B01)) = 0; - exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config1, CFG_SIZE(_di_dsi_init_irq_pkt_config1)); + exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config1, CFG_SIZE(_di_dsi_init_irq_pkt_config1)); // Reset pad trimmers for T210B01. if (!tegra_t210) @@ -499,7 +499,8 @@ void display_init() case PANEL_SAM_AMS699VC01: _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000); // Set color mode to natural. Stock is Default (0x00) which is VIVID (0x65). (Reset value is 0x20). - _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, MIPI_DCS_PRIV_SM_SET_COLOR_MODE | (DCS_SM_COLOR_MODE_NATURAL << 8), 0); + _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, + MIPI_DCS_PRIV_SM_SET_COLOR_MODE | (DCS_SM_COLOR_MODE_NATURAL << 8), 0); // Enable backlight and smooth PWM. _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, MIPI_DCS_SET_CONTROL_DISPLAY | ((DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL | DCS_CONTROL_DISPLAY_DIMMING_CTRL) << 8), 0); @@ -512,7 +513,7 @@ void display_init() // Set registers offset and set PWM transition to 6 frames (100ms). _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, MIPI_DCS_PRIV_SM_SET_REG_OFFSET | (7 << 8), 0); - _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, MIPI_DCS_PRIV_SM_SET_ELVSS | (6 << 8), 0); + _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, MIPI_DCS_PRIV_SM_SET_ELVSS | (6 << 8), 0); // Relock Level 2 registers. DSI(_DSIREG(DSI_WR_DATA)) = 0x539; // MIPI_DSI_DCS_LONG_WRITE: 5 bytes. @@ -593,12 +594,12 @@ void display_init() // Set pad trimmers and set MIPI DSI cal offsets. if (tegra_t210) { - exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, CFG_SIZE(_di_dsi_pad_cal_config_t210)); + exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, CFG_SIZE(_di_dsi_pad_cal_config_t210)); exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210, CFG_SIZE(_di_mipi_dsi_cal_offsets_config_t210)); } else { - exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210b01, CFG_SIZE(_di_dsi_pad_cal_config_t210b01)); + exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210b01, CFG_SIZE(_di_dsi_pad_cal_config_t210b01)); exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210b01, CFG_SIZE(_di_mipi_dsi_cal_offsets_config_t210b01)); } @@ -618,7 +619,8 @@ void display_backlight_pwm_init() clock_enable_pwm(); - PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN; // Enable PWM and set it to 25KHz PFM. 29.5KHz is stock. + // Enable PWM and set it to 25KHz PFM. 29.5KHz is stock. + PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN; PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_FUNC_MASK) | 1; // Set PWM0 mode. gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight power mode. @@ -626,7 +628,8 @@ void display_backlight_pwm_init() void display_backlight(bool enable) { - gpio_write(GPIO_PORT_V, GPIO_PIN_0, enable ? GPIO_HIGH : GPIO_LOW); // Backlight PWM GPIO. + // Backlight PWM GPIO. + gpio_write(GPIO_PORT_V, GPIO_PIN_0, enable ? GPIO_HIGH : GPIO_LOW); } static void _display_dsi_backlight_brightness(u32 duty) @@ -798,7 +801,8 @@ skip_panel_deinit: CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); // Power down pads. - DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF); + DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | + DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF); DSI(_DSIREG(DSI_POWER_CONTROL)) = 0; // Switch LCD PWM backlight pin to special function mode and enable PWM0 mode. @@ -890,64 +894,91 @@ u32 *display_init_framebuffer_log() void display_activate_console() { - DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window D. - DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = WIN_ENABLE; // Enable window DD. - DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0xFF80; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; + // Select window D. + DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; + + // Enable and setup window D. + DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = WIN_ENABLE; + DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0xFF80; // X: -128. + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ; + // Pull-down effect. for (u32 i = 0xFF80; i < 0x10000; i++) { + // Set window position. DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ; usleep(1000); } DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ; - DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_A_SELECT; // Select window A. + + // Re-select window A. + DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_A_SELECT; } void display_deactivate_console() { - DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window D. + // Select window D. + DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; + // Pull-up effect. for (u32 i = 0xFFFF; i > 0xFF7F; i--) { + // Set window position. DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ; usleep(500); } + // Disable window D. DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0; - DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0; // Disable window DD. - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; + DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ; - DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_A_SELECT; // Select window A. + + // Re-select window A. + DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_A_SELECT; } void display_init_cursor(void *crs_fb, u32 size) { // Setup cursor. - DISPLAY_A(_DIREG(DC_DISP_CURSOR_START_ADDR)) = CURSOR_CLIPPING(CURSOR_CLIP_WIN_A) | size | ((u32)crs_fb >> 10); - DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = - CURSOR_BLEND_R8G8B8A8 | CURSOR_BLEND_DST_FACTOR(CURSOR_BLEND_K1) | CURSOR_BLEND_SRC_FACTOR(CURSOR_BLEND_K1) | 0xFF; + DISPLAY_A(_DIREG(DC_DISP_CURSOR_START_ADDR)) = CURSOR_CLIPPING(CURSOR_CLIP_WIN_A) | size | ((u32)crs_fb >> 10); + DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = CURSOR_BLEND_R8G8B8A8 | + CURSOR_BLEND_DST_FACTOR(CURSOR_BLEND_K1) | + CURSOR_BLEND_SRC_FACTOR(CURSOR_BLEND_K1) | 0xFF; + // Enable cursor window. DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) |= CURSOR_ENABLE; // Arm and activate changes. - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ; } void display_set_pos_cursor(u32 x, u32 y) { + // Set cursor position. DISPLAY_A(_DIREG(DC_DISP_CURSOR_POSITION)) = x | (y << 16); - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ; } @@ -955,6 +986,7 @@ void display_deinit_cursor() { DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = 0; DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) &= ~CURSOR_ENABLE; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; + + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ; } diff --git a/bdk/input/als.c b/bdk/input/als.c index be55426..54e4464 100644 --- a/bdk/input/als.c +++ b/bdk/input/als.c @@ -73,7 +73,7 @@ void set_als_cfg(als_ctxt_t *als_ctxt, u8 gain, u8 cycle) else if (cycle > 255) cycle = 255; - i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_GAIN_REG), gain); + i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_GAIN_REG), gain); i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_TIMING_REG), (256 - cycle)); als_ctxt->gain = gain; @@ -83,25 +83,25 @@ void set_als_cfg(als_ctxt_t *als_ctxt, u8 gain, u8 cycle) void get_als_lux(als_ctxt_t *als_ctxt) { u32 data[2]; - u32 visible_light; + u32 vi_light; u32 ir_light; u64 lux = 0; u32 itime_us = BH1730_ITIME_CYCLE_TO_US * als_ctxt->cycle; // Get visible and ir light raw data. Mode is continuous so waiting for new values doesn't matter. data[0] = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0LOW_REG)) + - (i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0HIGH_REG)) << 8); + (i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0HIGH_REG)) << 8); data[1] = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1LOW_REG)) + - (i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1HIGH_REG)) << 8); + (i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1HIGH_REG)) << 8); - visible_light = data[0]; + vi_light = data[0]; ir_light = data[1]; - als_ctxt->over_limit = visible_light > 65534 || ir_light > 65534; - als_ctxt->vi_light = visible_light; + als_ctxt->vi_light = vi_light; als_ctxt->ir_light = ir_light; + als_ctxt->over_limit = vi_light > 65534 || ir_light > 65534; - if (!visible_light) + if (!vi_light) { als_ctxt->lux = 0; @@ -116,7 +116,7 @@ void get_als_lux(als_ctxt_t *als_ctxt) // Apply optical window calibration coefficients. for (u32 i = 0; i < opt_win_cal_count; i++) { - if (1000 * ir_light / visible_light < opt_win_cal[i].rc) + if (1000 * ir_light / vi_light < opt_win_cal[i].rc) { lux = ((u64)opt_win_cal[i].cv * data[0]) - (opt_win_cal[i].ci * data[1]); break; diff --git a/bdk/input/joycon.c b/bdk/input/joycon.c index 48d06d5..7a077fb 100644 --- a/bdk/input/joycon.c +++ b/bdk/input/joycon.c @@ -442,14 +442,14 @@ static void _jc_conn_check() hid_pkt_inc = 0; - jc_l.connected = false; + jc_l.connected = false; jc_l.rumble_sent = false; - jc_gamepad.buttons &= ~JC_BTN_MASK_L; jc_gamepad.conn_l = false; - jc_gamepad.batt_info_l = 0; + jc_gamepad.batt_info_l = 0; jc_gamepad.bt_conn_l.type = 0; + jc_gamepad.buttons &= ~JC_BTN_MASK_L; } if (!jc_r.detected) @@ -459,14 +459,14 @@ static void _jc_conn_check() hid_pkt_inc = 0; - jc_r.connected = false; + jc_r.connected = false; jc_r.rumble_sent = false; - jc_gamepad.buttons &= ~JC_BTN_MASK_R; jc_gamepad.conn_r = false; - jc_gamepad.batt_info_r = 0; + jc_gamepad.batt_info_r = 0; jc_gamepad.bt_conn_r.type = 0; + jc_gamepad.buttons &= ~JC_BTN_MASK_R; } } @@ -542,7 +542,7 @@ static void _jc_send_hid_cmd(u8 uart, u8 subcmd, u8 *data, u16 size) bool send_l_rumble = jc_l.connected && !jc_l.rumble_sent; // Enable rumble. - hid_pkt->cmd = JC_HID_OUTPUT_RPT; + hid_pkt->cmd = JC_HID_OUTPUT_RPT; hid_pkt->pkt_id = _jc_hid_pkt_id_incr(); hid_pkt->subcmd = JC_HID_SUBCMD_RUMBLE_CTL; hid_pkt->subcmd_data[0] = 1; @@ -552,7 +552,7 @@ static void _jc_send_hid_cmd(u8 uart, u8 subcmd, u8 *data, u16 size) _jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 0x10, false); // Send rumble. - hid_pkt->cmd = JC_HID_RUMBLE_RPT; + hid_pkt->cmd = JC_HID_RUMBLE_RPT; hid_pkt->pkt_id = _jc_hid_pkt_id_incr(); memcpy(hid_pkt->rumble, rumble_init, sizeof(rumble_init)); if (send_r_rumble) @@ -563,7 +563,7 @@ static void _jc_send_hid_cmd(u8 uart, u8 subcmd, u8 *data, u16 size) msleep(15); // Disable rumble. - hid_pkt->cmd = JC_HID_OUTPUT_RPT; + hid_pkt->cmd = JC_HID_OUTPUT_RPT; hid_pkt->pkt_id = _jc_hid_pkt_id_incr(); hid_pkt->subcmd = JC_HID_SUBCMD_RUMBLE_CTL; hid_pkt->subcmd_data[0] = 0; @@ -577,7 +577,7 @@ static void _jc_send_hid_cmd(u8 uart, u8 subcmd, u8 *data, u16 size) { bool crc_needed = (jc_l.uart == uart) ? (jc_l.type & JC_ID_HORI) : (jc_r.type & JC_ID_HORI); - hid_pkt->cmd = JC_HID_OUTPUT_RPT; + hid_pkt->cmd = JC_HID_OUTPUT_RPT; hid_pkt->pkt_id = _jc_hid_pkt_id_incr(); hid_pkt->subcmd = subcmd; if (data) @@ -646,7 +646,7 @@ static void _jc_parse_wired_hid(joycon_ctxt_t *jc, const u8* packet, u32 size) else bt_conn = &jc_gamepad.bt_conn_r; - jc_hid_in_spi_read_t *spi_info = (jc_hid_in_spi_read_t *)hid_pkt->subcmd_data; + jc_hid_in_spi_read_t *spi_info = (jc_hid_in_spi_read_t *)hid_pkt->subcmd_data; jc_hid_in_pair_data_t *pair_data = (jc_hid_in_pair_data_t *)spi_info->data; // Check if the reply is pairing info. @@ -718,7 +718,7 @@ static void _jc_sio_parse_payload(joycon_ctxt_t *jc, u8 cmd, const u8* payload, case JC_SIO_CMD_STATUS: jc_sio_hid_in_rpt_t *hid_pkt = (jc_sio_hid_in_rpt_t *)payload; jc_gamepad.buttons = hid_pkt->btn_right | hid_pkt->btn_shared << 8 | hid_pkt->btn_left << 16; - jc_gamepad.home = !gpio_read(GPIO_PORT_V, GPIO_PIN_3); + jc_gamepad.home = !gpio_read(GPIO_PORT_V, GPIO_PIN_3); jc_gamepad.lstick_x = hid_pkt->stick_h_left | ((hid_pkt->stick_m_left & 0xF) << 8); jc_gamepad.lstick_y = (hid_pkt->stick_m_left >> 4) | (hid_pkt->stick_v_left << 4); @@ -727,6 +727,7 @@ static void _jc_sio_parse_payload(joycon_ctxt_t *jc, u8 cmd, const u8* payload, jc_gamepad.batt_info_l = jc_l.connected; jc_gamepad.batt_info_r = gpio_read(GPIO_PORT_E, GPIO_PIN_7); // Set IRQ status. + jc_gamepad.conn_l = jc_l.connected; jc_gamepad.conn_r = jc_l.connected; break; @@ -831,9 +832,9 @@ static void _jc_req_nx_pad_status(joycon_ctxt_t *jc) } if (is_nxpad) - _joycon_send_raw(jc->uart, nx_pad_status, sizeof(nx_pad_status)); + _joycon_send_raw(jc->uart, nx_pad_status, sizeof(nx_pad_status)); else if (jc->sio_mode) - _joycon_send_raw(jc->uart, sio_pad_status, sizeof(sio_pad_status)); + _joycon_send_raw(jc->uart, sio_pad_status, sizeof(sio_pad_status)); else _joycon_send_raw(jc->uart, hori_pad_status, sizeof(hori_pad_status)); @@ -870,11 +871,11 @@ jc_gamepad_rpt_t *jc_get_bt_pairing_info(bool *is_l_hos, bool *is_r_hos) bt_conn = &jc_gamepad.bt_conn_l; memset(bt_conn->host_mac, 0, 6); - memset(bt_conn->ltk, 0, 16); + memset(bt_conn->ltk, 0, 16); bt_conn = &jc_gamepad.bt_conn_r; memset(bt_conn->host_mac, 0, 6); - memset(bt_conn->ltk, 0, 16); + memset(bt_conn->ltk, 0, 16); _jc_conn_check(); @@ -981,14 +982,14 @@ retry: { bt_conn = &jc_gamepad.bt_conn_l; memset(bt_conn->host_mac, 0, 6); - memset(bt_conn->ltk, 0, 16); + memset(bt_conn->ltk, 0, 16); } if (!jc_r_found) { bt_conn = &jc_gamepad.bt_conn_r; memset(bt_conn->host_mac, 0, 6); - memset(bt_conn->ltk, 0, 16); + memset(bt_conn->ltk, 0, 16); } } @@ -1159,12 +1160,12 @@ void jc_init_hw() gpio_config(GPIO_PORT_V, GPIO_PIN_3, GPIO_MODE_GPIO); // Configure Sio IRQ - PINMUX_AUX(PINMUX_AUX_GPIO_PE7) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP; + PINMUX_AUX(PINMUX_AUX_GPIO_PE7) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP; gpio_config(GPIO_PORT_E, GPIO_PIN_7, GPIO_MODE_GPIO); // Configure Sio RST and BOOT0. PINMUX_AUX(PINMUX_AUX_CAM1_STROBE) = PINMUX_PULL_DOWN | 1; - PINMUX_AUX(PINMUX_AUX_CAM2_PWDN) = PINMUX_PULL_DOWN | 1; + PINMUX_AUX(PINMUX_AUX_CAM2_PWDN) = PINMUX_PULL_DOWN | 1; gpio_config(GPIO_PORT_T, GPIO_PIN_1 | GPIO_PIN_0, GPIO_MODE_GPIO); gpio_output_enable(GPIO_PORT_T, GPIO_PIN_1 | GPIO_PIN_0, GPIO_OUTPUT_ENABLE); gpio_write(GPIO_PORT_T, GPIO_PIN_1 | GPIO_PIN_0, GPIO_LOW); diff --git a/bdk/input/touch.c b/bdk/input/touch.c index 748429a..8b6247e 100644 --- a/bdk/input/touch.c +++ b/bdk/input/touch.c @@ -87,19 +87,19 @@ static int touch_wait_event(u8 event, u8 status, u32 timeout, u8 *buf) static void _touch_compensate_limits(touch_event *event, bool touching) { - event->x = MAX(event->x, EDGE_OFFSET); - event->x = MIN(event->x, X_REAL_MAX); + event->x = MAX(event->x, EDGE_OFFSET); + event->x = MIN(event->x, X_REAL_MAX); event->x -= EDGE_OFFSET; u32 x_adj = (1280 * 1000) / (X_REAL_MAX - EDGE_OFFSET); - event->x = ((u32)event->x * x_adj) / 1000; + event->x = ((u32)event->x * x_adj) / 1000; if (touching) { - event->y = MAX(event->y, EDGE_OFFSET); - event->y = MIN(event->y, Y_REAL_MAX); + event->y = MAX(event->y, EDGE_OFFSET); + event->y = MIN(event->y, Y_REAL_MAX); event->y -= EDGE_OFFSET; u32 y_adj = (720 * 1000) / (Y_REAL_MAX - EDGE_OFFSET); - event->y = ((u32)event->y * y_adj) / 1000; + event->y = ((u32)event->y * y_adj) / 1000; } } @@ -115,6 +115,7 @@ static void _touch_process_contact_event(touch_event *event, bool touching) event->z = event->raw[5] | (event->raw[6] << 8); event->z = event->z << 6; + u16 tmp = 0x40; if ((event->raw[7] & 0x3F) != 1 && (event->raw[7] & 0x3F) != 0x3F) tmp = event->raw[7] & 0x3F; @@ -245,7 +246,7 @@ int touch_get_fw_info(touch_fw_info_t *fw) res = touch_read_reg(cmd, 3, buf, 8); if (!res) { - fw->fw_id = (buf[1] << 24) | (buf[2] << 16) | (buf[3] << 8) | buf[4]; + fw->fw_id = (buf[1] << 24) | (buf[2] << 16) | (buf[3] << 8) | buf[4]; fw->ftb_ver = (buf[6] << 8) | buf[5]; } diff --git a/bdk/mem/heap.c b/bdk/mem/heap.c index 267fe9c..9c5b406 100644 --- a/bdk/mem/heap.c +++ b/bdk/mem/heap.c @@ -44,6 +44,7 @@ static void *_heap_alloc(u32 size) node->size = size; node->prev = NULL; node->next = NULL; + _heap.first = node; _heap.last = node; @@ -103,6 +104,7 @@ static void *_heap_alloc(u32 size) new_node->size = size; new_node->prev = node; new_node->next = NULL; + node->next = new_node; _heap.last = new_node; diff --git a/bdk/mem/sdram.c b/bdk/mem/sdram.c index 1876016..6eb265d 100644 --- a/bdk/mem/sdram.c +++ b/bdk/mem/sdram.c @@ -253,7 +253,7 @@ break_nosleep: *(vu32 *)params->emc_bct_spare6 = params->emc_bct_spare7; // Set pad controls. - EMC(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; + EMC(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; EMC(EMC_XM2COMPPADCTRL2) = params->emc_xm2_comp_pad_ctrl2; EMC(EMC_XM2COMPPADCTRL3) = params->emc_xm2_comp_pad_ctrl3; @@ -266,70 +266,70 @@ break_nosleep: EMC(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7; EMC(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8; - EMC(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; - EMC(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; - EMC(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; + EMC(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; + EMC(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; + EMC(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive; EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common; - EMC(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; - EMC(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; + EMC(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; + EMC(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; - EMC(EMC_DLL_CFG_0) = params->emc_dll_cfg0; - EMC(EMC_DLL_CFG_1) = params->emc_dll_cfg1; + EMC(EMC_DLL_CFG_0) = params->emc_dll_cfg0; + EMC(EMC_DLL_CFG_1) = params->emc_dll_cfg1; EMC(EMC_CFG_DIG_DLL_1) = params->emc_cfg_dig_dll_1; EMC(EMC_DATA_BRLSHFT_0) = params->emc_data_brlshft0; EMC(EMC_DATA_BRLSHFT_1) = params->emc_data_brlshft1; - EMC(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; - EMC(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; - EMC(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; - EMC(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; - EMC(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; - EMC(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; + EMC(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; + EMC(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; + EMC(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; + EMC(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; + EMC(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; + EMC(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; EMC(EMC_QUSE_BRLSHFT_0) = params->emc_quse_brlshft0; EMC(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1; EMC(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2; EMC(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3; EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = (params->emc_pmacro_brick_ctrl_rfu1 & 0x1BF01BF) | 0x1E401E40; - EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; + EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; - EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; - EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F; + EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; + EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F; EMC(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd; - EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0; - EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; - EMC(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; - EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; - EMC(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; - EMC(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; - EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl; + EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0; + EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; + EMC(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; + EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; + EMC(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; + EMC(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; + EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl; EMC(EMC_CFG_3) = params->emc_cfg3; - EMC(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; - EMC(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; - EMC(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; - EMC(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; - EMC(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; - EMC(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; + EMC(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; + EMC(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; + EMC(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; + EMC(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; + EMC(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; + EMC(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->emc_pmacro_tx_sel_clk_src0; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->emc_pmacro_tx_sel_clk_src1; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->emc_pmacro_tx_sel_clk_src2; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->emc_pmacro_tx_sel_clk_src3; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->emc_pmacro_tx_sel_clk_src4; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->emc_pmacro_tx_sel_clk_src5; - EMC(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; - EMC(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; - EMC(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; - EMC(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; - EMC(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; - EMC(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; - EMC(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; - EMC(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; - EMC(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; - EMC(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0; - EMC(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1; - EMC(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; + EMC(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; + EMC(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; + EMC(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; + EMC(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; + EMC(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; + EMC(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; + EMC(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; + EMC(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; + EMC(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; + EMC(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0; + EMC(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1; + EMC(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; EMC(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->emc_pmacro_quse_ddll_rank0_0; EMC(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->emc_pmacro_quse_ddll_rank0_1; @@ -343,7 +343,7 @@ break_nosleep: EMC(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->emc_pmacro_quse_ddll_rank1_3; EMC(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->emc_pmacro_quse_ddll_rank1_4; EMC(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->emc_pmacro_quse_ddll_rank1_5; - EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1; + EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1; EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->emc_pmacro_ob_ddll_long_dq_rank0_0; EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->emc_pmacro_ob_ddll_long_dq_rank0_1; @@ -379,11 +379,11 @@ break_nosleep: EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ib_ddll_long_dqs_rank1_2; EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ib_ddll_long_dqs_rank1_3; - EMC(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; - EMC(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; - EMC(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; - EMC(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; - EMC(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; + EMC(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; + EMC(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; + EMC(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; + EMC(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; + EMC(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; EMC(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0; EMC(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1; EMC(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2; @@ -398,18 +398,18 @@ break_nosleep: EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place. // Initialize MC VPR settings. - MC(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; - MC(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; - MC(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; - MC(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; - MC(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; + MC(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; + MC(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; + MC(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; + MC(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; + MC(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->mc_video_protect_gpu_override0; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->mc_video_protect_gpu_override1; // Program SDRAM geometry parameters. - MC(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; - MC(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; - MC(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; + MC(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; + MC(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; + MC(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; MC(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->mc_emem_adr_cfg_channel_mask; // Program bank swizzling. @@ -421,44 +421,44 @@ break_nosleep: MC(MC_EMEM_CFG) = params->mc_emem_cfg; // Program SEC carveout (base and size). - MC(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; - MC(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; + MC(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; + MC(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; MC(MC_SEC_CARVEOUT_SIZE_MB) = params->mc_sec_carveout_size_mb; // Program MTS carveout (base and size). - MC(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; - MC(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; + MC(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; + MC(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; MC(MC_MTS_CARVEOUT_SIZE_MB) = params->mc_mts_carveout_size_mb; // Program the memory arbiter. - MC(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; + MC(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; MC(MC_EMEM_ARB_OUTSTANDING_REQ) = params->mc_emem_arb_outstanding_req; - MC(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; + MC(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; MC(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->emc_emem_arb_refpb_bank_ctrl; - MC(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; - MC(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; - MC(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; - MC(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; - MC(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; - MC(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; - MC(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; - MC(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; - MC(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; - MC(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; - MC(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; - MC(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; - MC(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; - MC(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; - MC(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; - MC(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; - MC(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; - MC(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; - MC(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; - MC(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; - MC(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; - MC(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; - MC(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; - MC(MC_DA_CONFIG0) = params->mc_da_cfg0; + MC(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; + MC(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; + MC(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; + MC(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; + MC(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; + MC(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; + MC(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; + MC(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; + MC(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; + MC(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; + MC(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; + MC(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; + MC(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; + MC(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; + MC(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; + MC(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; + MC(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; + MC(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; + MC(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; + MC(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; + MC(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; + MC(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; + MC(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; + MC(MC_DA_CONFIG0) = params->mc_da_cfg0; MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update. @@ -483,7 +483,7 @@ break_nosleep: EMC(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1; EMC(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval; - EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; + EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; usleep(params->emc_auto_cal_wait); // Patch 5 using BCT spare variables. @@ -491,96 +491,96 @@ break_nosleep: *(vu32 *)params->emc_bct_spare8 = params->emc_bct_spare9; // Program EMC timing configuration. - EMC(EMC_CFG_2) = params->emc_cfg2; - EMC(EMC_CFG_PIPE) = params->emc_cfg_pipe; - EMC(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; - EMC(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; - EMC(EMC_CMDQ) = params->emc_cmd_q; - EMC(EMC_MC2EMCQ) = params->emc_mc2emc_q; - EMC(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; - EMC(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; - EMC(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; - EMC(EMC_RC) = params->emc_rc; - EMC(EMC_RFC) = params->emc_rfc; - EMC(EMC_RFCPB) = params->emc_rfc_pb; - EMC(EMC_REFCTRL2) = params->emc_ref_ctrl2; - EMC(EMC_RFC_SLR) = params->emc_rfc_slr; - EMC(EMC_RAS) = params->emc_ras; - EMC(EMC_RP) = params->emc_rp; - EMC(EMC_TPPD) = params->emc_tppd; - EMC(EMC_R2R) = params->emc_r2r; - EMC(EMC_W2W) = params->emc_w2w; - EMC(EMC_R2W) = params->emc_r2w; - EMC(EMC_W2R) = params->emc_w2r; - EMC(EMC_R2P) = params->emc_r2p; - EMC(EMC_W2P) = params->emc_w2p; - EMC(EMC_CCDMW) = params->emc_ccdmw; - EMC(EMC_RD_RCD) = params->emc_rd_rcd; - EMC(EMC_WR_RCD) = params->emc_wr_rcd; - EMC(EMC_RRD) = params->emc_rrd; - EMC(EMC_REXT) = params->emc_rext; - EMC(EMC_WEXT) = params->emc_wext; - EMC(EMC_WDV) = params->emc_wdv; - EMC(EMC_WDV_CHK) = params->emc_wdv_chk; - EMC(EMC_WSV) = params->emc_wsv; - EMC(EMC_WEV) = params->emc_wev; - EMC(EMC_WDV_MASK) = params->emc_wdv_mask; - EMC(EMC_WS_DURATION) = params->emc_ws_duration; - EMC(EMC_WE_DURATION) = params->emc_we_duration; - EMC(EMC_QUSE) = params->emc_quse; - EMC(EMC_QUSE_WIDTH) = params->emc_quse_width; - EMC(EMC_IBDLY) = params->emc_ibdly; - EMC(EMC_OBDLY) = params->emc_obdly; - EMC(EMC_EINPUT) = params->emc_einput; + EMC(EMC_CFG_2) = params->emc_cfg2; + EMC(EMC_CFG_PIPE) = params->emc_cfg_pipe; + EMC(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; + EMC(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; + EMC(EMC_CMDQ) = params->emc_cmd_q; + EMC(EMC_MC2EMCQ) = params->emc_mc2emc_q; + EMC(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; + EMC(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; + EMC(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; + EMC(EMC_RC) = params->emc_rc; + EMC(EMC_RFC) = params->emc_rfc; + EMC(EMC_RFCPB) = params->emc_rfc_pb; + EMC(EMC_REFCTRL2) = params->emc_ref_ctrl2; + EMC(EMC_RFC_SLR) = params->emc_rfc_slr; + EMC(EMC_RAS) = params->emc_ras; + EMC(EMC_RP) = params->emc_rp; + EMC(EMC_TPPD) = params->emc_tppd; + EMC(EMC_R2R) = params->emc_r2r; + EMC(EMC_W2W) = params->emc_w2w; + EMC(EMC_R2W) = params->emc_r2w; + EMC(EMC_W2R) = params->emc_w2r; + EMC(EMC_R2P) = params->emc_r2p; + EMC(EMC_W2P) = params->emc_w2p; + EMC(EMC_CCDMW) = params->emc_ccdmw; + EMC(EMC_RD_RCD) = params->emc_rd_rcd; + EMC(EMC_WR_RCD) = params->emc_wr_rcd; + EMC(EMC_RRD) = params->emc_rrd; + EMC(EMC_REXT) = params->emc_rext; + EMC(EMC_WEXT) = params->emc_wext; + EMC(EMC_WDV) = params->emc_wdv; + EMC(EMC_WDV_CHK) = params->emc_wdv_chk; + EMC(EMC_WSV) = params->emc_wsv; + EMC(EMC_WEV) = params->emc_wev; + EMC(EMC_WDV_MASK) = params->emc_wdv_mask; + EMC(EMC_WS_DURATION) = params->emc_ws_duration; + EMC(EMC_WE_DURATION) = params->emc_we_duration; + EMC(EMC_QUSE) = params->emc_quse; + EMC(EMC_QUSE_WIDTH) = params->emc_quse_width; + EMC(EMC_IBDLY) = params->emc_ibdly; + EMC(EMC_OBDLY) = params->emc_obdly; + EMC(EMC_EINPUT) = params->emc_einput; EMC(EMC_EINPUT_DURATION) = params->emc_einput_duration; - EMC(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; - EMC(EMC_PUTERM_WIDTH) = params->emc_puterm_width; + EMC(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; + EMC(EMC_PUTERM_WIDTH) = params->emc_puterm_width; EMC(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->emc_pmacro_common_pad_tx_ctrl; - EMC(EMC_DBG) = params->emc_dbg; - EMC(EMC_QRST) = params->emc_qrst; - EMC(EMC_ISSUE_QRST) = 1; - EMC(EMC_ISSUE_QRST) = 0; - EMC(EMC_QSAFE) = params->emc_qsafe; - EMC(EMC_RDV) = params->emc_rdv; - EMC(EMC_RDV_MASK) = params->emc_rdv_mask; - EMC(EMC_RDV_EARLY) = params->emc_rdv_early; - EMC(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; - EMC(EMC_QPOP) = params->emc_qpop; - EMC(EMC_REFRESH) = params->emc_refresh; - EMC(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; + EMC(EMC_DBG) = params->emc_dbg; + EMC(EMC_QRST) = params->emc_qrst; + EMC(EMC_ISSUE_QRST) = 1; + EMC(EMC_ISSUE_QRST) = 0; + EMC(EMC_QSAFE) = params->emc_qsafe; + EMC(EMC_RDV) = params->emc_rdv; + EMC(EMC_RDV_MASK) = params->emc_rdv_mask; + EMC(EMC_RDV_EARLY) = params->emc_rdv_early; + EMC(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; + EMC(EMC_QPOP) = params->emc_qpop; + EMC(EMC_REFRESH) = params->emc_refresh; + EMC(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; EMC(EMC_PRE_REFRESH_REQ_CNT) = params->emc_prerefresh_req_cnt; - EMC(EMC_PDEX2WR) = params->emc_pdex2wr; - EMC(EMC_PDEX2RD) = params->emc_pdex2rd; - EMC(EMC_PCHG2PDEN) = params->emc_pchg2pden; - EMC(EMC_ACT2PDEN) = params->emc_act2pden; - EMC(EMC_AR2PDEN) = params->emc_ar2pden; - EMC(EMC_RW2PDEN) = params->emc_rw2pden; - EMC(EMC_CKE2PDEN) = params->emc_cke2pden; - EMC(EMC_PDEX2CKE) = params->emc_pdex2che; - EMC(EMC_PDEX2MRR) = params->emc_pdex2mrr; - EMC(EMC_TXSR) = params->emc_txsr; - EMC(EMC_TXSRDLL) = params->emc_txsr_dll; - EMC(EMC_TCKE) = params->emc_tcke; - EMC(EMC_TCKESR) = params->emc_tckesr; - EMC(EMC_TPD) = params->emc_tpd; - EMC(EMC_TFAW) = params->emc_tfaw; - EMC(EMC_TRPAB) = params->emc_trpab; - EMC(EMC_TCLKSTABLE) = params->emc_tclkstable; - EMC(EMC_TCLKSTOP) = params->emc_tclkstop; - EMC(EMC_TREFBW) = params->emc_trefbw; - EMC(EMC_ODT_WRITE) = params->emc_odt_write; - EMC(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; - EMC(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; + EMC(EMC_PDEX2WR) = params->emc_pdex2wr; + EMC(EMC_PDEX2RD) = params->emc_pdex2rd; + EMC(EMC_PCHG2PDEN) = params->emc_pchg2pden; + EMC(EMC_ACT2PDEN) = params->emc_act2pden; + EMC(EMC_AR2PDEN) = params->emc_ar2pden; + EMC(EMC_RW2PDEN) = params->emc_rw2pden; + EMC(EMC_CKE2PDEN) = params->emc_cke2pden; + EMC(EMC_PDEX2CKE) = params->emc_pdex2che; + EMC(EMC_PDEX2MRR) = params->emc_pdex2mrr; + EMC(EMC_TXSR) = params->emc_txsr; + EMC(EMC_TXSRDLL) = params->emc_txsr_dll; + EMC(EMC_TCKE) = params->emc_tcke; + EMC(EMC_TCKESR) = params->emc_tckesr; + EMC(EMC_TPD) = params->emc_tpd; + EMC(EMC_TFAW) = params->emc_tfaw; + EMC(EMC_TRPAB) = params->emc_trpab; + EMC(EMC_TCLKSTABLE) = params->emc_tclkstable; + EMC(EMC_TCLKSTOP) = params->emc_tclkstop; + EMC(EMC_TREFBW) = params->emc_trefbw; + EMC(EMC_ODT_WRITE) = params->emc_odt_write; + EMC(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; + EMC(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; // Don't write CFG_ADR_EN (bit 1) here - lock bit written later. - EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; - EMC(EMC_CFG_RSV) = params->emc_cfg_rsv; + EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; + EMC(EMC_CFG_RSV) = params->emc_cfg_rsv; EMC(EMC_PMC_SCRATCH1) = params->emc_pmc_scratch1; EMC(EMC_PMC_SCRATCH2) = params->emc_pmc_scratch2; EMC(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3; EMC(EMC_ACPD_CONTROL) = params->emc_acpd_control; - EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; + EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; // Set pipe bypass enable bits before sending any DRAM commands. EMC(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000; @@ -610,7 +610,7 @@ break_nosleep: if (params->memory_type == MEMORY_TYPE_LPDDR4) { EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; + EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; } } @@ -658,16 +658,16 @@ break_nosleep: *(vu32 *)params->emc_bct_spare10 = params->emc_bct_spare11; // Write mode registers. - EMC(EMC_MRW2) = params->emc_mrw2; - EMC(EMC_MRW) = params->emc_mrw1; - EMC(EMC_MRW3) = params->emc_mrw3; - EMC(EMC_MRW4) = params->emc_mrw4; - EMC(EMC_MRW6) = params->emc_mrw6; + EMC(EMC_MRW2) = params->emc_mrw2; + EMC(EMC_MRW) = params->emc_mrw1; + EMC(EMC_MRW3) = params->emc_mrw3; + EMC(EMC_MRW4) = params->emc_mrw4; + EMC(EMC_MRW6) = params->emc_mrw6; EMC(EMC_MRW14) = params->emc_mrw14; - EMC(EMC_MRW8) = params->emc_mrw8; + EMC(EMC_MRW8) = params->emc_mrw8; EMC(EMC_MRW12) = params->emc_mrw12; - EMC(EMC_MRW9) = params->emc_mrw9; + EMC(EMC_MRW9) = params->emc_mrw9; EMC(EMC_MRW13) = params->emc_mrw13; if (params->emc_zcal_warm_cold_boot_enables & 1) @@ -696,7 +696,7 @@ break_nosleep: { EMC(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval; EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; + EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; } // Patch 7 using BCT spare variables. @@ -712,11 +712,11 @@ break_nosleep: EMC(EMC_REFCTRL) = params->emc_dev_select | 0x80000000; EMC(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control; - EMC(EMC_CFG_UPDATE) = params->emc_cfg_update; - EMC(EMC_CFG) = params->emc_cfg; - EMC(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; + EMC(EMC_CFG_UPDATE) = params->emc_cfg_update; + EMC(EMC_CFG) = params->emc_cfg; + EMC(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; EMC(EMC_FDPD_CTRL_CMD) = params->emc_fdpd_ctrl_cmd; - EMC(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; + EMC(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; // Write addr swizzle lock bit. EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | 2; @@ -734,8 +734,8 @@ break_nosleep: // Lock carveouts per BCT cfg. MC(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access; - MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; - MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; + MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; + MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; // Disable write access to a bunch of EMC registers. MC(MC_EMEM_CFG_ACCESS_CTRL) = 1; @@ -752,7 +752,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) // Program DPD3/DPD4 regs (coldboot path). // Enable sel_dpd on unused pins. - PMC(APBDEV_PMC_WEAK_BIAS) = (pmc_scratch1 & 0x1000) << 19 | (pmc_scratch1 & 0xFFF) << 18 | (pmc_scratch1 & 0x8000) << 15; + PMC(APBDEV_PMC_WEAK_BIAS) = (pmc_scratch1 & 0x1000) << 19 | (pmc_scratch1 & 0xFFF) << 18 | (pmc_scratch1 & 0x8000) << 15; PMC(APBDEV_PMC_IO_DPD3_REQ) = (pmc_scratch1 & 0x9FFF) + 0x80000000; usleep(params->pmc_io_dpd3_req_wait); @@ -766,7 +766,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) // Program CMD mapping. Required before brick mapping, else // we can't guarantee CK will be differential at all times. - EMC(EMC_FBIO_CFG7) = params->emc_fbio_cfg7; + EMC(EMC_FBIO_CFG7) = params->emc_fbio_cfg7; EMC(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0; EMC(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1; EMC(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2; @@ -779,7 +779,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0; EMC(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1; EMC(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2; - EMC(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte; + EMC(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte; // Program brick mapping. EMC(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0; @@ -806,7 +806,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) usleep(params->pmc_vddp_sel_wait + 2); // Ensure the regulators settle. // Set clock sources. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = params->emc_clock_source; + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = params->emc_clock_source; CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = params->emc_clock_source_dll; // Select EMC write mux. @@ -837,7 +837,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) *(vu32 *)params->emc_bct_spare6 = params->emc_bct_spare7; // Set pad controls. - EMC(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; + EMC(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; EMC(EMC_XM2COMPPADCTRL2) = params->emc_xm2_comp_pad_ctrl2; EMC(EMC_XM2COMPPADCTRL3) = params->emc_xm2_comp_pad_ctrl3; @@ -850,51 +850,51 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7; EMC(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8; - EMC(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; - EMC(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; - EMC(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; - EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive; + EMC(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; + EMC(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; + EMC(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; + EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive; EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common; - EMC(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; - EMC(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; + EMC(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; + EMC(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; - EMC(EMC_DLL_CFG_0) = params->emc_dll_cfg0; - EMC(EMC_DLL_CFG_1) = params->emc_dll_cfg1; + EMC(EMC_DLL_CFG_0) = params->emc_dll_cfg0; + EMC(EMC_DLL_CFG_1) = params->emc_dll_cfg1; EMC(EMC_CFG_DIG_DLL_1) = params->emc_cfg_dig_dll_1; EMC(EMC_DATA_BRLSHFT_0) = params->emc_data_brlshft0; EMC(EMC_DATA_BRLSHFT_1) = params->emc_data_brlshft1; - EMC(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; - EMC(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; - EMC(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; - EMC(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; - EMC(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; - EMC(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; + EMC(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; + EMC(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; + EMC(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; + EMC(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; + EMC(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; + EMC(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; EMC(EMC_QUSE_BRLSHFT_0) = params->emc_quse_brlshft0; EMC(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1; EMC(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2; EMC(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3; EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1; - EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; + EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; - EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; - EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2; + EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; + EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2; EMC(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd; - EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; - EMC(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; - EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; - EMC(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; - EMC(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; - EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl & 0xEFFFFFFF; + EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; + EMC(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; + EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; + EMC(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; + EMC(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; + EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl & 0xEFFFFFFF; - EMC(EMC_CFG_3) = params->emc_cfg3; - EMC(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; - EMC(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; - EMC(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; - EMC(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; - EMC(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; - EMC(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; + EMC(EMC_CFG_3) = params->emc_cfg3; + EMC(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; + EMC(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; + EMC(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; + EMC(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; + EMC(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; + EMC(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->emc_pmacro_tx_sel_clk_src0; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->emc_pmacro_tx_sel_clk_src1; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->emc_pmacro_tx_sel_clk_src2; @@ -909,33 +909,33 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_3) = params->emc_pmacro_perbit_fgcg_ctrl3; EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_4) = params->emc_pmacro_perbit_fgcg_ctrl4; EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_5) = params->emc_pmacro_perbit_fgcg_ctrl5; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_0) = params->emc_pmacro_perbit_rfu_ctrl0; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_1) = params->emc_pmacro_perbit_rfu_ctrl1; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_2) = params->emc_pmacro_perbit_rfu_ctrl2; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_3) = params->emc_pmacro_perbit_rfu_ctrl3; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_4) = params->emc_pmacro_perbit_rfu_ctrl4; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_5) = params->emc_pmacro_perbit_rfu_ctrl5; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_0) = params->emc_pmacro_perbit_rfu_ctrl0; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_1) = params->emc_pmacro_perbit_rfu_ctrl1; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_2) = params->emc_pmacro_perbit_rfu_ctrl2; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_3) = params->emc_pmacro_perbit_rfu_ctrl3; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_4) = params->emc_pmacro_perbit_rfu_ctrl4; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_5) = params->emc_pmacro_perbit_rfu_ctrl5; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_0) = params->emc_pmacro_perbit_rfu1_ctrl0; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_1) = params->emc_pmacro_perbit_rfu1_ctrl1; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_2) = params->emc_pmacro_perbit_rfu1_ctrl2; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_3) = params->emc_pmacro_perbit_rfu1_ctrl3; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_4) = params->emc_pmacro_perbit_rfu1_ctrl4; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_5) = params->emc_pmacro_perbit_rfu1_ctrl5; - EMC(EMC_PMACRO_DATA_PI_CTRL) = params->emc_pmacro_data_pi_ctrl; - EMC(EMC_PMACRO_CMD_PI_CTRL) = params->emc_pmacro_cmd_pi_ctrl; + EMC(EMC_PMACRO_DATA_PI_CTRL) = params->emc_pmacro_data_pi_ctrl; + EMC(EMC_PMACRO_CMD_PI_CTRL) = params->emc_pmacro_cmd_pi_ctrl; - EMC(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; - EMC(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; - EMC(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; - EMC(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; - EMC(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; - EMC(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; - EMC(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; - EMC(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; - EMC(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; + EMC(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; + EMC(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; + EMC(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; + EMC(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; + EMC(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; + EMC(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; + EMC(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; + EMC(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; + EMC(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; EMC(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0; EMC(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1; - EMC(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; + EMC(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; EMC(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->emc_pmacro_quse_ddll_rank0_0; EMC(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->emc_pmacro_quse_ddll_rank0_1; @@ -984,11 +984,11 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ib_ddll_long_dqs_rank1_2; EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ib_ddll_long_dqs_rank1_3; - EMC(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; - EMC(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; - EMC(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; - EMC(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; - EMC(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; + EMC(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; + EMC(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; + EMC(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; + EMC(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; + EMC(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; EMC(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0; EMC(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1; EMC(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2; @@ -1002,27 +1002,27 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) // Patch 4 to 6 using BCT spare secure variables. if (params->emc_bct_spare_secure6) - *(vu32 *)params->emc_bct_spare_secure6 = params->emc_bct_spare_secure7; + *(vu32 *)params->emc_bct_spare_secure6 = params->emc_bct_spare_secure7; if (params->emc_bct_spare_secure8) - *(vu32 *)params->emc_bct_spare_secure8 = params->emc_bct_spare_secure9; + *(vu32 *)params->emc_bct_spare_secure8 = params->emc_bct_spare_secure9; if (params->emc_bct_spare_secure10) *(vu32 *)params->emc_bct_spare_secure10 = params->emc_bct_spare_secure11; EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place. // Initialize MC VPR settings. - MC(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; - MC(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; - MC(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; - MC(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; - MC(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; + MC(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; + MC(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; + MC(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; + MC(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; + MC(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->mc_video_protect_gpu_override0; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->mc_video_protect_gpu_override1; // Program SDRAM geometry parameters. - MC(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; - MC(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; - MC(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; + MC(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; + MC(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; + MC(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; MC(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->mc_emem_adr_cfg_channel_mask; // Program bank swizzling. @@ -1034,44 +1034,44 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) MC(MC_EMEM_CFG) = params->mc_emem_cfg; // Program SEC carveout (base and size). - MC(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; - MC(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; + MC(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; + MC(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; MC(MC_SEC_CARVEOUT_SIZE_MB) = params->mc_sec_carveout_size_mb; // Program MTS carveout (base and size). - MC(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; - MC(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; + MC(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; + MC(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; MC(MC_MTS_CARVEOUT_SIZE_MB) = params->mc_mts_carveout_size_mb; // Program the memory arbiter. - MC(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; + MC(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; MC(MC_EMEM_ARB_OUTSTANDING_REQ) = params->mc_emem_arb_outstanding_req; - MC(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; + MC(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; MC(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->emc_emem_arb_refpb_bank_ctrl; - MC(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; - MC(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; - MC(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; - MC(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; - MC(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; - MC(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; - MC(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; - MC(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; - MC(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; - MC(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; - MC(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; - MC(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; - MC(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; - MC(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; - MC(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; - MC(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; - MC(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; - MC(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; - MC(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; - MC(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; - MC(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; - MC(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; - MC(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; - MC(MC_DA_CONFIG0) = params->mc_da_cfg0; + MC(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; + MC(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; + MC(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; + MC(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; + MC(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; + MC(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; + MC(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; + MC(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; + MC(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; + MC(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; + MC(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; + MC(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; + MC(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; + MC(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; + MC(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; + MC(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; + MC(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; + MC(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; + MC(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; + MC(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; + MC(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; + MC(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; + MC(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; + MC(MC_DA_CONFIG0) = params->mc_da_cfg0; MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update. @@ -1096,7 +1096,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1; EMC(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval; - EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; + EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; usleep(params->emc_auto_cal_wait); // Patch 5 using BCT spare variables. @@ -1106,99 +1106,100 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_AUTO_CAL_CONFIG9) = params->emc_auto_cal_config9; // Program EMC timing configuration. - EMC(EMC_CFG_2) = params->emc_cfg2; - EMC(EMC_CFG_PIPE) = params->emc_cfg_pipe; - EMC(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; - EMC(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; - EMC(EMC_CMDQ) = params->emc_cmd_q; - EMC(EMC_MC2EMCQ) = params->emc_mc2emc_q; - EMC(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; - EMC(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; - EMC(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; - EMC(EMC_RC) = params->emc_rc; - EMC(EMC_RFC) = params->emc_rfc; - EMC(EMC_RFCPB) = params->emc_rfc_pb; - EMC(EMC_REFCTRL2) = params->emc_ref_ctrl2; - EMC(EMC_RFC_SLR) = params->emc_rfc_slr; - EMC(EMC_RAS) = params->emc_ras; - EMC(EMC_RP) = params->emc_rp; - EMC(EMC_TPPD) = params->emc_tppd; - EMC(EMC_CTT) = params->emc_trtm; - EMC(EMC_FBIO_TWTM) = params->emc_twtm; - EMC(EMC_FBIO_TRATM) = params->emc_tratm; - EMC(EMC_FBIO_TWATM) = params->emc_twatm; - EMC(EMC_FBIO_TR2REF) = params->emc_tr2ref; - EMC(EMC_R2R) = params->emc_r2r; - EMC(EMC_W2W) = params->emc_w2w; - EMC(EMC_R2W) = params->emc_r2w; - EMC(EMC_W2R) = params->emc_w2r; - EMC(EMC_R2P) = params->emc_r2p; - EMC(EMC_W2P) = params->emc_w2p; - EMC(EMC_CCDMW) = params->emc_ccdmw; - EMC(EMC_RD_RCD) = params->emc_rd_rcd; - EMC(EMC_WR_RCD) = params->emc_wr_rcd; - EMC(EMC_RRD) = params->emc_rrd; - EMC(EMC_REXT) = params->emc_rext; - EMC(EMC_WEXT) = params->emc_wext; - EMC(EMC_WDV) = params->emc_wdv; - EMC(EMC_WDV_CHK) = params->emc_wdv_chk; - EMC(EMC_WSV) = params->emc_wsv; - EMC(EMC_WEV) = params->emc_wev; - EMC(EMC_WDV_MASK) = params->emc_wdv_mask; - EMC(EMC_WS_DURATION) = params->emc_ws_duration; - EMC(EMC_WE_DURATION) = params->emc_we_duration; - EMC(EMC_QUSE) = params->emc_quse; - EMC(EMC_QUSE_WIDTH) = params->emc_quse_width; - EMC(EMC_IBDLY) = params->emc_ibdly; - EMC(EMC_OBDLY) = params->emc_obdly; - EMC(EMC_EINPUT) = params->emc_einput; + EMC(EMC_CFG_2) = params->emc_cfg2; + EMC(EMC_CFG_PIPE) = params->emc_cfg_pipe; + EMC(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; + EMC(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; + EMC(EMC_CMDQ) = params->emc_cmd_q; + EMC(EMC_MC2EMCQ) = params->emc_mc2emc_q; + EMC(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; + EMC(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; + EMC(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; + EMC(EMC_RC) = params->emc_rc; + EMC(EMC_RFC) = params->emc_rfc; + EMC(EMC_RFCPB) = params->emc_rfc_pb; + EMC(EMC_REFCTRL2) = params->emc_ref_ctrl2; + EMC(EMC_RFC_SLR) = params->emc_rfc_slr; + EMC(EMC_RAS) = params->emc_ras; + EMC(EMC_RP) = params->emc_rp; + EMC(EMC_TPPD) = params->emc_tppd; + EMC(EMC_CTT) = params->emc_trtm; + EMC(EMC_FBIO_TWTM) = params->emc_twtm; + EMC(EMC_FBIO_TRATM) = params->emc_tratm; + EMC(EMC_FBIO_TWATM) = params->emc_twatm; + EMC(EMC_FBIO_TR2REF) = params->emc_tr2ref; + EMC(EMC_R2R) = params->emc_r2r; + EMC(EMC_W2W) = params->emc_w2w; + EMC(EMC_R2W) = params->emc_r2w; + EMC(EMC_W2R) = params->emc_w2r; + EMC(EMC_R2P) = params->emc_r2p; + EMC(EMC_W2P) = params->emc_w2p; + EMC(EMC_CCDMW) = params->emc_ccdmw; + EMC(EMC_RD_RCD) = params->emc_rd_rcd; + EMC(EMC_WR_RCD) = params->emc_wr_rcd; + EMC(EMC_RRD) = params->emc_rrd; + EMC(EMC_REXT) = params->emc_rext; + EMC(EMC_WEXT) = params->emc_wext; + EMC(EMC_WDV) = params->emc_wdv; + EMC(EMC_WDV_CHK) = params->emc_wdv_chk; + EMC(EMC_WSV) = params->emc_wsv; + EMC(EMC_WEV) = params->emc_wev; + EMC(EMC_WDV_MASK) = params->emc_wdv_mask; + EMC(EMC_WS_DURATION) = params->emc_ws_duration; + EMC(EMC_WE_DURATION) = params->emc_we_duration; + EMC(EMC_QUSE) = params->emc_quse; + EMC(EMC_QUSE_WIDTH) = params->emc_quse_width; + EMC(EMC_IBDLY) = params->emc_ibdly; + EMC(EMC_OBDLY) = params->emc_obdly; + EMC(EMC_EINPUT) = params->emc_einput; EMC(EMC_EINPUT_DURATION) = params->emc_einput_duration; - EMC(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; - EMC(EMC_PUTERM_WIDTH) = params->emc_puterm_width; - EMC(EMC_DBG) = params->emc_dbg; - EMC(EMC_QRST) = params->emc_qrst; - EMC(EMC_ISSUE_QRST) = 1; - EMC(EMC_ISSUE_QRST) = 0; - EMC(EMC_QSAFE) = params->emc_qsafe; - EMC(EMC_RDV) = params->emc_rdv; - EMC(EMC_RDV_MASK) = params->emc_rdv_mask; - EMC(EMC_RDV_EARLY) = params->emc_rdv_early; - EMC(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; - EMC(EMC_QPOP) = params->emc_qpop; - EMC(EMC_REFRESH) = params->emc_refresh; - EMC(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; + EMC(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; + EMC(EMC_PUTERM_WIDTH) = params->emc_puterm_width; + + EMC(EMC_DBG) = params->emc_dbg; + EMC(EMC_QRST) = params->emc_qrst; + EMC(EMC_ISSUE_QRST) = 1; + EMC(EMC_ISSUE_QRST) = 0; + EMC(EMC_QSAFE) = params->emc_qsafe; + EMC(EMC_RDV) = params->emc_rdv; + EMC(EMC_RDV_MASK) = params->emc_rdv_mask; + EMC(EMC_RDV_EARLY) = params->emc_rdv_early; + EMC(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; + EMC(EMC_QPOP) = params->emc_qpop; + EMC(EMC_REFRESH) = params->emc_refresh; + EMC(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; EMC(EMC_PRE_REFRESH_REQ_CNT) = params->emc_prerefresh_req_cnt; - EMC(EMC_PDEX2WR) = params->emc_pdex2wr; - EMC(EMC_PDEX2RD) = params->emc_pdex2rd; - EMC(EMC_PCHG2PDEN) = params->emc_pchg2pden; - EMC(EMC_ACT2PDEN) = params->emc_act2pden; - EMC(EMC_AR2PDEN) = params->emc_ar2pden; - EMC(EMC_RW2PDEN) = params->emc_rw2pden; - EMC(EMC_CKE2PDEN) = params->emc_cke2pden; - EMC(EMC_PDEX2CKE) = params->emc_pdex2che; - EMC(EMC_PDEX2MRR) = params->emc_pdex2mrr; - EMC(EMC_TXSR) = params->emc_txsr; - EMC(EMC_TXSRDLL) = params->emc_txsr_dll; - EMC(EMC_TCKE) = params->emc_tcke; - EMC(EMC_TCKESR) = params->emc_tckesr; - EMC(EMC_TPD) = params->emc_tpd; - EMC(EMC_TFAW) = params->emc_tfaw; - EMC(EMC_TRPAB) = params->emc_trpab; - EMC(EMC_TCLKSTABLE) = params->emc_tclkstable; - EMC(EMC_TCLKSTOP) = params->emc_tclkstop; - EMC(EMC_TREFBW) = params->emc_trefbw; - EMC(EMC_ODT_WRITE) = params->emc_odt_write; - EMC(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; - EMC(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; + EMC(EMC_PDEX2WR) = params->emc_pdex2wr; + EMC(EMC_PDEX2RD) = params->emc_pdex2rd; + EMC(EMC_PCHG2PDEN) = params->emc_pchg2pden; + EMC(EMC_ACT2PDEN) = params->emc_act2pden; + EMC(EMC_AR2PDEN) = params->emc_ar2pden; + EMC(EMC_RW2PDEN) = params->emc_rw2pden; + EMC(EMC_CKE2PDEN) = params->emc_cke2pden; + EMC(EMC_PDEX2CKE) = params->emc_pdex2che; + EMC(EMC_PDEX2MRR) = params->emc_pdex2mrr; + EMC(EMC_TXSR) = params->emc_txsr; + EMC(EMC_TXSRDLL) = params->emc_txsr_dll; + EMC(EMC_TCKE) = params->emc_tcke; + EMC(EMC_TCKESR) = params->emc_tckesr; + EMC(EMC_TPD) = params->emc_tpd; + EMC(EMC_TFAW) = params->emc_tfaw; + EMC(EMC_TRPAB) = params->emc_trpab; + EMC(EMC_TCLKSTABLE) = params->emc_tclkstable; + EMC(EMC_TCLKSTOP) = params->emc_tclkstop; + EMC(EMC_TREFBW) = params->emc_trefbw; + EMC(EMC_ODT_WRITE) = params->emc_odt_write; + EMC(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; + EMC(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; // Don't write CFG_ADR_EN (bit 1) here - lock bit written later. - EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; - EMC(EMC_CFG_RSV) = params->emc_cfg_rsv; + EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; + EMC(EMC_CFG_RSV) = params->emc_cfg_rsv; EMC(EMC_PMC_SCRATCH1) = params->emc_pmc_scratch1; EMC(EMC_PMC_SCRATCH2) = params->emc_pmc_scratch2; EMC(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3; EMC(EMC_ACPD_CONTROL) = params->emc_acpd_control; - EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; + EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; EMC(EMC_PMACRO_DSR_VTTGEN_CTRL0) = params->emc_pmacro_dsr_vttgen_ctrl0; // Set pipe bypass enable bits before sending any DRAM commands. @@ -1234,7 +1235,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) if (params->memory_type == MEMORY_TYPE_LPDDR4) { EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; + EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; } } @@ -1282,16 +1283,16 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) *(vu32 *)params->emc_bct_spare10 = params->emc_bct_spare11; // Write mode registers. - EMC(EMC_MRW2) = params->emc_mrw2; - EMC(EMC_MRW) = params->emc_mrw1; - EMC(EMC_MRW3) = params->emc_mrw3; - EMC(EMC_MRW4) = params->emc_mrw4; - EMC(EMC_MRW6) = params->emc_mrw6; + EMC(EMC_MRW2) = params->emc_mrw2; + EMC(EMC_MRW) = params->emc_mrw1; + EMC(EMC_MRW3) = params->emc_mrw3; + EMC(EMC_MRW4) = params->emc_mrw4; + EMC(EMC_MRW6) = params->emc_mrw6; EMC(EMC_MRW14) = params->emc_mrw14; - EMC(EMC_MRW8) = params->emc_mrw8; + EMC(EMC_MRW8) = params->emc_mrw8; EMC(EMC_MRW12) = params->emc_mrw12; - EMC(EMC_MRW9) = params->emc_mrw9; + EMC(EMC_MRW9) = params->emc_mrw9; EMC(EMC_MRW13) = params->emc_mrw13; if (params->emc_zcal_warm_cold_boot_enables & 1) @@ -1328,7 +1329,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) { EMC(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval; EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; + EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; } // Patch 7 using BCT spare variables. @@ -1344,10 +1345,10 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_REFCTRL) = params->emc_dev_select | 0x80000000; EMC(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control; - EMC(EMC_CFG) = params->emc_cfg; - EMC(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; + EMC(EMC_CFG) = params->emc_cfg; + EMC(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; EMC(EMC_FDPD_CTRL_CMD) = params->emc_fdpd_ctrl_cmd; - EMC(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; + EMC(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; // Write addr swizzle lock bit. EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | 2; @@ -1367,8 +1368,8 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) // Lock carveouts per BCT cfg. MC(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access; - MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; - MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; + MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; + MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; // Disable write access to a bunch of EMC registers. MC(MC_EMEM_CFG_ACCESS_CTRL) = 1; @@ -1469,9 +1470,9 @@ static void _sdram_init_t210() // Turn on MEM IO Power. PMC(APBDEV_PMC_NO_IOPOWER) = params->pmc_no_io_power; - PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short; + PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short; - PMC(APBDEV_PMC_DDR_CNTRL) = params->pmc_ddr_ctrl; + PMC(APBDEV_PMC_DDR_CNTRL) = params->pmc_ddr_ctrl; // Patch 1 using BCT spare variables if (params->emc_bct_spare0) @@ -1490,9 +1491,9 @@ static void _sdram_init_t210b01() // Turn on MEM IO Power. PMC(APBDEV_PMC_NO_IOPOWER) = params->pmc_no_io_power; - PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short; + PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short; - PMC(APBDEV_PMC_DDR_CNTRL) = params->pmc_ddr_ctrl; + PMC(APBDEV_PMC_DDR_CNTRL) = params->pmc_ddr_ctrl; // Patch 1 using BCT spare variables if (params->emc_bct_spare0) diff --git a/bdk/mem/smmu.c b/bdk/mem/smmu.c index 9c2b8e4..8bc9aac 100644 --- a/bdk/mem/smmu.c +++ b/bdk/mem/smmu.c @@ -71,18 +71,19 @@ void smmu_flush_all() { MC(MC_SMMU_PTC_FLUSH) = 0; smmu_flush_regs(); + MC(MC_SMMU_TLB_FLUSH) = 0; smmu_flush_regs(); } void smmu_init(u32 secmon_base) { - MC(MC_SMMU_PTB_ASID) = 0; - MC(MC_SMMU_PTB_DATA) = 0; + MC(MC_SMMU_PTB_ASID) = 0; + MC(MC_SMMU_PTB_DATA) = 0; MC(MC_SMMU_TLB_CONFIG) = 0x30000030; MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F; - MC(MC_SMMU_PTC_FLUSH) = 0; - MC(MC_SMMU_TLB_FLUSH) = 0; + MC(MC_SMMU_PTC_FLUSH) = 0; + MC(MC_SMMU_TLB_FLUSH) = 0; // Set the secmon address *(u32 *)(smmu_payload + 0x30) = secmon_base; @@ -164,8 +165,8 @@ u32 *smmu_init_for_tsec() void smmu_deinit_for_tsec() { - MC(MC_SMMU_PTB_ASID) = 1; - MC(MC_SMMU_PTB_DATA) = 0; + MC(MC_SMMU_PTB_ASID) = 1; + MC(MC_SMMU_PTB_DATA) = 0; MC(MC_SMMU_TSEC_ASID) = 0; smmu_flush_regs(); } diff --git a/bdk/rtc/max77620-rtc.c b/bdk/rtc/max77620-rtc.c index 164df75..33f6fcc 100644 --- a/bdk/rtc/max77620-rtc.c +++ b/bdk/rtc/max77620-rtc.c @@ -35,7 +35,7 @@ void max77620_rtc_get_time(rtc_time_t *time) // Get time. time->sec = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_SEC_REG) & 0x7F; time->min = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MIN_REG) & 0x7F; - u8 hour = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_HOUR_REG); + u8 hour = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_HOUR_REG); time->hour = hour & 0x1F; if (!(val & MAX77620_RTC_24H) && (hour & MAX77620_RTC_HOUR_PM_MASK)) @@ -53,7 +53,7 @@ void max77620_rtc_get_time(rtc_time_t *time) } // Get date. - time->day = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_DATE_REG) & 0x1f; + time->day = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_DATE_REG) & 0x1f; time->month = (i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MONTH_REG) & 0xF) - 1; time->year = (i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_YEAR_REG) & 0x7F) + 2000; } @@ -82,9 +82,9 @@ void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time) u32 tmp, edays, year, month, day; // Set time. - time->sec = epoch % 60; + time->sec = epoch % 60; epoch /= 60; - time->min = epoch % 60; + time->min = epoch % 60; epoch /= 60; time->hour = epoch % 24; epoch /= 24; @@ -106,7 +106,7 @@ void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time) } else { - year -= 4715; + year -= 4715; month -= 13; } @@ -135,7 +135,7 @@ u32 max77620_rtc_date_to_epoch(const rtc_time_t *time) year--; } - epoch = (365 * year) + (year >> 2) - (year / 100) + (year / 400); // Years to days. + epoch = (365 * year) + (year >> 2) - (year / 100) + (year / 400); // Years to days. epoch += (30 * month) + (3 * (month + 1) / 5) + time->day; // Months to days. epoch -= 719561; // Epoch time is 1/1/1970. diff --git a/bdk/sec/se.c b/bdk/sec/se.c index dfacddf..79ae4ad 100644 --- a/bdk/sec/se.c +++ b/bdk/sec/se.c @@ -70,7 +70,7 @@ static void _gf256_mul_x_le(void *block) static void _se_ll_init(se_ll_t *ll, u32 addr, u32 size) { - ll->num = 0; + ll->num = 0; ll->addr = addr; ll->size = size; } @@ -90,9 +90,10 @@ static int _se_wait() ; // Check for errors. - if ((SE(SE_INT_STATUS_REG) & SE_INT_ERR_STAT) || + if ((SE(SE_INT_STATUS_REG) & SE_INT_ERR_STAT) || (SE(SE_STATUS_REG) & SE_STATUS_STATE_MASK) != SE_STATUS_STATE_IDLE || - SE(SE_ERR_STATUS_REG) != 0) + (SE(SE_ERR_STATUS_REG) != 0) + ) { return 0; } @@ -206,7 +207,7 @@ void se_rsa_acc_ctrl(u32 rs, u32 flags) { if (flags & SE_RSA_KEY_TBL_DIS_KEY_ACCESS_FLAG) SE(SE_RSA_KEYTABLE_ACCESS_REG + 4 * rs) = - (((flags >> 4) & SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG) |(flags & SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG)) ^ + (((flags >> 4) & SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG) | (flags & SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG)) ^ SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_USE_FLAG; if (flags & SE_RSA_KEY_LOCK_FLAG) SE(SE_RSA_SECURITY_PERKEY_REG) &= ~BIT(rs); @@ -283,8 +284,8 @@ void se_aes_iv_clear(u32 ks) int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input) { - SE(SE_CONFIG_REG) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_KEYTABLE); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT); + SE(SE_CONFIG_REG) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_KEYTABLE); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT); SE(SE_CRYPTO_BLOCK_COUNT_REG) = 1 - 1; SE(SE_CRYPTO_KEYTABLE_DST_REG) = SE_KEYTABLE_DST_KEY_INDEX(ks_dst) | SE_KEYTABLE_DST_WORD_QUAD(KEYS_0_3); @@ -312,14 +313,14 @@ int se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, if (enc) { SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) | - SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_XOR_POS(XOR_TOP); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) | + SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_XOR_POS(XOR_TOP); } else { SE(SE_CONFIG_REG) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVMEM) | - SE_CRYPTO_CORE_SEL(CORE_DECRYPT) | SE_CRYPTO_XOR_POS(XOR_BOTTOM); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVMEM) | + SE_CRYPTO_CORE_SEL(CORE_DECRYPT) | SE_CRYPTO_XOR_POS(XOR_BOTTOM); } SE(SE_CRYPTO_BLOCK_COUNT_REG) = (src_size >> 4) - 1; return _se_execute_oneshot(SE_OP_START, dst, dst_size, src, src_size); @@ -334,8 +335,9 @@ int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_s { SE(SE_SPARE_REG) = SE_ECO(SE_ERRATA_FIX_ENABLE); SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | - SE_CRYPTO_XOR_POS(XOR_BOTTOM) | SE_CRYPTO_INPUT_SEL(INPUT_LNR_CTR) | SE_CRYPTO_CTR_CNTN(1); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | + SE_CRYPTO_XOR_POS(XOR_BOTTOM) | SE_CRYPTO_INPUT_SEL(INPUT_LNR_CTR) | + SE_CRYPTO_CTR_CNTN(1); _se_aes_ctr_set(ctr); u32 src_size_aligned = src_size & 0xFFFFFFF0; @@ -549,9 +551,9 @@ int se_calc_sha256_finalize(void *hash, u32 *msg_left) int se_gen_prng128(void *dst) { // Setup config for X931 PRNG. - SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_HASH(HASH_DISABLE) | SE_CRYPTO_XOR_POS(XOR_BYPASS) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM); - SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_SRC(SRC_ENTROPY) | SE_RNG_CONFIG_MODE(MODE_NORMAL); + SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_HASH(HASH_DISABLE) | SE_CRYPTO_XOR_POS(XOR_BYPASS) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM); + SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_SRC(SRC_ENTROPY) | SE_RNG_CONFIG_MODE(MODE_NORMAL); //SE(SE_RNG_SRC_CONFIG_REG) = // SE_RNG_SRC_CONFIG_ENTR_SRC(RO_ENTR_ENABLE) | SE_RNG_SRC_CONFIG_ENTR_SRC_LOCK(RO_ENTR_LOCK_ENABLE); SE(SE_RNG_RESEED_INTERVAL_REG) = 1; @@ -567,9 +569,9 @@ void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize) u8 *aligned_buf = (u8 *)ALIGN((u32)buf, 0x40); // Set Secure Random Key. - SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_SRK); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(0) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM); - SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_SRC(SRC_ENTROPY) | SE_RNG_CONFIG_MODE(MODE_FORCE_RESEED); + SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_SRK); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(0) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM); + SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_SRC(SRC_ENTROPY) | SE_RNG_CONFIG_MODE(MODE_FORCE_RESEED); SE(SE_CRYPTO_LAST_BLOCK) = 0; _se_execute_oneshot(SE_OP_START, NULL, 0, NULL, 0); @@ -579,7 +581,7 @@ void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize) for (u32 i = 0; i < SE_AES_KEYSLOT_COUNT; i++) { SE(SE_CONTEXT_SAVE_CONFIG_REG) = SE_CONTEXT_SRC(AES_KEYTABLE) | SE_KEYTABLE_DST_KEY_INDEX(i) | - SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_0_3); + SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_0_3); SE(SE_CRYPTO_LAST_BLOCK) = 0; _se_execute_oneshot(SE_OP_CTX_SAVE, aligned_buf, SE_AES_BLOCK_SIZE, NULL, 0); @@ -588,7 +590,7 @@ void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize) if (keysize > SE_KEY_128_SIZE) { SE(SE_CONTEXT_SAVE_CONFIG_REG) = SE_CONTEXT_SRC(AES_KEYTABLE) | SE_KEYTABLE_DST_KEY_INDEX(i) | - SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_4_7); + SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_4_7); SE(SE_CRYPTO_LAST_BLOCK) = 0; _se_execute_oneshot(SE_OP_CTX_SAVE, aligned_buf, SE_AES_BLOCK_SIZE, NULL, 0); diff --git a/bdk/sec/tsec.c b/bdk/sec/tsec.c index 0097c09..3ff9974 100644 --- a/bdk/sec/tsec.c +++ b/bdk/sec/tsec.c @@ -20,16 +20,17 @@ #include "tsec.h" #include "tsec_t210.h" +#include +#include +#include +#include #include #include #include #include #include -#include #include -#include -#include -#include +#include // #include @@ -57,9 +58,9 @@ static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offse else cmd = TSEC_DMATRFCMD_IMEM; // DMA IMEM (Instruction memmory) - TSEC(TSEC_DMATRFMOFFS) = i_offset; + TSEC(TSEC_DMATRFMOFFS) = i_offset; TSEC(TSEC_DMATRFFBOFFS) = pa_offset; - TSEC(TSEC_DMATRFCMD) = cmd; + TSEC(TSEC_DMATRFCMD) = cmd; return _tsec_dma_wait_idle(); } @@ -83,7 +84,6 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) clock_enable_sor0(); clock_enable_sor1(); clock_enable_kfuse(); - kfuse_wait_ready(); if (type == TSEC_FW_TYPE_NEW) @@ -102,16 +102,16 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) TSEC(TSEC_DMACTL) = 0; TSEC(TSEC_IRQMSET) = TSEC_IRQMSET_EXT(0xFF) | - TSEC_IRQMSET_WDTMR | - TSEC_IRQMSET_HALT | - TSEC_IRQMSET_EXTERR | - TSEC_IRQMSET_SWGEN0 | + TSEC_IRQMSET_WDTMR | + TSEC_IRQMSET_HALT | + TSEC_IRQMSET_EXTERR | + TSEC_IRQMSET_SWGEN0 | TSEC_IRQMSET_SWGEN1; TSEC(TSEC_IRQDEST) = TSEC_IRQDEST_EXT(0xFF) | - TSEC_IRQDEST_HALT | - TSEC_IRQDEST_EXTERR | - TSEC_IRQDEST_SWGEN0 | + TSEC_IRQDEST_HALT | + TSEC_IRQDEST_EXTERR | + TSEC_IRQDEST_SWGEN0 | TSEC_IRQDEST_SWGEN1; TSEC(TSEC_ITFEN) = TSEC_ITFEN_CTXEN | TSEC_ITFEN_MTHDEN; if (!_tsec_dma_wait_idle()) @@ -128,6 +128,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) fwbuf = (u8 *)malloc(SZ_16K); u8 *fwbuf_aligned = (u8 *)ALIGN((u32)fwbuf, 0x100); memcpy(fwbuf_aligned, tsec_ctxt->fw, tsec_ctxt->size); + TSEC(TSEC_DMATRFBASE) = (u32)fwbuf_aligned >> 8; } @@ -180,7 +181,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) mc = page_alloc(1); memcpy(mc, (void *)MC_BASE, SZ_PAGE); mc[MC_IRAM_BOM / 4] = 0; - mc[MC_IRAM_TOM / 4] = 0x80000000; + mc[MC_IRAM_TOM / 4] = DRAM_START; smmu_map(pdir, MC_BASE, (u32)mc, 1, _READABLE | _NONSECURE); // IRAM @@ -197,10 +198,10 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) // Execute firmware. HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0x34C2E1DA; - TSEC(TSEC_STATUS) = 0; + TSEC(TSEC_STATUS) = 0; TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1. - TSEC(TSEC_BOOTVEC) = 0; - TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU; + TSEC(TSEC_BOOTVEC) = 0; + TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU; if (type == TSEC_FW_TYPE_EMU) { @@ -279,10 +280,10 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB); buf[2] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB); buf[3] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB); - SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB) = 0; + SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB) = 0; SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB) = 0; - SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB) = 0; - SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB) = 0; + SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB) = 0; + SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB) = 0; memcpy(tsec_keys, &buf, SE_KEY_128_SIZE); } diff --git a/bdk/soc/bpmp.c b/bdk/soc/bpmp.c index a3c18aa..03558d9 100644 --- a/bdk/soc/bpmp.c +++ b/bdk/soc/bpmp.c @@ -150,8 +150,8 @@ void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply) if (entry->enable) { mmu_entry->start_addr = ALIGN(entry->start_addr, BPMP_MMU_CACHE_LINE_SIZE); - mmu_entry->end_addr = ALIGN_DOWN(entry->end_addr, BPMP_MMU_CACHE_LINE_SIZE); - mmu_entry->attr = entry->attr; + mmu_entry->end_addr = ALIGN_DOWN(entry->end_addr, BPMP_MMU_CACHE_LINE_SIZE); + mmu_entry->attr = entry->attr; BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= BIT(idx); @@ -166,9 +166,9 @@ void bpmp_mmu_enable() return; // Init BPMP MMU. - BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_INIT; + BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_INIT; BPMP_CACHE_CTRL(BPMP_CACHE_MMU_FALLBACK_ENTRY) = MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC; // RWX for non-defined regions. - BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CFG) = MMU_CFG_SEQ_EN | MMU_CFG_TLB_EN | MMU_CFG_ABORT_STORE_LAST; + BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CFG) = MMU_CFG_SEQ_EN | MMU_CFG_TLB_EN | MMU_CFG_ABORT_STORE_LAST; // Init BPMP MMU entries. BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) = 0; diff --git a/bdk/soc/ccplex.c b/bdk/soc/ccplex.c index d7f6252..536769b 100644 --- a/bdk/soc/ccplex.c +++ b/bdk/soc/ccplex.c @@ -62,12 +62,12 @@ void ccplex_boot_cpu0(u32 entry) // Configure MSELECT source and enable clock to 102MHz. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6; - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_MSELECT); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_MSELECT); // Configure initial CPU clock frequency and enable clock. CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888; // PLLX_OUT0_LJ. CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000; - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_CPUG); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_CPUG); clock_enable_coresight(); @@ -100,7 +100,7 @@ void ccplex_boot_cpu0(u32 entry) // MC(MC_TZ_SECURITY_CTRL) = 1; // Clear MSELECT reset. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_CLR) = BIT(CLK_V_MSELECT); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_CLR) = BIT(CLK_V_MSELECT); // Clear NONCPU reset. CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000; // Clear CPU0 reset. diff --git a/bdk/soc/clock.c b/bdk/soc/clock.c index ad2d1fa..abf3564 100644 --- a/bdk/soc/clock.c +++ b/bdk/soc/clock.c @@ -60,55 +60,55 @@ static const clock_t _clock_i2c[] = { }; static clock_t _clock_se = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, CLK_V_SE, 0, 0 // 408MHz. + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, CLK_V_SE, 0, 0 // 408MHz. }; static clock_t _clock_tzram = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, CLK_V_TZRAM, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, CLK_V_TZRAM, 0, 0 }; static clock_t _clock_host1x = { - CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, CLK_L_HOST1X, 4, 3 // 163.2MHz. + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, CLK_L_HOST1X, 4, 3 // 163.2MHz. }; static clock_t _clock_tsec = { - CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, CLK_U_TSEC, 0, 2 // 204MHz. + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, CLK_U_TSEC, 0, 2 // 204MHz. }; static clock_t _clock_nvdec = { - CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, 0x698, CLK_Y_NVDEC, 4, 0 // 408 MHz. + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC, CLK_Y_NVDEC, 4, 0 // 408 MHz. }; static clock_t _clock_nvjpg = { - CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, 0x69C, CLK_Y_NVJPG, 4, 0 // 408 MHz. + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG, CLK_Y_NVJPG, 4, 0 // 408 MHz. }; static clock_t _clock_sor_safe = { - CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, CLK_Y_SOR_SAFE, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, CLK_Y_SOR_SAFE, 0, 0 }; static clock_t _clock_sor0 = { - CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NOT_USED, CLK_X_SOR0, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NOT_USED, CLK_X_SOR0, 0, 0 }; static clock_t _clock_sor1 = { - CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, CLK_X_SOR1, 0, 2 // 204MHz. + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, CLK_X_SOR1, 0, 2 // 204MHz. }; static clock_t _clock_kfuse = { - CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_KFUSE, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_KFUSE, 0, 0 }; static clock_t _clock_cl_dvfs = { - CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, CLK_W_DVFS, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, CLK_W_DVFS, 0, 0 }; static clock_t _clock_coresight = { - CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, CLK_U_CSITE, 0, 4 // 136MHz. + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, CLK_U_CSITE, 0, 4 // 136MHz. }; static clock_t _clock_pwm = { - CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, CLK_L_PWM, 6, 4 // Fref: 6.4MHz. HOS: PLLP / 54 = 7.55MHz. + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, CLK_L_PWM, 6, 4 // Fref: 6.4MHz. HOS: PLLP / 54 = 7.55MHz. }; static clock_t _clock_sdmmc_legacy_tm = { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, CLK_Y_SDMMC_LEGACY_TM, 4, 66 }; static clock_t _clock_apbdma = { - CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_APBDMA, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_APBDMA, 0, 0 }; static clock_t _clock_ahbdma = { - CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_AHBDMA, 0, 0 + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_AHBDMA, 0, 0 }; static clock_t _clock_actmon = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON, CLK_V_ACTMON, 6, 0 // 19.2MHz. + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON, CLK_V_ACTMON, 6, 0 // 19.2MHz. }; static clock_t _clock_extperiph1 = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1, CLK_V_EXTPERIPH1, 0, 0 diff --git a/bdk/soc/clock.h b/bdk/soc/clock.h index 9b974f6..add38f7 100644 --- a/bdk/soc/clock.h +++ b/bdk/soc/clock.h @@ -157,6 +157,8 @@ #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664 #define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL 0x66C #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694 +#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC 0x698 +#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG 0x69C #define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0 #define CLK_RST_CONTROLLER_CLK_SOURCE_APE 0x6C0 #define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK 0x6CC diff --git a/bdk/soc/hw_init.c b/bdk/soc/hw_init.c index 754309d..3631714 100644 --- a/bdk/soc/hw_init.c +++ b/bdk/soc/hw_init.c @@ -72,24 +72,24 @@ u32 hw_get_chip_id() static void _config_oscillators() { CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2. - SYSCTR0(SYSCTR0_CNTFID0) = 19200000; // Set counter frequency. - TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m. - CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; // Set OSC to 38.4MHz and drive strength. + SYSCTR0(SYSCTR0_CNTFID0) = 19200000; // Set counter frequency. + TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m. + CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; // Set OSC to 38.4MHz and drive strength. PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; // Set LP0 OSC drive strength. PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | PMC_OSC_EDPD_OVER_OSC_CTRL_OVER; - PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN; - PMC(APB_MISC_GP_ASDBGREG) = (PMC(APB_MISC_GP_ASDBGREG) & 0xFCFFFFFF) | (2 << 24); // CFG2TMC_RAM_SVOP_PDP. + PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN; + PMC(APB_MISC_GP_ASDBGREG) = (PMC(APB_MISC_GP_ASDBGREG) & 0xFCFFFFFF) | (2 << 24); // CFG2TMC_RAM_SVOP_PDP. - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1. - CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable. + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable. PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz) - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set BPMP/SCLK div to 1. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set BPMP/SCLK source to Run and PLLP_OUT2 (204MHz). + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set BPMP/SCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set BPMP/SCLK source to Run and PLLP_OUT2 (204MHz). CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1. - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3. + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3. } // The uart is skipped for Copper, Hoag and Calcio. Used in Icosa, Iowa and Aula. @@ -242,9 +242,9 @@ static void _mbist_workaround() // Set child clock sources. CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF; // Disable PLLD and set reference clock and csi clock. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF; // Set SOR1 to automatic muxing of safe clock (24MHz) or SOR1 clk switch. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. } static void _config_se_brom() @@ -404,9 +404,9 @@ void hw_init() // Power on T210B01 shadow TZRAM and lock the reg. if (!tegra_t210) { - PMC(APBDEV_PMC_TZRAM_PWR_CNTRL) &= ~PMC_TZRAM_PWR_CNTRL_SD; + PMC(APBDEV_PMC_TZRAM_PWR_CNTRL) &= ~PMC_TZRAM_PWR_CNTRL_SD; PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ; - PMC(APBDEV_PMC_TZRAM_SEC_DISABLE) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ; + PMC(APBDEV_PMC_TZRAM_SEC_DISABLE) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ; } // Initialize External memory controller and configure DRAM parameters. diff --git a/bdk/soc/irq.c b/bdk/soc/irq.c index b44e208..380cfe1 100644 --- a/bdk/soc/irq.c +++ b/bdk/soc/irq.c @@ -71,7 +71,7 @@ static void _irq_disable_and_ack_all() { u32 enabled_irqs = ICTLR(ctrl_idx, PRI_ICTLR_COP_IER); ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_CLR) = enabled_irqs; - ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = enabled_irqs; + ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = enabled_irqs; } } @@ -90,10 +90,10 @@ void irq_free(u32 irq) { if (irqs[idx].irq == irq && irqs[idx].handler) { - irqs[idx].irq = 0; + irqs[idx].irq = 0; irqs[idx].handler = NULL; - irqs[idx].data = NULL; - irqs[idx].flags = 0; + irqs[idx].data = NULL; + irqs[idx].flags = 0; _irq_disable_source(irq); } @@ -108,10 +108,10 @@ static void _irq_free_all() { _irq_disable_source(irqs[idx].irq); - irqs[idx].irq = 0; + irqs[idx].irq = 0; irqs[idx].handler = NULL; - irqs[idx].data = NULL; - irqs[idx].flags = 0; + irqs[idx].data = NULL; + irqs[idx].flags = 0; } } } @@ -220,10 +220,10 @@ irq_status_t irq_request(u32 irq, irq_handler_t handler, void *data, irq_flags_t DPRINTF("Registered handler, IRQ: %d, Slot: %d\n", irq, idx); DPRINTF("Handler: %08p, Flags: %x\n", (u32)handler, flags); - irqs[idx].irq = irq; + irqs[idx].irq = irq; irqs[idx].handler = handler; - irqs[idx].data = data; - irqs[idx].flags = flags; + irqs[idx].data = data; + irqs[idx].flags = flags; _irq_enable_source(irq); diff --git a/bdk/soc/pinmux.c b/bdk/soc/pinmux.c index 80d25c8..288a4f7 100644 --- a/bdk/soc/pinmux.c +++ b/bdk/soc/pinmux.c @@ -19,8 +19,8 @@ void pinmux_config_uart(u32 idx) { - PINMUX_AUX(PINMUX_AUX_UARTX_TX(idx)) = 0; - PINMUX_AUX(PINMUX_AUX_UARTX_RX(idx)) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; + PINMUX_AUX(PINMUX_AUX_UARTX_TX(idx)) = 0; + PINMUX_AUX(PINMUX_AUX_UARTX_RX(idx)) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; PINMUX_AUX(PINMUX_AUX_UARTX_RTS(idx)) = 0; PINMUX_AUX(PINMUX_AUX_UARTX_CTS(idx)) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; } diff --git a/bdk/soc/uart.c b/bdk/soc/uart.c index 7cb7671..228ac01 100644 --- a/bdk/soc/uart.c +++ b/bdk/soc/uart.c @@ -40,21 +40,27 @@ void uart_init(u32 idx, u32 baud, u32 mode) // Misc settings. u32 div = clk_type ? ((8 * baud + 408000000) / (16 * baud)) : 1; // DIV_ROUND_CLOSEST. uart->UART_IER_DLAB = 0; // Disable interrupts. - uart->UART_LCR = UART_LCR_DLAB | UART_LCR_WORD_LENGTH_8; // Enable DLAB & set 8n1 mode. - uart->UART_THR_DLAB = (u8)div; // Divisor latch LSB. + uart->UART_LCR = UART_LCR_DLAB | UART_LCR_WORD_LENGTH_8; // Enable DLAB & set 8n1 mode. + uart->UART_THR_DLAB = (u8)div; // Divisor latch LSB. uart->UART_IER_DLAB = (u8)(div >> 8); // Divisor latch MSB. + // Disable DLAB and set STOP bits setting if applicable. uart->UART_LCR = uart_lcr_stop | UART_LCR_WORD_LENGTH_8; (void)uart->UART_SPR; - // Setup and flush fifo. + // Enable fifo. uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO; (void)uart->UART_SPR; usleep(20); - uart->UART_MCR = 0; // Disable hardware flow control. + + // Disable hardware flow control. + uart->UART_MCR = 0; usleep(96); + + // Clear tx/rx fifos. uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO | UART_IIR_FCR_TX_CLR | UART_IIR_FCR_RX_CLR; + // Set hardware flow control. uart->UART_MCR = mode; // Wait 3 symbols for baudrate change. diff --git a/bdk/storage/emmc.c b/bdk/storage/emmc.c index a344a94..f168152 100644 --- a/bdk/storage/emmc.c +++ b/bdk/storage/emmc.c @@ -150,10 +150,10 @@ void emmc_gpt_parse(link_t *gpt) if (gpt_buf->entries[i].lba_start < gpt_buf->header.first_use_lba) continue; - part->index = i; + part->index = i; part->lba_start = gpt_buf->entries[i].lba_start; - part->lba_end = gpt_buf->entries[i].lba_end; - part->attrs = gpt_buf->entries[i].attrs; + part->lba_end = gpt_buf->entries[i].lba_end; + part->attrs = gpt_buf->entries[i].attrs; // ASCII conversion. Copy only the LSByte of the UTF-16LE name. for (u32 j = 0; j < 36; j++) diff --git a/bdk/storage/sdmmc.c b/bdk/storage/sdmmc.c index 0f0773d..f3e6cbc 100644 --- a/bdk/storage/sdmmc.c +++ b/bdk/storage/sdmmc.c @@ -180,11 +180,11 @@ int sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf) sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_63_CMD, 0, SDMMC_RSP_TYPE_1, 0); // similar to CMD17 with arg 0x0. - reqbuf.buf = buf; - reqbuf.num_sectors = 1; - reqbuf.blksize = 512; - reqbuf.is_write = 0; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.num_sectors = 1; + reqbuf.blksize = 512; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; u32 blkcnt_out; @@ -211,11 +211,11 @@ static int _sdmmc_storage_readwrite_ex(sdmmc_storage_t *storage, u32 *blkcnt_out sdmmc_init_cmd(&cmdbuf, is_write ? MMC_WRITE_MULTIPLE_BLOCK : MMC_READ_MULTIPLE_BLOCK, sector, SDMMC_RSP_TYPE_1, 0); - reqbuf.buf = buf; - reqbuf.num_sectors = num_sectors; - reqbuf.blksize = 512; - reqbuf.is_write = is_write; - reqbuf.is_multi_block = 1; + reqbuf.buf = buf; + reqbuf.num_sectors = num_sectors; + reqbuf.blksize = 512; + reqbuf.is_write = is_write; + reqbuf.is_multi_block = 1; reqbuf.is_auto_stop_trn = 1; if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, blkcnt_out)) @@ -434,19 +434,19 @@ static void _mmc_storage_parse_cid(sdmmc_storage_t *storage) case 0: /* MMC v1.0 - v1.2 */ case 1: /* MMC v1.4 */ storage->cid.prod_name[6] = unstuff_bits(raw_cid, 48, 8); - storage->cid.manfid = unstuff_bits(raw_cid, 104, 24); - storage->cid.hwrev = unstuff_bits(raw_cid, 44, 4); - storage->cid.fwrev = unstuff_bits(raw_cid, 40, 4); - storage->cid.serial = unstuff_bits(raw_cid, 16, 24); + storage->cid.manfid = unstuff_bits(raw_cid, 104, 24); + storage->cid.hwrev = unstuff_bits(raw_cid, 44, 4); + storage->cid.fwrev = unstuff_bits(raw_cid, 40, 4); + storage->cid.serial = unstuff_bits(raw_cid, 16, 24); break; case 2: /* MMC v2.0 - v2.2 */ case 3: /* MMC v3.1 - v3.3 */ case 4: /* MMC v4 */ - storage->cid.manfid = unstuff_bits(raw_cid, 120, 8); - storage->cid.oemid = unstuff_bits(raw_cid, 104, 8); - storage->cid.prv = unstuff_bits(raw_cid, 48, 8); - storage->cid.serial = unstuff_bits(raw_cid, 16, 32); + storage->cid.manfid = unstuff_bits(raw_cid, 120, 8); + storage->cid.oemid = unstuff_bits(raw_cid, 104, 8); + storage->cid.prv = unstuff_bits(raw_cid, 48, 8); + storage->cid.serial = unstuff_bits(raw_cid, 16, 32); break; default: @@ -483,30 +483,29 @@ static void _mmc_storage_parse_csd(sdmmc_storage_t *storage) static void _mmc_storage_parse_ext_csd(sdmmc_storage_t *storage, u8 *buf) { - storage->ext_csd.rev = buf[EXT_CSD_REV]; - storage->ext_csd.ext_struct = buf[EXT_CSD_STRUCTURE]; - storage->ext_csd.card_type = buf[EXT_CSD_CARD_TYPE]; - storage->ext_csd.dev_version = *(u16 *)&buf[EXT_CSD_DEVICE_VERSION]; - storage->ext_csd.boot_mult = buf[EXT_CSD_BOOT_MULT]; - storage->ext_csd.rpmb_mult = buf[EXT_CSD_RPMB_MULT]; - //storage->ext_csd.bkops = buf[EXT_CSD_BKOPS_SUPPORT]; - //storage->ext_csd.bkops_en = buf[EXT_CSD_BKOPS_EN]; + storage->ext_csd.rev = buf[EXT_CSD_REV]; + storage->ext_csd.ext_struct = buf[EXT_CSD_STRUCTURE]; + storage->ext_csd.card_type = buf[EXT_CSD_CARD_TYPE]; + storage->ext_csd.dev_version = *(u16 *)&buf[EXT_CSD_DEVICE_VERSION]; + storage->ext_csd.boot_mult = buf[EXT_CSD_BOOT_MULT]; + storage->ext_csd.rpmb_mult = buf[EXT_CSD_RPMB_MULT]; + //storage->ext_csd.bkops = buf[EXT_CSD_BKOPS_SUPPORT]; + //storage->ext_csd.bkops_en = buf[EXT_CSD_BKOPS_EN]; //storage->ext_csd.bkops_status = buf[EXT_CSD_BKOPS_STATUS]; - storage->ext_csd.pre_eol_info = buf[EXT_CSD_PRE_EOL_INFO]; + storage->ext_csd.pre_eol_info = buf[EXT_CSD_PRE_EOL_INFO]; storage->ext_csd.dev_life_est_a = buf[EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A]; storage->ext_csd.dev_life_est_b = buf[EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B]; - storage->ext_csd.cache_size = - buf[EXT_CSD_CACHE_SIZE] | - (buf[EXT_CSD_CACHE_SIZE + 1] << 8) | - (buf[EXT_CSD_CACHE_SIZE + 2] << 16) | - (buf[EXT_CSD_CACHE_SIZE + 3] << 24); - storage->ext_csd.max_enh_mult = - (buf[EXT_CSD_MAX_ENH_SIZE_MULT] | - (buf[EXT_CSD_MAX_ENH_SIZE_MULT + 1] << 8) | - (buf[EXT_CSD_MAX_ENH_SIZE_MULT + 2] << 16)) * - buf[EXT_CSD_HC_WP_GRP_SIZE] * buf[EXT_CSD_HC_ERASE_GRP_SIZE]; + storage->ext_csd.cache_size = buf[EXT_CSD_CACHE_SIZE] | + (buf[EXT_CSD_CACHE_SIZE + 1] << 8) | + (buf[EXT_CSD_CACHE_SIZE + 2] << 16) | + (buf[EXT_CSD_CACHE_SIZE + 3] << 24); + + storage->ext_csd.max_enh_mult = (buf[EXT_CSD_MAX_ENH_SIZE_MULT] | + (buf[EXT_CSD_MAX_ENH_SIZE_MULT + 1] << 8) | + (buf[EXT_CSD_MAX_ENH_SIZE_MULT + 2] << 16)) * + buf[EXT_CSD_HC_WP_GRP_SIZE] * buf[EXT_CSD_HC_ERASE_GRP_SIZE]; storage->sec_cnt = *(u32 *)&buf[EXT_CSD_SEC_CNT]; } @@ -917,11 +916,11 @@ int sd_storage_get_scr(sdmmc_storage_t *storage, u8 *buf) sdmmc_init_cmd(&cmdbuf, SD_APP_SEND_SCR, 0, SDMMC_RSP_TYPE_1, 0); sdmmc_req_t reqbuf; - reqbuf.buf = buf; - reqbuf.blksize = 8; - reqbuf.num_sectors = 1; - reqbuf.is_write = 0; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.blksize = 8; + reqbuf.num_sectors = 1; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; if (!_sd_storage_execute_app_cmd(storage, R1_STATE_TRAN, 0, &cmdbuf, &reqbuf, NULL)) @@ -948,11 +947,11 @@ static int _sd_storage_switch_get(sdmmc_storage_t *storage, void *buf) sdmmc_init_cmd(&cmdbuf, SD_SWITCH, 0xFFFFFF, SDMMC_RSP_TYPE_1, 0); sdmmc_req_t reqbuf; - reqbuf.buf = buf; - reqbuf.blksize = 64; - reqbuf.num_sectors = 1; - reqbuf.is_write = 0; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.blksize = 64; + reqbuf.num_sectors = 1; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL)) @@ -974,11 +973,11 @@ static int _sd_storage_switch(sdmmc_storage_t *storage, void *buf, int mode, int sdmmc_init_cmd(&cmdbuf, SD_SWITCH, switchcmd, SDMMC_RSP_TYPE_1, 0); sdmmc_req_t reqbuf; - reqbuf.buf = buf; - reqbuf.blksize = 64; - reqbuf.num_sectors = 1; - reqbuf.is_write = 0; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.blksize = 64; + reqbuf.num_sectors = 1; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL)) @@ -1227,11 +1226,11 @@ static void _sd_storage_parse_ssr(sdmmc_storage_t *storage) storage->ssr.speed_class = speed_class; break; } - storage->ssr.uhs_grade = unstuff_bits(raw_ssr1, 396 - 384, 4); + storage->ssr.uhs_grade = unstuff_bits(raw_ssr1, 396 - 384, 4); storage->ssr.video_class = unstuff_bits(raw_ssr1, 384 - 384, 8); - storage->ssr.app_class = unstuff_bits(raw_ssr2, 336 - 256, 4); + storage->ssr.app_class = unstuff_bits(raw_ssr2, 336 - 256, 4); - storage->ssr.au_size = unstuff_bits(raw_ssr1, 428 - 384, 4); + storage->ssr.au_size = unstuff_bits(raw_ssr1, 428 - 384, 4); storage->ssr.uhs_au_size = unstuff_bits(raw_ssr1, 392 - 384, 4); } @@ -1241,11 +1240,11 @@ int sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf) sdmmc_init_cmd(&cmdbuf, SD_APP_SD_STATUS, 0, SDMMC_RSP_TYPE_1, 0); sdmmc_req_t reqbuf; - reqbuf.buf = buf; - reqbuf.blksize = 64; - reqbuf.num_sectors = 1; - reqbuf.is_write = 0; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.blksize = 64; + reqbuf.num_sectors = 1; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; if (!(storage->csd.cmdclass & CCC_APP_SPEC)) @@ -1278,26 +1277,26 @@ static void _sd_storage_parse_cid(sdmmc_storage_t *storage) { u32 *raw_cid = (u32 *)&(storage->raw_cid); - storage->cid.manfid = unstuff_bits(raw_cid, 120, 8); - storage->cid.oemid = unstuff_bits(raw_cid, 104, 16); + storage->cid.manfid = unstuff_bits(raw_cid, 120, 8); + storage->cid.oemid = unstuff_bits(raw_cid, 104, 16); storage->cid.prod_name[0] = unstuff_bits(raw_cid, 96, 8); storage->cid.prod_name[1] = unstuff_bits(raw_cid, 88, 8); storage->cid.prod_name[2] = unstuff_bits(raw_cid, 80, 8); storage->cid.prod_name[3] = unstuff_bits(raw_cid, 72, 8); storage->cid.prod_name[4] = unstuff_bits(raw_cid, 64, 8); - storage->cid.hwrev = unstuff_bits(raw_cid, 60, 4); - storage->cid.fwrev = unstuff_bits(raw_cid, 56, 4); - storage->cid.serial = unstuff_bits(raw_cid, 24, 32); - storage->cid.year = unstuff_bits(raw_cid, 12, 8) + 2000; - storage->cid.month = unstuff_bits(raw_cid, 8, 4); + storage->cid.hwrev = unstuff_bits(raw_cid, 60, 4); + storage->cid.fwrev = unstuff_bits(raw_cid, 56, 4); + storage->cid.serial = unstuff_bits(raw_cid, 24, 32); + storage->cid.year = unstuff_bits(raw_cid, 12, 8) + 2000; + storage->cid.month = unstuff_bits(raw_cid, 8, 4); } static void _sd_storage_parse_csd(sdmmc_storage_t *storage) { u32 *raw_csd = (u32 *)&(storage->raw_csd); - storage->csd.structure = unstuff_bits(raw_csd, 126, 2); - storage->csd.cmdclass = unstuff_bits(raw_csd, 84, 12); + storage->csd.structure = unstuff_bits(raw_csd, 126, 2); + storage->csd.cmdclass = unstuff_bits(raw_csd, 84, 12); storage->csd.read_blkbits = unstuff_bits(raw_csd, 80, 4); storage->csd.write_protect = unstuff_bits(raw_csd, 12, 2); switch(storage->csd.structure) @@ -1308,8 +1307,8 @@ static void _sd_storage_parse_csd(sdmmc_storage_t *storage) break; case 1: - storage->csd.c_size = (1 + unstuff_bits(raw_csd, 48, 22)); - storage->csd.capacity = storage->csd.c_size << 10; + storage->csd.c_size = (1 + unstuff_bits(raw_csd, 48, 22)); + storage->csd.capacity = storage->csd.c_size << 10; storage->csd.read_blkbits = 9; break; @@ -1480,11 +1479,11 @@ int _gc_storage_custom_cmd(sdmmc_storage_t *storage, void *buf) sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_60_CMD, 0, SDMMC_RSP_TYPE_1, 1); sdmmc_req_t reqbuf; - reqbuf.buf = buf; - reqbuf.blksize = 64; - reqbuf.num_sectors = 1; - reqbuf.is_write = 1; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.blksize = 64; + reqbuf.num_sectors = 1; + reqbuf.is_write = 1; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL)) diff --git a/bdk/storage/sdmmc_driver.c b/bdk/storage/sdmmc_driver.c index b5c2e3d..de9c689 100644 --- a/bdk/storage/sdmmc_driver.c +++ b/bdk/storage/sdmmc_driver.c @@ -173,8 +173,8 @@ static void _sdmmc_pad_config_fallback(sdmmc_t *sdmmc, u32 power) break; case SDMMC_4: // 50 Ohm 2X Driver. PU:16, PD:16, B01: PU:10, PD:10. - APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) = - (APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) & 0xFFFFC003) | (sdmmc->t210b01 ? 0xA28 : 0x1040); + APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) = (APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) & 0xFFFFC003) | + (sdmmc->t210b01 ? 0xA28 : 0x1040); (void)APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL); // Commit write. break; } diff --git a/bdk/thermal/fan.c b/bdk/thermal/fan.c index 6c23b0f..e258615 100644 --- a/bdk/thermal/fan.c +++ b/bdk/thermal/fan.c @@ -78,8 +78,8 @@ void set_fan_duty(u32 duty) regulator_5v_disable(REGULATOR_5V_FAN); // Disable fan. - PINMUX_AUX(PINMUX_AUX_LCD_GPIO2) = - PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_TRISTATE | PINMUX_PULL_DOWN; // Set source to PWM1. + PINMUX_AUX(PINMUX_AUX_LCD_GPIO2) = PINMUX_INPUT_ENABLE | PINMUX_PARKED | + PINMUX_TRISTATE | PINMUX_PULL_DOWN; // Set source to PWM1. } else // Set PWM duty. { diff --git a/bdk/usb/usb_gadget_ums.c b/bdk/usb/usb_gadget_ums.c index a434e02..eead2bf 100644 --- a/bdk/usb/usb_gadget_ums.c +++ b/bdk/usb/usb_gadget_ums.c @@ -283,40 +283,40 @@ static void raise_exception(usbd_gadget_ums_t *ums, enum ums_state new_state) } } -static void ums_handle_ep0_ctrl(usbd_gadget_ums_t *ums) +static void _handle_ep0_ctrl(usbd_gadget_ums_t *ums) { if (usb_ops.usbd_handle_ep0_ctrl_setup()) raise_exception(ums, UMS_STATE_PROTOCOL_RESET); } -static int ums_wedge_bulk_in_endpoint(usbd_gadget_ums_t *ums) +static int _wedge_bulk_in_endpoint(usbd_gadget_ums_t *ums) { /* usbd_set_ep_wedge(bulk_ctxt->bulk_in); */ return UMS_RES_OK; } -static int ums_set_stall(u32 ep) +static int _set_ep_stall(u32 ep) { usb_ops.usbd_set_ep_stall(ep, USB_EP_CFG_STALL); return UMS_RES_OK; } -static int ums_clear_stall(u32 ep) +static int _clear_ep_stall(u32 ep) { usb_ops.usbd_set_ep_stall(ep, USB_EP_CFG_CLEAR); return UMS_RES_OK; } -static void ums_flush_endpoint(u32 ep) +static void _flush_endpoint(u32 ep) { if (usb_ops.usbd_flush_endpoint) usb_ops.usbd_flush_endpoint(ep); } -static void _ums_transfer_start(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, u32 ep, u32 sync_timeout) +static void _transfer_start(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, u32 ep, u32 sync_timeout) { if (ep == bulk_ctxt->bulk_in) { @@ -327,7 +327,7 @@ static void _ums_transfer_start(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, if (bulk_ctxt->bulk_in_status == USB_ERROR_XFER_ERROR) { ums->set_text(ums->label, "#FFDD00 Error:# EP IN transfer!"); - ums_flush_endpoint(bulk_ctxt->bulk_in); + _flush_endpoint(bulk_ctxt->bulk_in); } else if (bulk_ctxt->bulk_in_status == USB2_ERROR_XFER_NOT_ALIGNED) ums->set_text(ums->label, "#FFDD00 Error:# EP IN Buffer not aligned!"); @@ -344,7 +344,7 @@ static void _ums_transfer_start(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, if (bulk_ctxt->bulk_out_status == USB_ERROR_XFER_ERROR) { ums->set_text(ums->label, "#FFDD00 Error:# EP OUT transfer!"); - ums_flush_endpoint(bulk_ctxt->bulk_out); + _flush_endpoint(bulk_ctxt->bulk_out); } else if (bulk_ctxt->bulk_out_status == USB2_ERROR_XFER_NOT_ALIGNED) ums->set_text(ums->label, "#FFDD00 Error:# EP OUT Buffer not aligned!"); @@ -354,7 +354,7 @@ static void _ums_transfer_start(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, } } -static void _ums_transfer_out_big_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static void _transfer_out_big_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { bulk_ctxt->bulk_out_status = usb_ops.usb_device_ep1_out_read_big( bulk_ctxt->bulk_out_buf, bulk_ctxt->bulk_out_length, @@ -363,13 +363,13 @@ static void _ums_transfer_out_big_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk if (bulk_ctxt->bulk_out_status == USB_ERROR_XFER_ERROR) { ums->set_text(ums->label, "#FFDD00 Error:# EP OUT transfer!"); - ums_flush_endpoint(bulk_ctxt->bulk_out); + _flush_endpoint(bulk_ctxt->bulk_out); } bulk_ctxt->bulk_out_buf_state = BUF_STATE_FULL; } -static void _ums_transfer_finish(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, u32 ep, u32 sync_timeout) +static void _transfer_finish(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, u32 ep, u32 sync_timeout) { if (ep == bulk_ctxt->bulk_in) { @@ -379,7 +379,7 @@ static void _ums_transfer_finish(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, if (bulk_ctxt->bulk_in_status == USB_ERROR_XFER_ERROR) { ums->set_text(ums->label, "#FFDD00 Error:# EP IN transfer!"); - ums_flush_endpoint(bulk_ctxt->bulk_in); + _flush_endpoint(bulk_ctxt->bulk_in); } bulk_ctxt->bulk_in_buf_state = BUF_STATE_EMPTY; @@ -392,14 +392,14 @@ static void _ums_transfer_finish(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, if (bulk_ctxt->bulk_out_status == USB_ERROR_XFER_ERROR) { ums->set_text(ums->label, "#FFDD00 Error:# EP OUT transfer!"); - ums_flush_endpoint(bulk_ctxt->bulk_out); + _flush_endpoint(bulk_ctxt->bulk_out); } bulk_ctxt->bulk_out_buf_state = BUF_STATE_FULL; } } -static void _ums_reset_buffer(bulk_ctxt_t *bulk_ctxt, u32 ep) +static void _reset_buffer(bulk_ctxt_t *bulk_ctxt, u32 ep) { if (ep == bulk_ctxt->bulk_in) bulk_ctxt->bulk_in_buf = (u8 *)USB_EP_BULK_IN_BUF_ADDR; @@ -474,20 +474,21 @@ static int _scsi_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // Limit IO transfers based on request for faster concurrent reads. u32 max_io_transfer = (amount_left >= UMS_SCSI_TRANSFER_512K) ? - UMS_DISK_MAX_IO_TRANSFER_64K : UMS_DISK_MAX_IO_TRANSFER_32K; + UMS_DISK_MAX_IO_TRANSFER_64K : UMS_DISK_MAX_IO_TRANSFER_32K; while (true) { // Max io size and end sector limits. u32 amount = MIN(amount_left, max_io_transfer); - amount = MIN(amount, ums->lun.num_sectors - lba_offset); + amount = MIN(amount, ums->lun.num_sectors - lba_offset); // Check if it is a read past the end sector. if (!amount) { - ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; + bulk_ctxt->bulk_in_length = 0; bulk_ctxt->bulk_in_buf_state = BUF_STATE_FULL; break; @@ -499,7 +500,7 @@ static int _scsi_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // Wait for the async USB transfer to finish. if (!first_read) - _ums_transfer_finish(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED); + _transfer_finish(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED); lba_offset += amount; amount_left -= amount; @@ -513,9 +514,9 @@ static int _scsi_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) if (!amount) { ums->set_text(ums->label, "#FFDD00 Error:# SDMMC Read!"); - ums->lun.sense_data = SS_UNRECOVERED_READ_ERROR; + ums->lun.sense_data = SS_UNRECOVERED_READ_ERROR; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; break; } @@ -524,7 +525,7 @@ static int _scsi_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) break; // Start the USB transfer. - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_START); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_START); first_read = false; // Increment our buffer to read new data. @@ -581,8 +582,8 @@ static int _scsi_write(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) } // Carry out the file writes. - usb_lba_offset = lba_offset; - amount_left_to_req = ums->data_size_from_cmnd; + usb_lba_offset = lba_offset; + amount_left_to_req = ums->data_size_from_cmnd; amount_left_to_write = ums->data_size_from_cmnd; while (amount_left_to_write > 0) @@ -597,20 +598,20 @@ static int _scsi_write(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) if (usb_lba_offset >= ums->lun.num_sectors) { ums->set_text(ums->label, "#FFDD00 Error:# Write - Past last sector!"); - ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ums->lun.sense_data_info = usb_lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; break; } // Get the next buffer. - usb_lba_offset += amount >> UMS_DISK_LBA_SHIFT; + usb_lba_offset += amount >> UMS_DISK_LBA_SHIFT; ums->usb_amount_left -= amount; - amount_left_to_req -= amount; + amount_left_to_req -= amount; bulk_ctxt->bulk_out_length = amount; - _ums_transfer_out_big_read(ums, bulk_ctxt); + _transfer_out_big_read(ums, bulk_ctxt); } if (bulk_ctxt->bulk_out_buf_state == BUF_STATE_FULL) @@ -620,9 +621,10 @@ static int _scsi_write(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // Did something go wrong with the transfer?. if (bulk_ctxt->bulk_out_status != 0) { - ums->lun.sense_data = SS_COMMUNICATION_FAILURE; + ums->lun.sense_data = SS_COMMUNICATION_FAILURE; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; + s_printf(txt_buf, "#FFDD00 Error:# Write - Comm failure %d!", bulk_ctxt->bulk_out_status); ums->set_text(ums->label, txt_buf); break; @@ -662,9 +664,9 @@ DPRINTF("file write %X @ %X\n", amount, lba_offset); if (!amount) { ums->set_text(ums->label, "#FFDD00 Error:# SDMMC Write!"); - ums->lun.sense_data = SS_WRITE_ERROR; + ums->lun.sense_data = SS_WRITE_ERROR; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; break; } @@ -714,9 +716,9 @@ static int _scsi_verify(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) amount = MIN(verification_length, USB_EP_BUFFER_MAX_SIZE >> UMS_DISK_LBA_SHIFT); amount = MIN(amount, ums->lun.num_sectors - lba_offset); if (amount == 0) { - ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; break; } @@ -728,9 +730,9 @@ DPRINTF("File read %X @ %X\n", amount, lba_offset); if (!amount) { ums->set_text(ums->label, "#FFDD00 Error:# File verify!"); - ums->lun.sense_data = SS_UNRECOVERED_READ_ERROR; + ums->lun.sense_data = SS_UNRECOVERED_READ_ERROR; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; break; } lba_offset += amount; @@ -1116,8 +1118,9 @@ static int _scsi_read_format_capacities(usbd_gadget_ums_t *ums, bulk_ctxt_t *bul // Check whether the command is properly formed and whether its data size // and direction agree with the values we already have. -static int _ums_check_scsi_cmd(usbd_gadget_ums_t *ums, u32 cmnd_size, - enum data_direction data_dir, u32 mask, int needs_medium) +static int _check_scsi_cmd(usbd_gadget_ums_t *ums, u32 cmnd_size, + enum data_direction data_dir, u32 mask, + int needs_medium) { //const char dirletter[4] = {'u', 'o', 'i', 'n'}; DPRINTF("SCSI command: %X; Dc=%d, D%c=%X; Hc=%d, H%c=%X\n", @@ -1165,9 +1168,9 @@ DPRINTF("SCSI command: %X; Dc=%d, D%c=%X; Hc=%d, H%c=%X\n", if (ums->cmnd[0] != SC_REQUEST_SENSE) { - ums->lun.sense_data = SS_NO_SENSE; + ums->lun.sense_data = SS_NO_SENSE; ums->lun.sense_data_info = 0; - ums->lun.info_valid = 0; + ums->lun.info_valid = 0; } // If a unit attention condition exists, only INQUIRY and REQUEST SENSE @@ -1204,7 +1207,7 @@ DPRINTF("SCSI command: %X; Dc=%d, D%c=%X; Hc=%d, H%c=%X\n", return UMS_RES_OK; } -static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { u32 len; int reply = UMS_RES_INVALID_ARG; @@ -1219,21 +1222,21 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) u32 mask = (1<<4); if (ums->cmnd[1] == 1 && ums->cmnd[2] == 0x80) // Inquiry S/N. mask = (1<<1) | (1<<2) | (1<<4); - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, mask, 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, mask, 0); if (reply == 0) reply = _scsi_inquiry(ums, bulk_ctxt); break; case SC_LOG_SENSE: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]); - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (3<<7), 0); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (3<<7), 0); if (reply == 0) reply = _scsi_log_sense(ums, bulk_ctxt); break; case SC_MODE_SELECT_6: ums->data_size_from_cmnd = ums->cmnd[4]; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_FROM_HOST, (1<<1) | (1<<4), 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_FROM_HOST, (1<<1) | (1<<4), 0); if (reply == 0) { // We don't support MODE SELECT. @@ -1244,7 +1247,7 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case SC_MODE_SELECT_10: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]); - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_FROM_HOST, (1<<1) | (3<<7), 0); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_FROM_HOST, (1<<1) | (3<<7), 0); if (reply == 0) { // We don't support MODE SELECT. @@ -1255,21 +1258,21 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case SC_MODE_SENSE_6: ums->data_size_from_cmnd = ums->cmnd[4]; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (1<<4), 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (1<<4), 0); if (reply == 0) reply = _scsi_mode_sense(ums, bulk_ctxt); break; case SC_MODE_SENSE_10: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]); - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (3<<7), 0); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (3<<7), 0); if (reply == 0) reply = _scsi_mode_sense(ums, bulk_ctxt); break; case SC_PREVENT_ALLOW_MEDIUM_REMOVAL: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_NONE, (1<<4), 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_NONE, (1<<4), 0); if (reply == 0) reply = _scsi_prevent_allow_removal(ums); break; @@ -1277,68 +1280,68 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case SC_READ_6: len = ums->cmnd[4]; ums->data_size_from_cmnd = (len == 0 ? 256 : len) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (7<<1) | (1<<4), 1); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (7<<1) | (1<<4), 1); if (reply == 0) reply = _scsi_read(ums, bulk_ctxt); break; case SC_READ_10: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (0xf<<2) | (3<<7), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (0xf<<2) | (3<<7), 1); if (reply == 0) reply = _scsi_read(ums, bulk_ctxt); break; case SC_READ_12: ums->data_size_from_cmnd = get_array_be_to_le32(&ums->cmnd[6]) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 12, DATA_DIR_TO_HOST, (1<<1) | (0xf<<2) | (0xf<<6), 1); + reply = _check_scsi_cmd(ums, 12, DATA_DIR_TO_HOST, (1<<1) | (0xf<<2) | (0xf<<6), 1); if (reply == 0) reply = _scsi_read(ums, bulk_ctxt); break; case SC_READ_CAPACITY: ums->data_size_from_cmnd = 8; - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (0xf<<2) | (1<<8), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (0xf<<2) | (1<<8), 1); if (reply == 0) reply = _scsi_read_capacity(ums, bulk_ctxt); break; case SC_READ_FORMAT_CAPACITIES: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]); - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (3<<7), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (3<<7), 1); if (reply == 0) reply = _scsi_read_format_capacities(ums, bulk_ctxt); break; case SC_REQUEST_SENSE: ums->data_size_from_cmnd = ums->cmnd[4]; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (1<<4), 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (1<<4), 0); if (reply == 0) reply = _scsi_request_sense(ums, bulk_ctxt); break; case SC_START_STOP_UNIT: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_NONE, (1<<1) | (1<<4), 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_NONE, (1<<1) | (1<<4), 0); if (reply == 0) reply = _scsi_start_stop(ums); break; case SC_SYNCHRONIZE_CACHE: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_NONE, (0xf<<2) | (3<<7), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_NONE, (0xf<<2) | (3<<7), 1); if (reply == 0) reply = 0; // Don't bother break; case SC_TEST_UNIT_READY: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_NONE, 0, 1); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_NONE, 0, 1); break; // This command is used by Windows. We support a minimal version and BytChk must be 0. case SC_VERIFY: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_NONE, (1<<1) | (0xf<<2) | (3<<7), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_NONE, (1<<1) | (0xf<<2) | (3<<7), 1); if (reply == 0) reply = _scsi_verify(ums, bulk_ctxt); break; @@ -1346,21 +1349,21 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case SC_WRITE_6: len = ums->cmnd[4]; ums->data_size_from_cmnd = (len == 0 ? 256 : len) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_FROM_HOST, (7<<1) | (1<<4), 1); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_FROM_HOST, (7<<1) | (1<<4), 1); if (reply == 0) reply = _scsi_write(ums, bulk_ctxt); break; case SC_WRITE_10: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_FROM_HOST, (1<<1) | (0xf<<2) | (3<<7), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_FROM_HOST, (1<<1) | (0xf<<2) | (3<<7), 1); if (reply == 0) reply = _scsi_write(ums, bulk_ctxt); break; case SC_WRITE_12: ums->data_size_from_cmnd = get_array_be_to_le32(&ums->cmnd[6]) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 12, DATA_DIR_FROM_HOST, (1<<1) | (0xf<<2) | (0xf<<6), 1); + reply = _check_scsi_cmd(ums, 12, DATA_DIR_FROM_HOST, (1<<1) | (0xf<<2) | (0xf<<6), 1); if (reply == 0) reply = _scsi_write(ums, bulk_ctxt); break; @@ -1374,7 +1377,7 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case SC_SEND_DIAGNOSTIC: default: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, ums->cmnd_size, DATA_DIR_UNKNOWN, 0xFF, 0); + reply = _check_scsi_cmd(ums, ums->cmnd_size, DATA_DIR_UNKNOWN, 0xFF, 0); if (reply == 0) { ums->lun.sense_data = SS_INVALID_COMMAND; @@ -1386,7 +1389,7 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) if (reply == UMS_RES_INVALID_ARG) reply = 0; // Error reply length. - // Set up reply buffer for finish_reply(). Otherwise it's already set. + // Set up reply buffer for _finish_reply(). Otherwise it's already set. if (reply >= 0 && ums->data_dir == DATA_DIR_TO_HOST) { reply = MIN((u32)reply, ums->data_size_from_cmnd); @@ -1398,7 +1401,7 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) return UMS_RES_OK; } -static int pad_with_zeros(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _pad_with_zeros(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { bulk_ctxt->bulk_in_buf_state = BUF_STATE_EMPTY; // For the first iteration. u32 current_len_to_keep = bulk_ctxt->bulk_in_length; @@ -1409,7 +1412,7 @@ static int pad_with_zeros(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) u32 nsend = MIN(ums->usb_amount_left, USB_EP_BUFFER_MAX_SIZE); memset(bulk_ctxt->bulk_in_buf + current_len_to_keep, 0, nsend - current_len_to_keep); bulk_ctxt->bulk_in_length = nsend; - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); ums->usb_amount_left -= nsend; current_len_to_keep = 0; } @@ -1417,7 +1420,7 @@ static int pad_with_zeros(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) return UMS_RES_OK; } -static int throw_away_data(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _throw_away_data(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { if (bulk_ctxt->bulk_out_buf_state != BUF_STATE_EMPTY || ums->usb_amount_left > 0) { @@ -1427,7 +1430,7 @@ static int throw_away_data(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) u32 amount = MIN(ums->usb_amount_left, USB_EP_BUFFER_MAX_SIZE); bulk_ctxt->bulk_out_length = amount; - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_DATA); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_DATA); ums->usb_amount_left -= amount; return UMS_RES_OK; @@ -1448,7 +1451,7 @@ static int throw_away_data(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) return UMS_RES_OK; } -static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { int rc = UMS_RES_OK; @@ -1461,8 +1464,8 @@ static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case DATA_DIR_UNKNOWN: if (ums->can_stall) { - ums_set_stall(bulk_ctxt->bulk_out); - rc = ums_set_stall(bulk_ctxt->bulk_in); + _set_ep_stall(bulk_ctxt->bulk_out); + rc = _set_ep_stall(bulk_ctxt->bulk_in); ums->set_text(ums->label, "#FFDD00 Error:# Direction unknown. Stalled both EP!"); } // Else do nothing. break; @@ -1474,7 +1477,7 @@ static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // If there's no residue, simply send the last buffer. if (!ums->residue) { - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); /* For Bulk-only, if we're allowed to stall then send the * short packet and halt the bulk-in endpoint. If we can't @@ -1482,16 +1485,16 @@ static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) } else if (ums->can_stall) { - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); - rc = ums_set_stall(bulk_ctxt->bulk_in); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); + rc = _set_ep_stall(bulk_ctxt->bulk_in); ums->set_text(ums->label, "#FFDD00 Error:# Residue. Stalled EP IN!"); } else - rc = pad_with_zeros(ums, bulk_ctxt); + rc = _pad_with_zeros(ums, bulk_ctxt); } // In case we used SDMMC transfer, reset the buffer address. - _ums_reset_buffer(bulk_ctxt, bulk_ctxt->bulk_in); + _reset_buffer(bulk_ctxt, bulk_ctxt->bulk_in); break; // We have processed all we want from the data the host has sent. @@ -1505,7 +1508,7 @@ static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) rc = UMS_RES_PROT_FATAL; } else // We can't stall. Read in the excess data and throw it away. - rc = throw_away_data(ums, bulk_ctxt); + rc = _throw_away_data(ums, bulk_ctxt); } break; @@ -1540,7 +1543,7 @@ static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) * Line always at SE0. */ -static int received_cbw(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _received_cbw(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { // Was this a real packet? Should it be ignored? if (bulk_ctxt->bulk_out_status || bulk_ctxt->bulk_out_ignore || ums->lun.unmounted) @@ -1610,7 +1613,7 @@ static int received_cbw(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) * we can simply accept and discard any data received * until the next reset. */ - ums_wedge_bulk_in_endpoint(ums); + _wedge_bulk_in_endpoint(ums); bulk_ctxt->bulk_out_ignore = 1; return UMS_RES_INVALID_ARG; } @@ -1626,8 +1629,8 @@ static int received_cbw(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) * bulk pipes if we are allowed to. */ if (ums->can_stall) { - ums_set_stall(bulk_ctxt->bulk_out); - ums_set_stall(bulk_ctxt->bulk_in); + _set_ep_stall(bulk_ctxt->bulk_out); + _set_ep_stall(bulk_ctxt->bulk_in); ums->set_text(ums->label, "#FFDD00 Error:# CBW unknown - Stalled both EP!"); } @@ -1657,7 +1660,7 @@ static int received_cbw(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) return UMS_RES_OK; } -static int get_next_command(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _get_next_command(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { int rc = UMS_RES_OK; @@ -1671,9 +1674,9 @@ static int get_next_command(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // Queue a request to read a Bulk-only CBW. if (!ums->cbw_req_queued) - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_CMD); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_CMD); else - _ums_transfer_finish(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_CMD); + _transfer_finish(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_CMD); /* * On XUSB do not allow multiple requests for CBW to be done. @@ -1694,13 +1697,13 @@ static int get_next_command(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // //wait irq. // } - rc = received_cbw(ums, bulk_ctxt); + rc = _received_cbw(ums, bulk_ctxt); bulk_ctxt->bulk_out_buf_state = BUF_STATE_EMPTY; return rc; } -static void send_status(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static void _send_status(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { u8 status = USB_STATUS_PASS; u32 sd = ums->lun.sense_data; @@ -1723,26 +1726,26 @@ static void send_status(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) bulk_send_pkt_t *csw = (bulk_send_pkt_t *)bulk_ctxt->bulk_in_buf; csw->Signature = USB_BULK_CS_SIG; - csw->Tag = ums->tag; - csw->Residue = ums->residue; - csw->Status = status; + csw->Tag = ums->tag; + csw->Residue = ums->residue; + csw->Status = status; bulk_ctxt->bulk_in_length = USB_BULK_CS_WRAP_LEN; - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_CMD); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_CMD); } -static void handle_exception(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static void _handle_exception(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { enum ums_state old_state; // Clear out the controller's fifos. - ums_flush_endpoint(bulk_ctxt->bulk_in); - ums_flush_endpoint(bulk_ctxt->bulk_out); + _flush_endpoint(bulk_ctxt->bulk_in); + _flush_endpoint(bulk_ctxt->bulk_out); /* Reset the I/O buffer states and pointers, the SCSI * state, and the exception. Then invoke the handler. */ - bulk_ctxt->bulk_in_buf_state = BUF_STATE_EMPTY; + bulk_ctxt->bulk_in_buf_state = BUF_STATE_EMPTY; bulk_ctxt->bulk_out_buf_state = BUF_STATE_EMPTY; old_state = ums->state; @@ -1750,10 +1753,10 @@ static void handle_exception(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) if (old_state != UMS_STATE_ABORT_BULK_OUT) { ums->lun.prevent_medium_removal = 0; - ums->lun.sense_data = SS_NO_SENSE; - ums->lun.unit_attention_data = SS_NO_SENSE; - ums->lun.sense_data_info = 0; - ums->lun.info_valid = 0; + ums->lun.sense_data = SS_NO_SENSE; + ums->lun.unit_attention_data = SS_NO_SENSE; + ums->lun.sense_data_info = 0; + ums->lun.info_valid = 0; } ums->state = UMS_STATE_NORMAL; @@ -1764,7 +1767,7 @@ static void handle_exception(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case UMS_STATE_NORMAL: break; case UMS_STATE_ABORT_BULK_OUT: - send_status(ums, bulk_ctxt); + _send_status(ums, bulk_ctxt); break; case UMS_STATE_PROTOCOL_RESET: @@ -1774,7 +1777,7 @@ static void handle_exception(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) if (bulk_ctxt->bulk_out_ignore) { bulk_ctxt->bulk_out_ignore = 0; - ums_clear_stall(bulk_ctxt->bulk_in); + _clear_ep_stall(bulk_ctxt->bulk_in); } ums->lun.unit_attention_data = SS_RESET_OCCURRED; break; @@ -1832,17 +1835,17 @@ int usb_device_gadget_ums(usb_ctxt_t *usbs) ums.state = UMS_STATE_NORMAL; ums.can_stall = 0; - ums.bulk_ctxt.bulk_in = USB_EP_BULK_IN; + ums.bulk_ctxt.bulk_in = USB_EP_BULK_IN; ums.bulk_ctxt.bulk_in_buf = (u8 *)USB_EP_BULK_IN_BUF_ADDR; - ums.bulk_ctxt.bulk_out = USB_EP_BULK_OUT; + ums.bulk_ctxt.bulk_out = USB_EP_BULK_OUT; ums.bulk_ctxt.bulk_out_buf = (u8 *)USB_EP_BULK_OUT_BUF_ADDR; // Set LUN parameters. - ums.lun.ro = usbs->ro; - ums.lun.type = usbs->type; + ums.lun.ro = usbs->ro; + ums.lun.type = usbs->type; ums.lun.partition = usbs->partition; - ums.lun.offset = usbs->offset; + ums.lun.offset = usbs->offset; ums.lun.removable = 1; // Always removable to force OSes to use prevent media removal. ums.lun.unit_attention_data = SS_RESET_OCCURRED; @@ -1859,15 +1862,17 @@ int usb_device_gadget_ums(usb_ctxt_t *usbs) sd_end(); sd_mount(); sd_unmount(); - ums.lun.sdmmc = &sd_sdmmc; + + ums.lun.sdmmc = &sd_sdmmc; ums.lun.storage = &sd_storage; } else { - ums.lun.sdmmc = &emmc_sdmmc; - ums.lun.storage = &emmc_storage; emmc_initialize(false); sdmmc_storage_set_mmc_partition(ums.lun.storage, ums.lun.partition - 1); + + ums.lun.sdmmc = &emmc_sdmmc; + ums.lun.storage = &emmc_storage; } ums.set_text(ums.label, "#C7EA46 Status:# Waiting for connection"); @@ -1905,26 +1910,26 @@ int usb_device_gadget_ums(usb_ctxt_t *usbs) if (ums.state != UMS_STATE_NORMAL) { - handle_exception(&ums, &ums.bulk_ctxt); + _handle_exception(&ums, &ums.bulk_ctxt); continue; } - ums_handle_ep0_ctrl(&ums); + _handle_ep0_ctrl(&ums); - if (get_next_command(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) + if (_get_next_command(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) continue; - ums_handle_ep0_ctrl(&ums); + _handle_ep0_ctrl(&ums); - if (_ums_parse_scsi_cmd(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) + if (_parse_scsi_cmd(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) continue; - ums_handle_ep0_ctrl(&ums); + _handle_ep0_ctrl(&ums); - if (finish_reply(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) + if (_finish_reply(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) continue; - send_status(&ums, &ums.bulk_ctxt); + _send_status(&ums, &ums.bulk_ctxt); } while (ums.state != UMS_STATE_TERMINATED); if (ums.lun.prevent_medium_removal) diff --git a/bdk/usb/usbd.c b/bdk/usb/usbd.c index c8e5e23..6eabae3 100644 --- a/bdk/usb/usbd.c +++ b/bdk/usb/usbd.c @@ -143,11 +143,11 @@ static int _usbd_reset_usb_otg_phy_device_mode() // Clear all device addresses, enabled setup requests and transmit events. usbd_otg->regs->periodiclistbase = 0; - usbd_otg->regs->endptsetupstat = usbd_otg->regs->endptsetupstat; - usbd_otg->regs->endptcomplete = usbd_otg->regs->endptcomplete; + usbd_otg->regs->endptsetupstat = usbd_otg->regs->endptsetupstat; + usbd_otg->regs->endptcomplete = usbd_otg->regs->endptcomplete; // Stop device controller. - usbd_otg->regs->usbcmd &= ~USB2D_USBCMD_RUN; + usbd_otg->regs->usbcmd &= ~USB2D_USBCMD_RUN; // Set controller mode to idle. usbd_otg->regs->usbmode &= ~USB2D_USBMODE_CM_MASK; @@ -192,16 +192,15 @@ static int _usbd_reset_usb_otg_phy_device_mode() usbd_otg->regs->usbintr = 0; // Set the ID pullup and disable all OTGSC interrupts. - usbd_otg->regs->otgsc = USB2D_OTGSC_USB_ID_PULLUP; + usbd_otg->regs->otgsc = USB2D_OTGSC_USB_ID_PULLUP; // Clear all relevant interrupt statuses. - usbd_otg->regs->usbsts = - USB2D_USBSTS_UI | USB2D_USBSTS_UEI | USB2D_USBSTS_PCI | - USB2D_USBSTS_FRI | USB2D_USBSTS_SEI | USB2D_USBSTS_AAI | - USB2D_USBSTS_URI | USB2D_USBSTS_SRI | USB2D_USBSTS_SLI; + usbd_otg->regs->usbsts = USB2D_USBSTS_UI | USB2D_USBSTS_UEI | USB2D_USBSTS_PCI | + USB2D_USBSTS_FRI | USB2D_USBSTS_SEI | USB2D_USBSTS_AAI | + USB2D_USBSTS_URI | USB2D_USBSTS_SRI | USB2D_USBSTS_SLI; // Disable and clear all OTGSC interrupts. - usbd_otg->regs->otgsc = USB2D_OTGSC_USB_IRQ_STS_MASK; + usbd_otg->regs->otgsc = USB2D_OTGSC_USB_IRQ_STS_MASK; // Clear EP0, EP1, EP2 setup requests. usbd_otg->regs->endptsetupstat = 7; //TODO: Shouldn't this be endptsetupstat = endptsetupstat? @@ -225,8 +224,7 @@ static void _usb_charger_detect() gpio_config(GPIO_PORT_V, GPIO_PIN_3, GPIO_MODE_GPIO); // Configure charger pin. - PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN1) &= - ~(PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_TRISTATE | PINMUX_PULL_MASK); + PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN1) &= ~(PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_TRISTATE | PINMUX_PULL_MASK); gpio_config(GPIO_PORT_CC, GPIO_PIN_5, GPIO_MODE_GPIO); gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_5, GPIO_OUTPUT_ENABLE); @@ -289,12 +287,12 @@ static void _usb_init_phy() // Configure misc UTMIP. USB(USB1_UTMIP_DEBOUNCE_CFG0) = (USB(USB1_UTMIP_DEBOUNCE_CFG0) & 0xFFFF0000) | 0xBB80; - USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFFFFC0FF) | 0x100; // when osc is 38.4KHz + USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFFFFC0FF) | 0x100; // when osc is 38.4KHz //USB(USB1_UTMIP_SPARE_CFG0) &= 0xFFFFFEE7; unpatched0 - USB(USB1_UTMIP_BIAS_CFG2) |= 2; //patched0 - UTMIP_HSSQUELCH_LEVEL_NEW: 2. + USB(USB1_UTMIP_BIAS_CFG2) |= 2; //patched0 - UTMIP_HSSQUELCH_LEVEL_NEW: 2. USB(USB1_UTMIP_SPARE_CFG0) &= 0xFFFFFE67; //patched0 - FUSE_HS_IREF_CAP_CFG - USB(USB1_UTMIP_TX_CFG0) |= 0x80000; + USB(USB1_UTMIP_TX_CFG0) |= 0x80000; //USB(USB1_UTMIP_HSRX_CFG0) = (USB(USB1_UTMIP_HSRX_CFG0) & 0xFFF003FF) | 0x88000 | 0x4000; unpatched1 USB(USB1_UTMIP_HSRX_CFG0) = (USB(USB1_UTMIP_HSRX_CFG0) & 0xF0F003FF) | 0x88000 | 0x4000; //patched1 - reset UTMIP_PCOUNT_UPDN_DIV: From 1 to 0. @@ -307,7 +305,7 @@ static void _usb_init_phy() CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) |= 0x40000000; // Enable USB2 tracking clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK); CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) & 0xFFFFFF00) | 6; // Set trank divisor to 4. USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFFC03F07) | 0x78000 | 0x50; // Set delays. @@ -338,7 +336,7 @@ static void _usb_init_phy() usleep(1); // Clear power downs on UTMIP ID and VBUS wake up, PD, PD2, PDZI, PDCHRP, PDDR. - PMC(APBDEV_PMC_USB_AO) &= 0xFFFFFFF3; // UTMIP ID and VBUS wake up. + PMC(APBDEV_PMC_USB_AO) &= 0xFFFFFFF3; // UTMIP ID and VBUS wake up. usleep(1); USB(USB1_UTMIP_XCVR_CFG0) &= 0xFFFFBFFF; // UTMIP_FORCE_PD_POWERDOWN. usleep(1); @@ -362,14 +360,14 @@ int usb_device_init() // AHB USB performance cfg. AHB_GIZMO(AHB_GIZMO_AHB_MEM) |= AHB_MEM_DONT_SPLIT_AHB_WR | AHB_MEM_ENB_FAST_REARBITRATE; - AHB_GIZMO(AHB_GIZMO_USB) |= AHB_GIZMO_IMMEDIATE; + AHB_GIZMO(AHB_GIZMO_USB) |= AHB_GIZMO_IMMEDIATE; AHB_GIZMO(AHB_ARBITRATION_PRIORITY_CTRL) = PRIORITY_CTRL_WEIGHT(7) | PRIORITY_SELECT_USB; - AHB_GIZMO(AHB_AHB_MEM_PREFETCH_CFG1) = - MEM_PREFETCH_ENABLE | MEM_PREFETCH_USB_MST_ID | MEM_PREFETCH_ADDR_BNDRY(12) | 0x1000; // Addr boundary 64KB, Inactivity 4096 cycles. + AHB_GIZMO(AHB_AHB_MEM_PREFETCH_CFG1) = MEM_PREFETCH_ENABLE | MEM_PREFETCH_USB_MST_ID | + MEM_PREFETCH_ADDR_BNDRY(12) | 0x1000; // Addr boundary 64KB, Inactivity 4096 cycles. // Set software and hardware context storage and clear it. usbdaemon = (usbd_t *)USBD_ADDR; // Depends on USB_TD_BUFFER_PAGE_SIZE aligned address. - usbd_otg = &usbd_usb_otg_controller_ctxt; + usbd_otg = &usbd_usb_otg_controller_ctxt; memset(usbd_otg, 0, sizeof(usbd_controller_t)); memset(usbdaemon, 0, sizeof(usbd_t)); @@ -529,13 +527,11 @@ static void _usbd_initialize_ep_ctrl(u32 endpoint) { u32 endpoint_type = usbd_otg->regs->endptctrl[actual_ep] & ~USB2D_ENDPTCTRL_RX_EP_TYPE_MASK; if (actual_ep) - { endpoint_type |= usbd_otg->gadget ? USB2D_ENDPTCTRL_RX_EP_TYPE_INTR : USB2D_ENDPTCTRL_RX_EP_TYPE_BULK; - } else endpoint_type |= USB2D_ENDPTCTRL_RX_EP_TYPE_CTRL; - usbd_otg->regs->endptctrl[actual_ep] = endpoint_type; + usbd_otg->regs->endptctrl[actual_ep] = endpoint_type; usbd_otg->regs->endptctrl[actual_ep] &= ~USB2D_ENDPTCTRL_RX_EP_STALL; if (actual_ep == USB_HW_EP1) @@ -547,7 +543,7 @@ static void _usbd_initialize_ep_ctrl(u32 endpoint) static int _usbd_initialize_ep0() { - memset((void *)usbdaemon->qhs, 0, sizeof(dQH_t) * 4); // Clear all used EP queue heads. + memset((void *)usbdaemon->qhs, 0, sizeof(dQH_t) * 4); // Clear all used EP queue heads. memset((void *)usbdaemon->dtds, 0, sizeof(dTD_t) * 4); // Clear all used EP0 token heads. usbd_otg->regs->asynclistaddr = (u32)usbdaemon->qhs; @@ -588,8 +584,8 @@ int usbd_flush_endpoint(u32 endpoint) { usb_hw_ep_t actual_ep = (endpoint & 2) >> 1; - usb_dir_t direction = endpoint & 1; - u32 reg_mask = endpoint; + usb_dir_t direction = endpoint & 1; + u32 reg_mask = endpoint; // Flash all endpoints or 1. if (endpoint != USB_EP_ALL) @@ -640,10 +636,10 @@ static void _usb_reset_disable_ep1() _usbd_stall_reset_ep1(USB_DIR_IN, USB_EP_CFG_RESET); // EP1 Bulk IN. _usbd_disable_ep1(); - usbd_otg->config_num = 0; - usbd_otg->interface_num = 0; + usbd_otg->config_num = 0; + usbd_otg->interface_num = 0; usbd_otg->configuration_set = false; - usbd_otg->max_lun_set = false; + usbd_otg->max_lun_set = false; } void usbd_end(bool reset_ep, bool only_controller) @@ -668,9 +664,11 @@ static void _usbd_mark_ep_complete(u32 endpoint) usb_dir_t direction = endpoint & 1; usbd_flush_endpoint(endpoint); + memset((void *)&usbdaemon->dtds[endpoint * 4], 0, sizeof(dTD_t) * 4); - memset((void *)&usbdaemon->qhs[endpoint], 0, sizeof(dQH_t)); - usbdaemon->ep_configured[endpoint] = 0; + memset((void *)&usbdaemon->qhs[endpoint], 0, sizeof(dQH_t)); + + usbdaemon->ep_configured[endpoint] = 0; usbdaemon->ep_bytes_requested[endpoint] = 0; if (direction == USB_DIR_IN) @@ -850,9 +848,8 @@ static int _usbd_ep_ack(usb_ep_t ep) static void _usbd_set_ep0_stall() { // EP Control endpoints must be always stalled together. - usbd_otg->regs->endptctrl[0] = - USB2D_ENDPTCTRL_TX_EP_ENABLE | USB2D_ENDPTCTRL_TX_EP_STALL | - USB2D_ENDPTCTRL_RX_EP_ENABLE | USB2D_ENDPTCTRL_RX_EP_STALL; + usbd_otg->regs->endptctrl[0] = USB2D_ENDPTCTRL_TX_EP_ENABLE | USB2D_ENDPTCTRL_TX_EP_STALL | + USB2D_ENDPTCTRL_RX_EP_ENABLE | USB2D_ENDPTCTRL_RX_EP_STALL; } int usbd_set_ep_stall(u32 endpoint, int ep_stall) @@ -1341,8 +1338,8 @@ static int _usbd_ep0_initialize() // Clear all device addresses, enabled setup requests, transmit events and flush all endpoints. usbd_otg->regs->periodiclistbase = 0; - usbd_otg->regs->endptsetupstat = usbd_otg->regs->endptsetupstat; - usbd_otg->regs->endptcomplete = usbd_otg->regs->endptcomplete; + usbd_otg->regs->endptsetupstat = usbd_otg->regs->endptsetupstat; + usbd_otg->regs->endptcomplete = usbd_otg->regs->endptcomplete; usbd_flush_endpoint(USB_EP_ALL); } diff --git a/bdk/usb/xusbd.c b/bdk/usb/xusbd.c index ec3b62d..3ebb908 100644 --- a/bdk/usb/xusbd.c +++ b/bdk/usb/xusbd.c @@ -397,9 +397,9 @@ typedef struct _xusbd_event_queues_t { event_trb_t xusb_event_ring_seg0[XUSB_TRB_SLOTS]; event_trb_t xusb_event_ring_seg1[XUSB_TRB_SLOTS]; - data_trb_t xusb_cntrl_event_queue[XUSB_TRB_SLOTS]; - data_trb_t xusb_bulkin_event_queue[XUSB_TRB_SLOTS]; - data_trb_t xusb_bulkout_event_queue[XUSB_TRB_SLOTS]; + data_trb_t xusb_cntrl_event_queue[XUSB_TRB_SLOTS]; + data_trb_t xusb_bulkin_event_queue[XUSB_TRB_SLOTS]; + data_trb_t xusb_bulkout_event_queue[XUSB_TRB_SLOTS]; volatile xusb_ep_ctx_t xusb_ep_ctxt[4]; } xusbd_event_queues_t; @@ -676,8 +676,8 @@ static int _xusb_ep_init_context(u32 ep_idx) { case XUSB_EP_CTRL_IN: usbd_xotg->cntrl_producer_cycle = 1; - usbd_xotg->cntrl_epenqueue_ptr = xusb_evtq->xusb_cntrl_event_queue; - usbd_xotg->cntrl_epdequeue_ptr = xusb_evtq->xusb_cntrl_event_queue; + usbd_xotg->cntrl_epenqueue_ptr = xusb_evtq->xusb_cntrl_event_queue; + usbd_xotg->cntrl_epdequeue_ptr = xusb_evtq->xusb_cntrl_event_queue; _xusb_ep_set_type_and_metrics(ep_idx, ep_ctxt); @@ -685,16 +685,16 @@ static int _xusb_ep_init_context(u32 ep_idx) ep_ctxt->trd_dequeueptr_hi = 0; link_trb = (link_trb_t *)&xusb_evtq->xusb_cntrl_event_queue[XUSB_LINK_TRB_IDX]; - link_trb->toggle_cycle = 1; + link_trb->toggle_cycle = 1; link_trb->ring_seg_ptrlo = (u32)xusb_evtq->xusb_cntrl_event_queue >> 4; link_trb->ring_seg_ptrhi = 0; - link_trb->trb_type = XUSB_TRB_LINK; + link_trb->trb_type = XUSB_TRB_LINK; break; case USB_EP_BULK_OUT: usbd_xotg->bulkout_producer_cycle = 1; - usbd_xotg->bulkout_epenqueue_ptr = xusb_evtq->xusb_bulkout_event_queue; - usbd_xotg->bulkout_epdequeue_ptr = xusb_evtq->xusb_bulkout_event_queue; + usbd_xotg->bulkout_epenqueue_ptr = xusb_evtq->xusb_bulkout_event_queue; + usbd_xotg->bulkout_epdequeue_ptr = xusb_evtq->xusb_bulkout_event_queue; _xusb_ep_set_type_and_metrics(ep_idx, ep_ctxt); @@ -702,16 +702,16 @@ static int _xusb_ep_init_context(u32 ep_idx) ep_ctxt->trd_dequeueptr_hi = 0; link_trb = (link_trb_t *)&xusb_evtq->xusb_bulkout_event_queue[XUSB_LINK_TRB_IDX]; - link_trb->toggle_cycle = 1; + link_trb->toggle_cycle = 1; link_trb->ring_seg_ptrlo = (u32)xusb_evtq->xusb_bulkout_event_queue >> 4; link_trb->ring_seg_ptrhi = 0; - link_trb->trb_type = XUSB_TRB_LINK; + link_trb->trb_type = XUSB_TRB_LINK; break; case USB_EP_BULK_IN: usbd_xotg->bulkin_producer_cycle = 1; - usbd_xotg->bulkin_epenqueue_ptr = xusb_evtq->xusb_bulkin_event_queue; - usbd_xotg->bulkin_epdequeue_ptr = xusb_evtq->xusb_bulkin_event_queue; + usbd_xotg->bulkin_epenqueue_ptr = xusb_evtq->xusb_bulkin_event_queue; + usbd_xotg->bulkin_epdequeue_ptr = xusb_evtq->xusb_bulkin_event_queue; _xusb_ep_set_type_and_metrics(ep_idx, ep_ctxt); @@ -719,10 +719,10 @@ static int _xusb_ep_init_context(u32 ep_idx) ep_ctxt->trd_dequeueptr_hi = 0; link_trb = (link_trb_t *)&xusb_evtq->xusb_bulkin_event_queue[XUSB_LINK_TRB_IDX]; - link_trb->toggle_cycle = 1; + link_trb->toggle_cycle = 1; link_trb->ring_seg_ptrlo = (u32)xusb_evtq->xusb_bulkin_event_queue >> 4; link_trb->ring_seg_ptrhi = 0; - link_trb->trb_type = XUSB_TRB_LINK; + link_trb->trb_type = XUSB_TRB_LINK; break; } @@ -744,7 +744,7 @@ static int _xusbd_ep_initialize(u32 ep_idx) if (!res) { XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_PAUSE) &= ~BIT(ep_idx); - XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_HALT) &= ~BIT(ep_idx); + XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_HALT) &= ~BIT(ep_idx); } return res; default: @@ -830,7 +830,7 @@ static void _xusb_init_phy() (void)XUSB_PADCTL(XUSB_PADCTL_USB2_OTG_PAD0_CTL_1); // Commit write. // Enable USB2 tracking clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK); CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) & 0xFFFFFF00) | 6; // Set trank divisor to 4. // Set tracking parameters and trigger it. @@ -939,10 +939,10 @@ int xusb_device_init() // AHB USB performance cfg. AHB_GIZMO(AHB_GIZMO_AHB_MEM) |= AHB_MEM_DONT_SPLIT_AHB_WR | AHB_MEM_ENB_FAST_REARBITRATE; - AHB_GIZMO(AHB_GIZMO_USB3) |= AHB_GIZMO_IMMEDIATE; - AHB_GIZMO(AHB_ARBITRATION_PRIORITY_CTRL) = PRIORITY_CTRL_WEIGHT(7) | PRIORITY_SELECT_USB3; - AHB_GIZMO(AHB_AHB_MEM_PREFETCH_CFG1) = - MEM_PREFETCH_ENABLE | MEM_PREFETCH_USB3_MST_ID | MEM_PREFETCH_ADDR_BNDRY(12) | 0x1000; // Addr boundary 64KB, Inactivity 4096 cycles. + AHB_GIZMO(AHB_GIZMO_USB3) |= AHB_GIZMO_IMMEDIATE; + AHB_GIZMO(AHB_ARBITRATION_PRIORITY_CTRL) = PRIORITY_CTRL_WEIGHT(7) | PRIORITY_SELECT_USB3; + AHB_GIZMO(AHB_AHB_MEM_PREFETCH_CFG1) = MEM_PREFETCH_ENABLE | MEM_PREFETCH_USB3_MST_ID | + MEM_PREFETCH_ADDR_BNDRY(12) | 0x1000; // Addr boundary 64KB, Inactivity 4096 cycles. // Initialize context. usbd_xotg = &usbd_xotg_controller_ctxt; @@ -950,8 +950,8 @@ int xusb_device_init() // Initialize event and EP rings. _xusbd_ep_init_event_ring(); - memset(xusb_evtq->xusb_cntrl_event_queue, 0, sizeof(xusb_evtq->xusb_cntrl_event_queue)); - memset(xusb_evtq->xusb_bulkin_event_queue, 0, sizeof(xusb_evtq->xusb_bulkin_event_queue)); + memset(xusb_evtq->xusb_cntrl_event_queue, 0, sizeof(xusb_evtq->xusb_cntrl_event_queue)); + memset(xusb_evtq->xusb_bulkin_event_queue, 0, sizeof(xusb_evtq->xusb_bulkin_event_queue)); memset(xusb_evtq->xusb_bulkout_event_queue, 0, sizeof(xusb_evtq->xusb_bulkout_event_queue)); // Initialize Control EP. @@ -1015,7 +1015,9 @@ static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) link_trb = (link_trb_t *)next_trb; link_trb->cycle = usbd_xotg->cntrl_producer_cycle & 1; link_trb->toggle_cycle = 1; + next_trb = (data_trb_t *)(link_trb->ring_seg_ptrlo << 4); + usbd_xotg->cntrl_producer_cycle ^= 1; } usbd_xotg->cntrl_epenqueue_ptr = next_trb; @@ -1031,7 +1033,9 @@ static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) link_trb = (link_trb_t *)next_trb; link_trb->cycle = usbd_xotg->bulkout_producer_cycle & 1; link_trb->toggle_cycle = 1; + next_trb = (data_trb_t *)(link_trb->ring_seg_ptrlo << 4); + usbd_xotg->bulkout_producer_cycle ^= 1; } usbd_xotg->bulkout_epenqueue_ptr = next_trb; @@ -1047,7 +1051,9 @@ static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) link_trb = (link_trb_t *)next_trb; link_trb->cycle = usbd_xotg->bulkin_producer_cycle & 1; link_trb->toggle_cycle = 1; + next_trb = (data_trb_t *)(link_trb->ring_seg_ptrlo << 4); + usbd_xotg->bulkin_producer_cycle ^= 1; } usbd_xotg->bulkin_epenqueue_ptr = next_trb; @@ -1064,9 +1070,11 @@ static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) { // Flush data before transfer. bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLEAN_WAY, false); + u32 target_id = (ep_idx << 8) & 0xFFFF; if (ep_idx == XUSB_EP_CTRL_IN) target_id |= usbd_xotg->ctrl_seq_num << 16; + XUSB_DEV_XHCI(XUSB_DEV_XHCI_DB) = target_id; } @@ -1075,10 +1083,10 @@ static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) static void _xusb_create_status_trb(status_trb_t *trb, usb_dir_t direction) { - trb->cycle = usbd_xotg->cntrl_producer_cycle & 1; - trb->ioc = 1; // Enable interrupt on completion. + trb->cycle = usbd_xotg->cntrl_producer_cycle & 1; + trb->ioc = 1; // Enable interrupt on completion. trb->trb_type = XUSB_TRB_STATUS; - trb->dir = direction; + trb->dir = direction; } static void _xusb_create_normal_trb(normal_trb_t *trb, u8 *buf, u32 len, usb_dir_t direction) @@ -1092,16 +1100,16 @@ static void _xusb_create_normal_trb(normal_trb_t *trb, u8 *buf, u32 len, usb_dir // Single TRB transfer. trb->td_size = 0; - trb->chain = 0; + trb->chain = 0; if (direction == USB_DIR_IN) producer_cycle = usbd_xotg->bulkin_producer_cycle & 1; else producer_cycle = usbd_xotg->bulkout_producer_cycle & 1; - trb->cycle = producer_cycle; - trb->isp = 1; // Enable interrupt on short packet. - trb->ioc = 1; // Enable interrupt on completion. + trb->cycle = producer_cycle; + trb->isp = 1; // Enable interrupt on short packet. + trb->ioc = 1; // Enable interrupt on completion. trb->trb_type = XUSB_TRB_NORMAL; } @@ -1114,13 +1122,13 @@ static void _xusb_create_data_trb(data_trb_t *trb, u8 *buf, u32 len, usb_dir_t d // Single TRB transfer. trb->td_size = 0; - trb->chain = 0; + trb->chain = 0; - trb->cycle = usbd_xotg->cntrl_producer_cycle & 1; - trb->isp = 1; // Enable interrupt on short packet. - trb->ioc = 1; // Enable interrupt on completion. + trb->cycle = usbd_xotg->cntrl_producer_cycle & 1; + trb->isp = 1; // Enable interrupt on short packet. + trb->ioc = 1; // Enable interrupt on completion. trb->trb_type = XUSB_TRB_DATA; - trb->dir = direction; + trb->dir = direction; } static int _xusb_issue_status_trb(usb_dir_t direction) @@ -1131,6 +1139,7 @@ static int _xusb_issue_status_trb(usb_dir_t direction) if (usbd_xotg->cntrl_epenqueue_ptr == usbd_xotg->cntrl_epdequeue_ptr || direction == USB_DIR_OUT) { _xusb_create_status_trb(&trb, direction); + res = _xusb_queue_trb(XUSB_EP_CTRL_IN, &trb, EP_RING_DOORBELL); usbd_xotg->wait_for_event_trb = XUSB_TRB_STATUS; } @@ -1146,6 +1155,7 @@ static int _xusb_issue_normal_trb(u8 *buf, u32 len, usb_dir_t direction) u32 ep_idx = USB_EP_BULK_IN; if (direction == USB_DIR_OUT) ep_idx = USB_EP_BULK_OUT; + int res = _xusb_queue_trb(ep_idx, &trb, EP_RING_DOORBELL); if (!res) usbd_xotg->wait_for_event_trb = XUSB_TRB_NORMAL; @@ -1161,6 +1171,7 @@ static int _xusb_issue_data_trb(u8 *buf, u32 len, usb_dir_t direction) if (usbd_xotg->cntrl_epenqueue_ptr == usbd_xotg->cntrl_epdequeue_ptr) { _xusb_create_data_trb(&trb, buf, len, direction); + res = _xusb_queue_trb(XUSB_EP_CTRL_IN, &trb, EP_RING_DOORBELL); if (!res) usbd_xotg->wait_for_event_trb = XUSB_TRB_DATA; @@ -1430,8 +1441,8 @@ static int _xusb_handle_get_ep_status(u32 ep_idx) u32 ep_mask = BIT(ep_idx); static u8 xusb_ep_status_descriptor[2] = {0}; - xusb_ep_status_descriptor[0] = - (XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_HALT) & ep_mask) ? USB_STATUS_EP_HALTED : USB_STATUS_EP_OK; + xusb_ep_status_descriptor[0] = (XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_HALT) & ep_mask) ? USB_STATUS_EP_HALTED : USB_STATUS_EP_OK; + return _xusb_issue_data_trb(xusb_ep_status_descriptor, 2, USB_DIR_IN); } @@ -1453,6 +1464,7 @@ static int _xusb_handle_get_class_request(usb_ctrl_setup_t *ctrl_setup) case USB_REQUEST_BULK_RESET: usbd_xotg->bulk_reset_req = true; return _xusb_issue_status_trb(USB_DIR_IN); // DELAYED_STATUS; + case USB_REQUEST_BULK_GET_MAX_LUN: if (!usbd_xotg->max_lun_set) goto stall; @@ -1939,7 +1951,7 @@ int xusb_device_enumerate(usb_gadget_type gadget) // Enable overrides for VBUS and ID. XUSB_PADCTL(XUSB_PADCTL_USB2_VBUS_ID) = (XUSB_PADCTL(XUSB_PADCTL_USB2_VBUS_ID) & ~(PADCTL_USB2_VBUS_ID_VBUS_OVR_MASK | PADCTL_USB2_VBUS_ID_SRC_MASK)) | - PADCTL_USB2_VBUS_ID_VBUS_OVR_EN | PADCTL_USB2_VBUS_ID_SRC_ID_OVR_EN; + PADCTL_USB2_VBUS_ID_VBUS_OVR_EN | PADCTL_USB2_VBUS_ID_SRC_ID_OVR_EN; // Clear halt for LTSSM. XUSB_DEV_XHCI(XUSB_DEV_XHCI_PORTHALT) &= ~XHCI_PORTHALT_HALT_LTSSM; @@ -1950,16 +1962,15 @@ int xusb_device_enumerate(usb_gadget_type gadget) // Override access to High/Full Speed. XUSB_DEV_XHCI(XUSB_DEV_XHCI_CFG_DEV_FE) = (XUSB_DEV_XHCI(XUSB_DEV_XHCI_CFG_DEV_FE) & ~XHCI_CFG_DEV_FE_PORTREGSEL_MASK) | XHCI_CFG_DEV_FE_PORTREGSEL_HSFS; - XUSB_DEV_XHCI(XUSB_DEV_XHCI_PORTSC) = - (XUSB_DEV_XHCI(XUSB_DEV_XHCI_PORTSC) & ~XHCI_PORTSC_PLS_MASK) | XHCI_PORTSC_LWS | XHCI_PORTSC_PLS_RXDETECT; + XUSB_DEV_XHCI(XUSB_DEV_XHCI_PORTSC) = (XUSB_DEV_XHCI(XUSB_DEV_XHCI_PORTSC) & ~XHCI_PORTSC_PLS_MASK) | XHCI_PORTSC_LWS | XHCI_PORTSC_PLS_RXDETECT; XUSB_DEV_XHCI(XUSB_DEV_XHCI_CFG_DEV_FE) &= ~XHCI_CFG_DEV_FE_PORTREGSEL_MASK; // Enable VBUS and set ID to Float. XUSB_PADCTL(XUSB_PADCTL_USB2_VBUS_ID) = (XUSB_PADCTL(XUSB_PADCTL_USB2_VBUS_ID) & ~PADCTL_USB2_VBUS_ID_OVR_MASK) | - PADCTL_USB2_VBUS_ID_OVR_FLOAT | PADCTL_USB2_VBUS_ID_VBUS_ON; + PADCTL_USB2_VBUS_ID_OVR_FLOAT | PADCTL_USB2_VBUS_ID_VBUS_ON; usbd_xotg->wait_for_event_trb = XUSB_TRB_SETUP; - usbd_xotg->device_state = XUSB_DEFAULT; + usbd_xotg->device_state = XUSB_DEFAULT; // Timeout if cable or communication isn't started in 1.5 minutes. u32 timer = get_tmr_ms() + 90000; @@ -2014,6 +2025,7 @@ int xusb_device_ep1_out_read(u8 *buf, u32 len, u32 *bytes_read, u32 sync_tries) int res = USB_RES_OK; usbd_xotg->tx_count[USB_DIR_OUT] = 0; usbd_xotg->tx_bytes[USB_DIR_OUT] = len; + _xusb_issue_normal_trb(buf, len, USB_DIR_OUT); usbd_xotg->tx_count[USB_DIR_OUT]++; @@ -2083,6 +2095,7 @@ int xusb_device_ep1_in_write(u8 *buf, u32 len, u32 *bytes_written, u32 sync_trie int res = USB_RES_OK; usbd_xotg->tx_count[USB_DIR_IN] = 0; usbd_xotg->tx_bytes[USB_DIR_IN] = len; + _xusb_issue_normal_trb(buf, len, USB_DIR_IN); usbd_xotg->tx_count[USB_DIR_IN]++; @@ -2132,7 +2145,7 @@ bool xusb_device_class_send_max_lun(u8 max_lun) // Timeout if get MAX_LUN request doesn't happen in 10s. u32 timer = get_tmr_ms() + 10000; - usbd_xotg->max_lun = max_lun; + usbd_xotg->max_lun = max_lun; usbd_xotg->max_lun_set = true; // Wait for request and transfer start. diff --git a/bdk/utils/ini.c b/bdk/utils/ini.c index 6177d68..bc0afc5 100644 --- a/bdk/utils/ini.c +++ b/bdk/utils/ini.c @@ -57,11 +57,11 @@ int ini_parse(link_t *dst, char *ini_path, bool is_dir) { FIL fp; u32 lblen; - u32 pathlen = strlen(ini_path); u32 k = 0; + u32 pathlen = strlen(ini_path); ini_sec_t *csec = NULL; - char *lbuf = NULL; + char *lbuf = NULL; char *filelist = NULL; char *filename = (char *)malloc(256); @@ -142,8 +142,8 @@ int ini_parse(link_t *dst, char *ini_path, bool is_dir) u32 i = _find_section_name(lbuf, lblen, '='); // Calculate total allocation size. - u32 klen = strlen(&lbuf[0]) + 1; - u32 vlen = strlen(&lbuf[i + 1]) + 1; + u32 klen = strlen(&lbuf[0]) + 1; + u32 vlen = strlen(&lbuf[i + 1]) + 1; char *buf = calloc(sizeof(ini_kv_t) + klen + vlen, 1); ini_kv_t *kv = (ini_kv_t *)buf;