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https://github.com/CTCaer/hekate
synced 2024-12-22 03:11:16 +00:00
bdk: various functionality independent changes
This commit is contained in:
CTCaer
parent
5894062b93
commit
70504c295e
18 changed files with 56 additions and 28 deletions
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@ -657,23 +657,24 @@
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/* Switch Panels:
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*
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* 6.2" panels for Icosa and Iowa skus:
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* 6.2" panels for Icosa and Iowa SKUs:
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* [10] 81 [26]: JDI LPM062M326A
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* [10] 96 [09]: JDI LAM062M109A
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* [20] 93 [0F]: InnoLux P062CCA-AZ1 (Rev A1)
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* [20] 95 [0F]: InnoLux P062CCA-AZ2 (Rev B1)
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* [20] 96 [0F]: InnoLux P062CCA-AZ3 [UNCONFIRMED MODEL REV]
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* [20] 97 [0F]: InnoLux P062CCA-??? [UNCONFIRMED MODEL REV]
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* [20] 98 [0F]: InnoLux P062CCA-??? [UNCONFIRMED MODEL REV]
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* [30] 94 [0F]: AUO A062TAN01 (59.06A33.001)
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* [30] 95 [0F]: AUO A062TAN02 (59.06A33.002)
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* [30] XX [0F]: AUO A062TAN03 (59.06A33.003) [UNCONFIRMED ID]
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*
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* 5.5" panels for Hoag skus:
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* 5.5" panels for Hoag SKUs:
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* [20] 94 [10]: InnoLux 2J055IA-27A (Rev B1)
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* [30] 93 [10]: AUO A055TAN01 (59.05A30.001)
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* [40] XX [10]: Vendor 40 [UNCONFIRMED ID]
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*
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* 7.0" OLED panels for Aula skus:
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* 7.0" OLED panels for Aula SKUs:
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* [50] 9B [20]: Samsung AMS699VC01-0 (Rev 2.5)
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*/
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@ -410,7 +410,7 @@ int touch_power_on()
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gpio_output_enable(GPIO_PORT_J, GPIO_PIN_7, GPIO_OUTPUT_ENABLE);
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gpio_write(GPIO_PORT_J, GPIO_PIN_7, GPIO_HIGH);
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// IRQ and more.
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// Touscreen IRQ.
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// PINMUX_AUX(PINMUX_AUX_TOUCH_INT) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP | 3;
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// gpio_config(GPIO_PORT_X, GPIO_PIN_1, GPIO_MODE_GPIO);
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// gpio_write(GPIO_PORT_X, GPIO_PIN_1, GPIO_LOW);
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@ -464,11 +464,19 @@
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#define MC_UNTRANSLATED_REGION_CHECK 0x948
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#define MC_DA_CONFIG0 0x9dc
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// MC_VIDEO_PROTECT_REG_CTRL
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#define VPR_LOCK_MODE_SHIFT 0
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#define VPR_CTRL_UNLOCKED (0 << VPR_LOCK_MODE_SHIFT)
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#define VPR_CTRL_LOCKED (1 << VPR_LOCK_MODE_SHIFT)
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#define VPR_PROTECT_MODE_SHIFT 1
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#define SEC_CTRL_SECURE (0 << VPR_PROTECT_MODE_SHIFT)
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#define VPR_CTRL_TZ_SECURE (1 << VPR_PROTECT_MODE_SHIFT)
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// MC_SECURITY_CARVEOUTX_CFG0
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// Mode of LOCK_MODE.
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#define PROTECT_MODE_SHIFT 0
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#define SEC_CARVEOUT_CFG_SECURE (0 << PROTECT_MODE_SHIFT0)
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#define SEC_CARVEOUT_CFG_TZ_SECURE (1 << PROTECT_MODE_SHIFT0)
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#define SEC_CARVEOUT_CFG_SECURE (0 << PROTECT_MODE_SHIFT)
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#define SEC_CARVEOUT_CFG_TZ_SECURE (1 << PROTECT_MODE_SHIFT)
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// Enables PROTECT_MODE.
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#define LOCK_MODE_SHIFT 1
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#define SEC_CARVEOUT_CFG_UNLOCKED (0 << LOCK_MODE_SHIFT)
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@ -19,8 +19,8 @@
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#include "minerva.h"
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#include <soc/clock.h>
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#include <ianos/ianos.h>
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#include <mem/emc.h>
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#include <soc/clock.h>
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#include <soc/fuse.h>
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#include <soc/hw_init.h>
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@ -30,6 +30,7 @@
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#define MC_SMMU_TLB_FLUSH 0x30
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#define MC_SMMU_PTC_FLUSH 0x34
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#define MC_SMMU_ASID_SECURITY 0x38
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#define MC_SMMU_AVPC_ASID 0x23C
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#define MC_SMMU_TSEC_ASID 0x294
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#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
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#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
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@ -95,9 +95,9 @@
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#define MAX77620_IRQSD_PFI_SD1 BIT(6)
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#define MAX77620_IRQSD_PFI_SD0 BIT(7)
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#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 // LDO number that irq occured.
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#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 // LDO number that irq occurred.
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#define MAX77620_REG_IRQ_MSK_L0_7 0x10
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#define MAX77620_REG_IRQ_LVL2_L8 0x09 // LDO number that irq occured. Only bit0: LDO8 is valid.
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#define MAX77620_REG_IRQ_LVL2_L8 0x09 // LDO number that irq occurred. Only bit0: LDO8 is valid.
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#define MAX77620_REG_IRQ_MSK_L8 0x11
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#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A // Edge detection interrupt.
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@ -139,8 +139,8 @@
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#define MAX77620_REG_DVSSD0 0x1B
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#define MAX77620_REG_DVSSD1 0x1C
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#define MAX77620_SDX_VOLT_MASK 0xFF
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#define MAX77620_SD0_VOLT_MASK 0x3F
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#define MAX77620_SD1_VOLT_MASK 0x7F
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#define MAX77620_SD0_VOLT_MASK 0x7F // Max is 0x40.
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#define MAX77620_SD1_VOLT_MASK 0x7F // Max is 0x4C.
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#define MAX77620_LDO_VOLT_MASK 0x3F
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#define MAX77620_REG_SD0_CFG 0x1D
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@ -20,6 +20,14 @@
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#include <utils/types.h>
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/*
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* SDx actual min is 625 mV. Multipliers 0/1 reserved.
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* SD0 max is 1400 mV
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* SD1 max is 1550 mV
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* SD2 max is 3787.5 mV
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* SD3 max is 3787.5 mV
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*/
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/*
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* Switch Power domains (max77620):
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* Name | Usage | uV step | uV min | uV default | uV max | Init
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@ -17,8 +17,8 @@
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#ifndef _MAX77812_H_
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#define _MAX77812_H_
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#define MAX77812_PHASE31_CPU_I2C_ADDR 0x31 // 2 Outputs: 3-phase M1 + 1-phase M4.
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#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
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#define MAX77812_PHASE31_CPU_I2C_ADDR 0x31 // High power GPU. 2 Outputs: 3-phase M1 + 1-phase M4.
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#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // Low power GPU. 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
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#define MAX77812_REG_RSET 0x00
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#define MAX77812_REG_INT_SRC 0x01
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@ -74,14 +74,14 @@
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#define MAX77812_REG_GLB_CFG2 0x34
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#define MAX77812_REG_GLB_CFG3 0x35
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/*! Protected area and settings only for MAX77812_REG_VERSION 4 */
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/*! Protected area and settings only for MAX77812_ES2_VERSION */
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#define MAX77812_REG_GLB_CFG4 0x36
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#define MAX77812_REG_GLB_CFG5 0x37
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#define MAX77812_REG_GLB_CFG6 0x38
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#define MAX77812_REG_GLB_CFG7 0x39
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#define MAX77812_REG_GLB_CFG8 0x3A
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#define MAX77812_REG_PROT_ACCESS 0xFD
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#define MAX77812_REG_MAX 0xFE
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#define MAX77812_REG_MAX 0xFD
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#define MAX77812_REG_EN_CTRL_MASK(n) BIT(n)
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#define MAX77812_START_SLEW_RATE_MASK 0x07
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@ -304,6 +304,8 @@
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#define SE_STATUS_STATE_WAIT_OUT 2
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#define SE_STATUS_STATE_WAIT_IN 3
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#define SE_STATUS_STATE_MASK 3
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#define SE_STATUS_MEM_IF_IDLE (0 << 2)
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#define SE_STATUS_MEM_IF_BUSY BIT(2)
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#define SE_ERR_STATUS_REG 0x804
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#define SE_ERR_STATUS_SE_NS_ACCESS BIT(0)
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@ -91,6 +91,7 @@ void ccplex_boot_cpu0(u32 entry)
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// Set reset vector.
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SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN;
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SB(SB_AA64_RESET_HIGH) = 0;
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// Non-secure reset vector write disable.
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SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS;
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(void)SB(SB_CSR);
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@ -117,6 +117,7 @@
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON 0x3E8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 0x3EC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
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@ -37,6 +37,8 @@
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#define FUSE_DISABLEREGPROGRAM 0x2C
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#define FUSE_WRITE_ACCESS_SW 0x30
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#define FUSE_PWR_GOOD_SW 0x34
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/*! Fuse Cached registers */
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#define FUSE_SKU_INFO 0x110
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#define FUSE_CPU_SPEEDO_0_CALIB 0x114
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#define FUSE_CPU_IDDQ_CALIB 0x118
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@ -64,8 +66,10 @@
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#define FUSE_OPT_WAFER_ID 0x210
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#define FUSE_OPT_X_COORDINATE 0x214
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#define FUSE_OPT_Y_COORDINATE 0x218
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#define FUSE_OPT_OPS_RESERVED 0x220
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#define FUSE_GPU_IDDQ_CALIB 0x228
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#define FUSE_USB_CALIB_EXT 0x350
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#define FUSE_RESERVED_FIELD 0x354
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#define FUSE_RESERVED_ODM28_T210B01 0x240
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@ -21,6 +21,7 @@
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#include <utils/types.h>
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#define BL_MAGIC_CRBOOT_SLD 0x30444C53 // SLD0, seamless display type 0.
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#define BL_MAGIC_HEKATF_SLD 0x31444C53 // SLD1, seamless display type 1.
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#define BL_MAGIC_BROKEN_HWI 0xBAADF00D // Broken hwinit.
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extern u32 hw_rst_status;
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@ -53,7 +53,7 @@
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#define PMC_CRYPTO_OP_SE_DISABLE 1
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#define APBDEV_PMC_SCRATCH33 0x120
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#define APBDEV_PMC_SCRATCH37 0x130
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#define PMC_SCRATCH37_KERNEL_PANIC_FLAG BIT(24)
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#define PMC_SCRATCH37_KERNEL_PANIC_MAGIC 0x4E415054
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#define APBDEV_PMC_SCRATCH40 0x13C
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#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
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#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000
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@ -103,6 +103,9 @@
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#define APBDEV_PMC_SCRATCH188 0x810
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#define APBDEV_PMC_SCRATCH190 0x818
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#define APBDEV_PMC_SCRATCH200 0x840
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#define APBDEV_PMC_SECURE_SCRATCH108 0xB08
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#define APBDEV_PMC_SECURE_SCRATCH109 0xB0C
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#define APBDEV_PMC_SECURE_SCRATCH110 0xB10
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#define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8
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#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
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#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0
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@ -35,6 +35,7 @@
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#define AHBDMA_BASE 0x60008000
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#define SYSREG_BASE 0x6000C000
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#define SB_BASE (SYSREG_BASE + 0x200)
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#define ACTMON_BASE 0x6000C800
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#define GPIO_BASE 0x6000D000
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#define GPIO_1_BASE (GPIO_BASE)
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#define GPIO_2_BASE (GPIO_BASE + 0x100)
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@ -89,6 +90,7 @@
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#define SYSREG(off) _REG(SYSREG_BASE, off)
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#define AHB_GIZMO(off) _REG(SYSREG_BASE, off)
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#define SB(off) _REG(SB_BASE, off)
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#define ACTMON(off) _REG(ACTMON_BASE, off)
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#define GPIO(off) _REG(GPIO_BASE, off)
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#define GPIO_1(off) _REG(GPIO_1_BASE, off)
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#define GPIO_2(off) _REG(GPIO_2_BASE, off)
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@ -184,6 +186,8 @@
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#define MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB.
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#define MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21)
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#define MEM_PREFETCH_ENABLE BIT(31)
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#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xFC
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#define MEM_WRQUE_SE_MST_ID BIT(14)
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#define AHB_AHB_SPARE_REG 0x110
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/*! Misc registers. */
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@ -192,6 +196,7 @@
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#define APB_MISC_GP_HIDREV 0x804
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#define GP_HIDREV_MAJOR_T210 0x1
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#define GP_HIDREV_MAJOR_T210B01 0x2
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#define APB_MISC_GP_ASDBGREG 0x810
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#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
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#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
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@ -113,13 +113,6 @@ void s_printf(char *out_buf, const char *fmt, ...)
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case 'X':
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_s_putn(va_arg(ap, u32), 16, fill, fcnt);
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break;
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case 'k':
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//gfx_con.fgcol = va_arg(ap, u32);
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break;
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case 'K':
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//gfx_con.bgcol = va_arg(ap, u32);
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//gfx_con.fillbg = 1;
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break;
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case '%':
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_s_putc('%');
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break;
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@ -46,9 +46,9 @@ typedef volatile unsigned short vu16;
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typedef volatile unsigned int vu32;
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#ifdef __aarch64__
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typedef u64 uptr;
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typedef unsigned long long uptr;
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#else /* __arm__ or __thumb__ */
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typedef u32 uptr;
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typedef unsigned long uptr;
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#endif
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/* Important */
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@ -137,8 +137,8 @@ typedef struct __attribute__((__packed__)) _boot_cfg_t
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{
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struct
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{
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char id[8]; // 7 char ASCII null teminated.
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char emummc_path[0x78]; // emuMMC/XXX, ASCII null teminated.
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char id[8]; // 7 char ASCII null terminated.
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char emummc_path[0x78]; // emuMMC/XXX, ASCII null terminated.
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};
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u8 ums; // nyx_ums_type.
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u8 xt_str[0x80];
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