bdk: various functionality independent changes

bdk/display/di.h

@@ -657,23 +657,24 @@
 
 /* Switch Panels:
  *
- * 6.2" panels for Icosa and Iowa skus:
+ * 6.2" panels for Icosa and Iowa SKUs:
  * [10] 81 [26]: JDI LPM062M326A
  * [10] 96 [09]: JDI LAM062M109A
  * [20] 93 [0F]: InnoLux P062CCA-AZ1 (Rev A1)
  * [20] 95 [0F]: InnoLux P062CCA-AZ2 (Rev B1)
  * [20] 96 [0F]: InnoLux P062CCA-AZ3 [UNCONFIRMED MODEL REV]
+ * [20] 97 [0F]: InnoLux P062CCA-??? [UNCONFIRMED MODEL REV]
  * [20] 98 [0F]: InnoLux P062CCA-??? [UNCONFIRMED MODEL REV]
  * [30] 94 [0F]: AUO A062TAN01 (59.06A33.001)
  * [30] 95 [0F]: AUO A062TAN02 (59.06A33.002)
  * [30] XX [0F]: AUO A062TAN03 (59.06A33.003) [UNCONFIRMED ID]
  *
- * 5.5" panels for Hoag skus:
+ * 5.5" panels for Hoag SKUs:
  * [20] 94 [10]: InnoLux 2J055IA-27A (Rev B1)
  * [30] 93 [10]: AUO A055TAN01 (59.05A30.001)
  * [40] XX [10]: Vendor 40 [UNCONFIRMED ID]
  *
- * 7.0" OLED panels for Aula skus:
+ * 7.0" OLED panels for Aula SKUs:
  * [50] 9B [20]: Samsung AMS699VC01-0 (Rev 2.5)
  */
 

bdk/input/touch.c

@@ -410,7 +410,7 @@ int touch_power_on()
 	gpio_output_enable(GPIO_PORT_J, GPIO_PIN_7, GPIO_OUTPUT_ENABLE);
 	gpio_write(GPIO_PORT_J, GPIO_PIN_7, GPIO_HIGH);
 
-	// IRQ and more.
+	// Touscreen IRQ.
 	// PINMUX_AUX(PINMUX_AUX_TOUCH_INT) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP | 3;
 	// gpio_config(GPIO_PORT_X, GPIO_PIN_1, GPIO_MODE_GPIO);
 	// gpio_write(GPIO_PORT_X, GPIO_PIN_1, GPIO_LOW);

bdk/mem/mc_t210.h

@@ -464,11 +464,19 @@
 #define MC_UNTRANSLATED_REGION_CHECK                            0x948
 #define MC_DA_CONFIG0                                           0x9dc
 
+// MC_VIDEO_PROTECT_REG_CTRL
+#define VPR_LOCK_MODE_SHIFT 0
+#define VPR_CTRL_UNLOCKED  (0 << VPR_LOCK_MODE_SHIFT)
+#define VPR_CTRL_LOCKED    (1 << VPR_LOCK_MODE_SHIFT)
+#define VPR_PROTECT_MODE_SHIFT 1
+#define SEC_CTRL_SECURE    (0 << VPR_PROTECT_MODE_SHIFT)
+#define VPR_CTRL_TZ_SECURE (1 << VPR_PROTECT_MODE_SHIFT)
+
 // MC_SECURITY_CARVEOUTX_CFG0
 // Mode of LOCK_MODE.
 #define PROTECT_MODE_SHIFT 0
-#define SEC_CARVEOUT_CFG_SECURE    (0 << PROTECT_MODE_SHIFT0)
+#define SEC_CARVEOUT_CFG_SECURE    (0 << PROTECT_MODE_SHIFT)
-#define SEC_CARVEOUT_CFG_TZ_SECURE (1 << PROTECT_MODE_SHIFT0)
+#define SEC_CARVEOUT_CFG_TZ_SECURE (1 << PROTECT_MODE_SHIFT)
 // Enables PROTECT_MODE.
 #define LOCK_MODE_SHIFT 1
 #define SEC_CARVEOUT_CFG_UNLOCKED (0 << LOCK_MODE_SHIFT)

bdk/mem/minerva.c

@@ -19,8 +19,8 @@
 
 #include "minerva.h"
 
-#include <soc/clock.h>
 #include <ianos/ianos.h>
+#include <mem/emc.h>
 #include <soc/clock.h>
 #include <soc/fuse.h>
 #include <soc/hw_init.h>

bdk/mem/smmu.h

@@ -30,6 +30,7 @@
 #define MC_SMMU_TLB_FLUSH            0x30
 #define MC_SMMU_PTC_FLUSH            0x34
 #define MC_SMMU_ASID_SECURITY        0x38
+#define MC_SMMU_AVPC_ASID            0x23C
 #define MC_SMMU_TSEC_ASID            0x294
 #define MC_SMMU_TRANSLATION_ENABLE_0 0x228
 #define MC_SMMU_TRANSLATION_ENABLE_1 0x22c

bdk/power/max77620.h

@@ -95,9 +95,9 @@
 #define  MAX77620_IRQSD_PFI_SD1               BIT(6)
 #define  MAX77620_IRQSD_PFI_SD0               BIT(7)
 
-#define MAX77620_REG_IRQ_LVL2_L0_7  0x08 // LDO number that irq occured.
+#define MAX77620_REG_IRQ_LVL2_L0_7  0x08 // LDO number that irq occurred.
 #define MAX77620_REG_IRQ_MSK_L0_7   0x10
-#define MAX77620_REG_IRQ_LVL2_L8    0x09 // LDO number that irq occured. Only bit0: LDO8 is valid.
+#define MAX77620_REG_IRQ_LVL2_L8    0x09 // LDO number that irq occurred. Only bit0: LDO8 is valid.
 #define MAX77620_REG_IRQ_MSK_L8     0x11
 #define MAX77620_REG_IRQ_LVL2_GPIO  0x0A // Edge detection interrupt.
 
@@ -139,8 +139,8 @@
 #define MAX77620_REG_DVSSD0         0x1B
 #define MAX77620_REG_DVSSD1         0x1C
 #define  MAX77620_SDX_VOLT_MASK               0xFF
-#define  MAX77620_SD0_VOLT_MASK               0x3F
+#define  MAX77620_SD0_VOLT_MASK               0x7F // Max is 0x40.
-#define  MAX77620_SD1_VOLT_MASK               0x7F
+#define  MAX77620_SD1_VOLT_MASK               0x7F // Max is 0x4C.
 #define  MAX77620_LDO_VOLT_MASK               0x3F
 
 #define MAX77620_REG_SD0_CFG        0x1D

bdk/power/max7762x.h

@@ -20,6 +20,14 @@
 
 #include <utils/types.h>
 
+/*
+ * SDx actual min is 625 mV. Multipliers 0/1 reserved.
+ * SD0 max is 1400 mV
+ * SD1 max is 1550 mV
+ * SD2 max is 3787.5 mV
+ * SD3 max is 3787.5 mV
+ */
+
 /*
 * Switch Power domains (max77620):
 * Name  | Usage         | uV step | uV min | uV default | uV max  | Init

bdk/power/max77812.h

@@ -17,8 +17,8 @@
 #ifndef _MAX77812_H_
 #define _MAX77812_H_
 
-#define MAX77812_PHASE31_CPU_I2C_ADDR  0x31 // 2 Outputs: 3-phase M1 + 1-phase M4.
+#define MAX77812_PHASE31_CPU_I2C_ADDR  0x31 // High power GPU. 2 Outputs: 3-phase M1 + 1-phase M4.
-#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
+#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // Low  power GPU. 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
 
 #define MAX77812_REG_RSET			0x00
 #define MAX77812_REG_INT_SRC		0x01
@@ -74,14 +74,14 @@
 #define MAX77812_REG_GLB_CFG2		0x34
 #define MAX77812_REG_GLB_CFG3		0x35
 
-/*! Protected area and settings only for MAX77812_REG_VERSION 4 */
+/*! Protected area and settings only for MAX77812_ES2_VERSION */
 #define MAX77812_REG_GLB_CFG4		0x36
 #define MAX77812_REG_GLB_CFG5		0x37
 #define MAX77812_REG_GLB_CFG6		0x38
 #define MAX77812_REG_GLB_CFG7		0x39
 #define MAX77812_REG_GLB_CFG8		0x3A
 #define MAX77812_REG_PROT_ACCESS	0xFD
-#define MAX77812_REG_MAX			0xFE
+#define MAX77812_REG_MAX			0xFD
 
 #define MAX77812_REG_EN_CTRL_MASK(n)		BIT(n)
 #define MAX77812_START_SLEW_RATE_MASK		0x07

bdk/sec/se_t210.h

@@ -304,6 +304,8 @@
 #define  SE_STATUS_STATE_WAIT_OUT 2
 #define  SE_STATUS_STATE_WAIT_IN  3
 #define  SE_STATUS_STATE_MASK     3
+#define  SE_STATUS_MEM_IF_IDLE    (0 << 2)
+#define  SE_STATUS_MEM_IF_BUSY    BIT(2)
 
 #define SE_ERR_STATUS_REG 0x804
 #define  SE_ERR_STATUS_SE_NS_ACCESS    BIT(0)

bdk/soc/ccplex.c

@@ -91,6 +91,7 @@ void ccplex_boot_cpu0(u32 entry)
 	// Set reset vector.
 	SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN;
 	SB(SB_AA64_RESET_HIGH) = 0;
+
 	// Non-secure reset vector write disable.
 	SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS;
 	(void)SB(SB_CSR);

bdk/soc/clock.c

@@ -79,7 +79,7 @@ static clock_t _clock_sor0 = {
 	CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NOT_USED,                         CLK_X_SOR0,     0, 0
 };
 static clock_t _clock_sor1 = {
-	CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1,   CLK_X_SOR1,     0, 2 //204MHz.
+	CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1,   CLK_X_SOR1,     0, 2 // 204MHz.
 };
 static clock_t _clock_kfuse = {
 	CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE,                        CLK_H_KFUSE,    0, 0

bdk/soc/clock.h

@@ -117,6 +117,7 @@
 #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
 #define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4
+#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON 0x3E8
 #define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 0x3EC
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410

bdk/soc/fuse.h

@@ -37,6 +37,8 @@
 #define FUSE_DISABLEREGPROGRAM 0x2C
 #define FUSE_WRITE_ACCESS_SW 0x30
 #define FUSE_PWR_GOOD_SW 0x34
+
+/*! Fuse Cached registers */
 #define FUSE_SKU_INFO 0x110
 #define FUSE_CPU_SPEEDO_0_CALIB 0x114
 #define FUSE_CPU_IDDQ_CALIB 0x118
@@ -64,8 +66,10 @@
 #define FUSE_OPT_WAFER_ID 0x210
 #define FUSE_OPT_X_COORDINATE 0x214
 #define FUSE_OPT_Y_COORDINATE 0x218
+#define FUSE_OPT_OPS_RESERVED 0x220
 #define FUSE_GPU_IDDQ_CALIB	0x228
 #define FUSE_USB_CALIB_EXT 0x350
+#define FUSE_RESERVED_FIELD 0x354
 
 #define FUSE_RESERVED_ODM28_T210B01 0x240
 

bdk/soc/hw_init.h

@@ -21,6 +21,7 @@
 #include <utils/types.h>
 
 #define BL_MAGIC_CRBOOT_SLD 0x30444C53 // SLD0, seamless display type 0.
+#define BL_MAGIC_HEKATF_SLD 0x31444C53 // SLD1, seamless display type 1.
 #define BL_MAGIC_BROKEN_HWI 0xBAADF00D // Broken hwinit.
 
 extern u32 hw_rst_status;

bdk/soc/pmc.h

@@ -53,7 +53,7 @@
 #define  PMC_CRYPTO_OP_SE_DISABLE 1
 #define APBDEV_PMC_SCRATCH33 0x120
 #define APBDEV_PMC_SCRATCH37 0x130
-#define  PMC_SCRATCH37_KERNEL_PANIC_FLAG BIT(24)
+#define  PMC_SCRATCH37_KERNEL_PANIC_MAGIC 0x4E415054
 #define APBDEV_PMC_SCRATCH40 0x13C
 #define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
 #define  PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000
@@ -103,6 +103,9 @@
 #define APBDEV_PMC_SCRATCH188 0x810
 #define APBDEV_PMC_SCRATCH190 0x818
 #define APBDEV_PMC_SCRATCH200 0x840
+#define APBDEV_PMC_SECURE_SCRATCH108 0xB08
+#define APBDEV_PMC_SECURE_SCRATCH109 0xB0C
+#define APBDEV_PMC_SECURE_SCRATCH110 0xB10
 #define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8
 #define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
 #define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0

bdk/soc/t210.h

@@ -35,6 +35,7 @@
 #define AHBDMA_BASE 0x60008000
 #define SYSREG_BASE 0x6000C000
 #define SB_BASE (SYSREG_BASE + 0x200)
+#define ACTMON_BASE 0x6000C800
 #define GPIO_BASE 0x6000D000
 #define GPIO_1_BASE (GPIO_BASE)
 #define GPIO_2_BASE (GPIO_BASE + 0x100)
@@ -89,6 +90,7 @@
 #define SYSREG(off) _REG(SYSREG_BASE, off)
 #define AHB_GIZMO(off) _REG(SYSREG_BASE, off)
 #define SB(off) _REG(SB_BASE, off)
+#define ACTMON(off) _REG(ACTMON_BASE, off)
 #define GPIO(off) _REG(GPIO_BASE, off)
 #define GPIO_1(off) _REG(GPIO_1_BASE, off)
 #define GPIO_2(off) _REG(GPIO_2_BASE, off)
@@ -184,6 +186,8 @@
 #define  MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB.
 #define  MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21)
 #define  MEM_PREFETCH_ENABLE BIT(31)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xFC
+#define  MEM_WRQUE_SE_MST_ID BIT(14)
 #define AHB_AHB_SPARE_REG 0x110
 
 /*! Misc registers. */
@@ -192,6 +196,7 @@
 #define APB_MISC_GP_HIDREV 0x804
 #define  GP_HIDREV_MAJOR_T210    0x1
 #define  GP_HIDREV_MAJOR_T210B01 0x2
+#define APB_MISC_GP_ASDBGREG 0x810
 #define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
 #define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
 #define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98

bdk/utils/sprintf.c

@@ -113,13 +113,6 @@ void s_printf(char *out_buf, const char *fmt, ...)
 			case 'X':
 				_s_putn(va_arg(ap, u32), 16, fill, fcnt);
 				break;
-			case 'k':
-				//gfx_con.fgcol = va_arg(ap, u32);
-				break;
-			case 'K':
-				//gfx_con.bgcol = va_arg(ap, u32);
-				//gfx_con.fillbg = 1;
-				break;
 			case '%':
 				_s_putc('%');
 				break;

bdk/utils/types.h

@@ -46,9 +46,9 @@ typedef volatile unsigned short vu16;
 typedef volatile unsigned int vu32;
 
 #ifdef __aarch64__
-typedef u64 uptr;
+typedef unsigned long long uptr;
 #else /* __arm__ or __thumb__ */
-typedef u32 uptr;
+typedef unsigned long uptr;
 #endif
 
 /* Important */
@@ -137,8 +137,8 @@ typedef struct __attribute__((__packed__)) _boot_cfg_t
 	{
 		struct
 		{
-			char id[8]; // 7 char ASCII null teminated.
+			char id[8]; // 7 char ASCII null terminated.
-			char emummc_path[0x78]; // emuMMC/XXX, ASCII null teminated.
+			char emummc_path[0x78]; // emuMMC/XXX, ASCII null terminated.
 		};
 		u8 ums; // nyx_ums_type.
 		u8 xt_str[0x80];