mirror of
https://github.com/CTCaer/hekate
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nyx: remove nx_emmc_bis objects as they reside in bdk now
This commit is contained in:
CTCaer
parent
49f34581bb
commit
6be12f32e6
2 changed files with 0 additions and 538 deletions
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@ -1,308 +0,0 @@
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/*
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* eMMC BIS driver for Nintendo Switch
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*
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* Copyright (c) 2019-2020 shchmue
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* Copyright (c) 2019-2022 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <bdk.h>
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#define BIS_CLUSTER_SECTORS 32
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#define BIS_CLUSTER_SIZE 16384
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#define BIS_CACHE_MAX_ENTRIES 16384
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#define BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY -1
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typedef struct _cluster_cache_t
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{
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u32 cluster_idx; // Index of the cluster in the partition.
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bool dirty; // Has been modified without write-back flag.
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u8 data[BIS_CLUSTER_SIZE]; // The cached cluster itself. Aligned to 8 bytes for DMA engine.
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} cluster_cache_t;
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typedef struct _bis_cache_t
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{
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bool full;
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bool enabled;
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u32 dirty_cnt;
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u32 top_idx;
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u8 dma_buff[BIS_CLUSTER_SIZE]; // Aligned to 8 bytes for DMA engine.
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cluster_cache_t clusters[];
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} bis_cache_t;
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static u8 ks_crypt = 0;
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static u8 ks_tweak = 0;
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static u32 emu_offset = 0;
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static emmc_part_t *system_part = NULL;
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static u32 *cache_lookup_tbl = (u32 *)NX_BIS_LOOKUP_ADDR;
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static bis_cache_t *bis_cache = (bis_cache_t *)NX_BIS_CACHE_ADDR;
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static int nx_emmc_bis_write_block(u32 sector, u32 count, void *buff, bool flush)
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{
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if (!system_part)
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return 3; // Not ready.
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int res;
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u8 tweak[SE_KEY_128_SIZE] __attribute__((aligned(4)));
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u32 cluster = sector / BIS_CLUSTER_SECTORS;
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u32 aligned_sector = cluster * BIS_CLUSTER_SECTORS;
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u32 sector_in_cluster = sector % BIS_CLUSTER_SECTORS;
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u32 lookup_idx = cache_lookup_tbl[cluster];
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bool is_cached = lookup_idx != (u32)BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY;
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// Write to cached cluster.
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if (is_cached)
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{
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if (buff)
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memcpy(bis_cache->clusters[lookup_idx].data + sector_in_cluster * EMMC_BLOCKSIZE, buff, count * EMMC_BLOCKSIZE);
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else
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buff = bis_cache->clusters[lookup_idx].data;
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if (!bis_cache->clusters[lookup_idx].dirty)
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bis_cache->dirty_cnt++;
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bis_cache->clusters[lookup_idx].dirty = true;
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if (!flush)
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return 0; // Success.
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// Reset args to trigger a full cluster flush to emmc.
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sector_in_cluster = 0;
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sector = aligned_sector;
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count = BIS_CLUSTER_SECTORS;
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}
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// Encrypt cluster.
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if (!se_aes_xts_crypt_sec_nx(ks_tweak, ks_crypt, ENCRYPT, cluster, tweak, true, sector_in_cluster, bis_cache->dma_buff, buff, count * EMMC_BLOCKSIZE))
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return 1; // Encryption error.
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// If not reading from cache, do a regular read and decrypt.
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if (!emu_offset)
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res = emmc_part_write(system_part, sector, count, bis_cache->dma_buff);
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else
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res = sdmmc_storage_write(&sd_storage, emu_offset + system_part->lba_start + sector, count, bis_cache->dma_buff);
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if (!res)
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return 1; // R/W error.
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// Mark cache entry not dirty if write succeeds.
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if (is_cached)
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{
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bis_cache->clusters[lookup_idx].dirty = false;
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bis_cache->dirty_cnt--;
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}
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return 0; // Success.
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}
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static void _nx_emmc_bis_cluster_cache_init(bool enable_cache)
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{
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u32 cache_lookup_tbl_size = (system_part->lba_end - system_part->lba_start + 1) / BIS_CLUSTER_SECTORS * sizeof(*cache_lookup_tbl);
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// Clear cache header.
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memset(bis_cache, 0, sizeof(bis_cache_t));
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// Clear cluster lookup table.
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memset(cache_lookup_tbl, BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY, cache_lookup_tbl_size);
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// Enable cache.
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bis_cache->enabled = enable_cache;
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}
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static void _nx_emmc_bis_flush_cache()
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{
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if (!bis_cache->enabled || !bis_cache->dirty_cnt)
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return;
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for (u32 i = 0; i < bis_cache->top_idx && bis_cache->dirty_cnt; i++)
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{
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if (bis_cache->clusters[i].dirty) {
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nx_emmc_bis_write_block(bis_cache->clusters[i].cluster_idx * BIS_CLUSTER_SECTORS, BIS_CLUSTER_SECTORS, NULL, true);
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bis_cache->dirty_cnt--;
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}
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}
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_nx_emmc_bis_cluster_cache_init(true);
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}
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static int nx_emmc_bis_read_block_normal(u32 sector, u32 count, void *buff)
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{
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static u32 prev_cluster = -1;
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static u32 prev_sector = 0;
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static u8 tweak[SE_KEY_128_SIZE] __attribute__((aligned(4)));
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int res;
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bool regen_tweak = true;
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u32 tweak_exp = 0;
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u32 cluster = sector / BIS_CLUSTER_SECTORS;
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u32 sector_in_cluster = sector % BIS_CLUSTER_SECTORS;
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// If not reading from cache, do a regular read and decrypt.
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if (!emu_offset)
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res = emmc_part_read(system_part, sector, count, bis_cache->dma_buff);
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else
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res = sdmmc_storage_read(&sd_storage, emu_offset + system_part->lba_start + sector, count, bis_cache->dma_buff);
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if (!res)
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return 1; // R/W error.
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if (prev_cluster != cluster) // Sector in different cluster than last read.
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{
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prev_cluster = cluster;
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tweak_exp = sector_in_cluster;
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}
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else if (sector > prev_sector) // Sector in same cluster and past last sector.
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{
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// Calculates the new tweak using the saved one, reducing expensive _gf256_mul_x_le calls.
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tweak_exp = sector - prev_sector - 1;
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regen_tweak = false;
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}
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else // Sector in same cluster and before or same as last sector.
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tweak_exp = sector_in_cluster;
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// Maximum one cluster (1 XTS crypto block 16KB).
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if (!se_aes_xts_crypt_sec_nx(ks_tweak, ks_crypt, DECRYPT, prev_cluster, tweak, regen_tweak, tweak_exp, buff, bis_cache->dma_buff, count * EMMC_BLOCKSIZE))
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return 1; // R/W error.
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prev_sector = sector + count - 1;
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return 0; // Success.
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}
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static int nx_emmc_bis_read_block_cached(u32 sector, u32 count, void *buff)
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{
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int res;
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u8 cache_tweak[SE_KEY_128_SIZE] __attribute__((aligned(4)));
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u32 cluster = sector / BIS_CLUSTER_SECTORS;
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u32 cluster_sector = cluster * BIS_CLUSTER_SECTORS;
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u32 sector_in_cluster = sector % BIS_CLUSTER_SECTORS;
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u32 lookup_idx = cache_lookup_tbl[cluster];
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// Read from cached cluster.
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if (lookup_idx != (u32)BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY)
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{
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memcpy(buff, bis_cache->clusters[lookup_idx].data + sector_in_cluster * EMMC_BLOCKSIZE, count * EMMC_BLOCKSIZE);
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return 0; // Success.
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}
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// Flush cache if full.
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if (bis_cache->top_idx >= BIS_CACHE_MAX_ENTRIES)
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_nx_emmc_bis_flush_cache();
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// Set new cached cluster parameters.
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bis_cache->clusters[bis_cache->top_idx].cluster_idx = cluster;
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bis_cache->clusters[bis_cache->top_idx].dirty = false;
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cache_lookup_tbl[cluster] = bis_cache->top_idx;
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// Read the whole cluster the sector resides in.
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if (!emu_offset)
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res = emmc_part_read(system_part, cluster_sector, BIS_CLUSTER_SECTORS, bis_cache->dma_buff);
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else
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res = sdmmc_storage_read(&sd_storage, emu_offset + system_part->lba_start + cluster_sector, BIS_CLUSTER_SECTORS, bis_cache->dma_buff);
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if (!res)
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return 1; // R/W error.
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// Decrypt cluster.
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if (!se_aes_xts_crypt_sec_nx(ks_tweak, ks_crypt, DECRYPT, cluster, cache_tweak, true, 0, bis_cache->dma_buff, bis_cache->dma_buff, BIS_CLUSTER_SIZE))
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return 1; // Decryption error.
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// Copy to cluster cache.
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memcpy(bis_cache->clusters[bis_cache->top_idx].data, bis_cache->dma_buff, BIS_CLUSTER_SIZE);
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memcpy(buff, bis_cache->dma_buff + sector_in_cluster * EMMC_BLOCKSIZE, count * EMMC_BLOCKSIZE);
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// Increment cache count.
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bis_cache->top_idx++;
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return 0; // Success.
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}
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static int nx_emmc_bis_read_block(u32 sector, u32 count, void *buff)
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{
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if (!system_part)
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return 3; // Not ready.
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if (bis_cache->enabled)
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return nx_emmc_bis_read_block_cached(sector, count, buff);
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else
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return nx_emmc_bis_read_block_normal(sector, count, buff);
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}
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int nx_emmc_bis_read(u32 sector, u32 count, void *buff)
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{
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u8 *buf = (u8 *)buff;
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u32 curr_sct = sector;
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while (count)
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{
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u32 sct_cnt = MIN(count, BIS_CLUSTER_SECTORS);
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if (nx_emmc_bis_read_block(curr_sct, sct_cnt, buf))
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return 0;
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count -= sct_cnt;
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curr_sct += sct_cnt;
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buf += sct_cnt * EMMC_BLOCKSIZE;
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}
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return 1;
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}
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int nx_emmc_bis_write(u32 sector, u32 count, void *buff)
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{
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u8 *buf = (u8 *)buff;
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u32 curr_sct = sector;
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while (count)
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{
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u32 sct_cnt = MIN(count, BIS_CLUSTER_SECTORS);
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if (nx_emmc_bis_write_block(curr_sct, sct_cnt, buf, false))
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return 0;
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count -= sct_cnt;
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curr_sct += sct_cnt;
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buf += sct_cnt * EMMC_BLOCKSIZE;
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}
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return 1;
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}
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void nx_emmc_bis_init(emmc_part_t *part, bool enable_cache, u32 emummc_offset)
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{
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system_part = part;
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emu_offset = emummc_offset;
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_nx_emmc_bis_cluster_cache_init(enable_cache);
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if (!strcmp(part->name, "PRODINFO") || !strcmp(part->name, "PRODINFOF"))
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{
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ks_crypt = 0;
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ks_tweak = 1;
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}
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else if (!strcmp(part->name, "SAFE"))
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{
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ks_crypt = 2;
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ks_tweak = 3;
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}
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else if (!strcmp(part->name, "SYSTEM") || !strcmp(part->name, "USER"))
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{
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ks_crypt = 4;
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ks_tweak = 5;
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}
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else
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system_part = NULL;
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}
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void nx_emmc_bis_end()
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{
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_nx_emmc_bis_flush_cache();
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system_part = NULL;
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}
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@ -1,230 +0,0 @@
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/*
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* Copyright (c) 2019 shchmue
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef NX_EMMC_BIS_H
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#define NX_EMMC_BIS_H
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#include <bdk.h>
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typedef struct _nx_emmc_cal0_spk_t
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{
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u16 unk0;
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u16 unk1;
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u16 eq_bw_lop;
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u16 eq_gn_lop;
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u16 eq_fc_bp1;
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u16 eq_bw_bp1;
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u16 eq_gn_bp1;
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u16 eq_fc_bp2;
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u16 eq_bw_bp2;
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u16 eq_gn_bp2;
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u16 eq_fc_bp3;
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u16 eq_bw_bp3;
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u16 eq_gn_bp3;
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u16 eq_fc_bp4;
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u16 eq_bw_bp4;
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u16 eq_gn_bp4;
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u16 eq_fc_hip1;
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u16 eq_gn_hip1;
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u16 eq_fc_hip2;
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u16 eq_bw_hip2;
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u16 eq_gn_hip2;
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u16 eq_pre_vol;
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u16 eq_pst_vol;
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u16 eq_ctrl2;
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u16 eq_ctrl1;
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u16 drc_agc_2;
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u16 drc_agc_3;
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u16 drc_agc_1;
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u16 spk_vol;
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u16 hp_vol;
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u16 dac1_min_vol_spk;
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u16 dac1_max_vol_spk;
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u16 dac1_min_vol_hp;
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u16 dac1_max_vol_hp;
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u16 in1_in2;
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u16 adc_vol_min;
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u16 adc_vol_max;
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u8 unk4[16];
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} __attribute__((packed)) nx_emmc_cal0_spk_t;
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typedef struct _nx_emmc_cal0_t
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{
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u32 magic; // 'CAL0'.
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u32 version;
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u32 body_size;
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u16 model;
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u16 update_cnt;
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u8 pad_crc16_0[0x10];
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u8 body_sha256[0x20];
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char cfg_id1[0x1E];
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u8 crc16_pad1[2];
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u8 rsvd0[0x20];
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u32 wlan_cc_num;
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u32 wlan_cc_last;
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char wlan_cc[128][3];
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u8 crc16_pad2[8];
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u8 wlan_mac[6];
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u8 crc16_pad3[2];
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u8 rsvd1[8];
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u8 bd_mac[6];
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u8 crc16_pad4[2];
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u8 rsvd2[8];
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u8 acc_offset[6];
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u8 crc16_pad5[2];
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u8 acc_scale[6];
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u8 crc16_pad6[2];
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u8 gyro_offset[6];
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u8 crc16_pad7[2];
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u8 gyro_scale[6];
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u8 crc16_pad8[2];
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char serial_number[0x18];
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u8 crc16_pad9[8];
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u8 ecc_p256_device_key[0x30];
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u8 crc16_pad10[0x10];
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u8 ecc_p256_device_cert[0x180];
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u8 crc16_pad11[0x10];
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u8 ecc_p233_device_key[0x30];
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u8 crc16_pad12[0x10];
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u8 ecc_p33_device_cert[0x180];
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u8 crc16_pad13[0x10];
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u8 ecc_p256_ticket_key[0x30];
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u8 crc16_pad14[0x10];
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u8 ecc_p256_ticket_cert[0x180];
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u8 crc16_pad15[0x10];
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u8 ecc_p233_ticket_key[0x30];
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u8 crc16_pad16[0x10];
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u8 ecc_p33_ticket_cert[0x180];
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u8 crc16_pad17[0x10];
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u8 ssl_key[0x110];
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u8 crc16_pad18[0x10];
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u32 ssl_cert_size;
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u8 crc16_pad19[0xC];
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u8 ssl_cert[0x800];
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u8 ssl_sha256[0x20];
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u8 random_number[0x1000];
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u8 random_number_sha256[0x20];
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u8 gc_key[0x110];
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u8 crc16_pad20[0x10];
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u8 gc_cert[0x400];
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u8 gc_cert_sha256[0x20];
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u8 rsa2048_eticket_key[0x220];
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u8 crc16_pad21[0x10];
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u8 rsa2048_eticket_cert[0x240];
|
||||
u8 crc16_pad22[0x10];
|
||||
|
||||
char battery_lot[0x1E];
|
||||
u8 crc16_pad23[2];
|
||||
nx_emmc_cal0_spk_t spk_cal;
|
||||
u8 spk_cal_rsvd[0x800 - sizeof(nx_emmc_cal0_spk_t)];
|
||||
u8 crc16_pad24[0x10];
|
||||
u32 region_code;
|
||||
u8 crc16_pad25[0xC];
|
||||
|
||||
u8 amiibo_key[0x50];
|
||||
u8 crc16_pad26[0x10];
|
||||
u8 amiibo_ecqv_cert[0x14];
|
||||
u8 crc16_pad27[0xC];
|
||||
u8 amiibo_ecqdsa_cert[0x70];
|
||||
u8 crc16_pad28[0x10];
|
||||
u8 amiibo_ecqv_bls_key[0x40];
|
||||
u8 crc16_pad29[0x10];
|
||||
u8 amiibo_ecqv_bls_cert[0x20];
|
||||
u8 crc16_pad30[0x10];
|
||||
u8 amiibo_ecqv_bls_root_cert[0x90];
|
||||
u8 crc16_pad31[0x10];
|
||||
|
||||
u32 product_model; // 1: Nx, 2: Copper, 4: Hoag.
|
||||
u8 crc16_pad32[0xC];
|
||||
u8 home_menu_scheme_main_color[6];
|
||||
u8 crc16_pad33[0xA];
|
||||
u32 lcd_bl_brightness_mapping[3]; // Floats. Normally 100%, 0% and 2%.
|
||||
u8 crc16_pad34[0x4];
|
||||
|
||||
u8 ext_ecc_b233_device_key[0x50];
|
||||
u8 crc16_pad35[0x10];
|
||||
u8 ext_ecc_p256_eticket_key[0x50];
|
||||
u8 crc16_pad36[0x10];
|
||||
u8 ext_ecc_b233_eticket_key[0x50];
|
||||
u8 crc16_pad37[0x10];
|
||||
u8 ext_ecc_rsa2048_eticket_key[0x240];
|
||||
u8 crc16_pad38[0x10];
|
||||
u8 ext_ssl_key[0x130];
|
||||
u8 crc16_pad39[0x10];
|
||||
u8 ext_gc_key[0x130];
|
||||
u8 crc16_pad40[0x10];
|
||||
|
||||
u32 lcd_vendor;
|
||||
u8 crc16_pad41[0xC];
|
||||
|
||||
// 5.0.0 and up.
|
||||
u8 ext_rsa2048_device_key[0x240];
|
||||
u8 crc16_pad42[0x10];
|
||||
u8 rsa2048_device_cert[0x240];
|
||||
u8 crc16_pad43[0x10];
|
||||
|
||||
u8 usbc_pwr_src_circuit_ver;
|
||||
u8 crc16_pad44[0xF];
|
||||
|
||||
// 9.0.0 and up.
|
||||
u32 home_menu_scheme_sub_color;
|
||||
u8 crc16_pad45[0xC];
|
||||
u32 home_menu_scheme_bezel_color;
|
||||
u8 crc16_pad46[0xC];
|
||||
u32 home_menu_scheme_main_color1;
|
||||
u8 crc16_pad47[0xC];
|
||||
u32 home_menu_scheme_main_color2;
|
||||
u8 crc16_pad48[0xC];
|
||||
u32 home_menu_scheme_main_color3;
|
||||
u8 crc16_pad49[0xC];
|
||||
|
||||
u8 analog_stick_type_l;
|
||||
u8 crc16_pad50[0xF];
|
||||
u8 analog_stick_param_l[0x12];
|
||||
u8 crc16_pad51[0xE];
|
||||
u8 analog_stick_cal_l[0x9];
|
||||
u8 crc16_pad52[0x7];
|
||||
u8 analog_stick_type_r;
|
||||
u8 crc16_pad53[0xF];
|
||||
u8 analog_stick_param_r[0x12];
|
||||
u8 crc16_pad54[0xE];
|
||||
u8 analog_stick_cal_r[0x9];
|
||||
u8 crc16_pad55[0x7];
|
||||
u8 console_6axis_sensor_type;
|
||||
u8 crc16_pad56[0xF];
|
||||
u8 console_6axis_sensor_hor_off[0x6];
|
||||
u8 crc16_pad57[0xA];
|
||||
|
||||
// 6.0.0 and up.
|
||||
u8 battery_ver;
|
||||
u8 crc16_pad58[0x1F];
|
||||
|
||||
// 9.0.0 and up.
|
||||
u32 home_menu_scheme_model;
|
||||
u8 crc16_pad59[0xC];
|
||||
|
||||
// 10.0.0 and up.
|
||||
u8 console_6axis_sensor_mount_type;
|
||||
} __attribute__((packed)) nx_emmc_cal0_t;
|
||||
|
||||
int nx_emmc_bis_read(u32 sector, u32 count, void *buff);
|
||||
int nx_emmc_bis_write(u32 sector, u32 count, void *buff);
|
||||
void nx_emmc_bis_init(emmc_part_t *part, bool enable_cache, u32 emummc_offset);
|
||||
void nx_emmc_bis_end();
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue