diff --git a/ipl/btn.c b/ipl/btn.c index 0b7b97d..7b3647e 100755 --- a/ipl/btn.c +++ b/ipl/btn.c @@ -60,14 +60,14 @@ u32 btn_wait() u32 btn_wait_timeout(u32 time_ms, u32 mask) { - u32 timeout = get_tmr_us() + (time_ms * 1000); + u32 timeout = get_tmr_ms() + time_ms; u32 res = btn_read() & mask; do { if (!(res & mask)) res = btn_read() & mask; - } while (get_tmr_us() < timeout); + } while (get_tmr_ms() < timeout); return res; } diff --git a/ipl/clock.c b/ipl/clock.c index aa6500c..08d712e 100755 --- a/ipl/clock.c +++ b/ipl/clock.c @@ -147,9 +147,9 @@ void clock_enable_kfuse() CLOCK(0x8) = (CLOCK(0x8) & 0xFFFFFEFF) | 0x100; CLOCK(0x14) &= 0xFFFFFEFF; CLOCK(0x14) = (CLOCK(0x14) & 0xFFFFFEFF) | 0x100; - sleep(10); + usleep(10); CLOCK(0x8) &= 0xFFFFFEFF; - sleep(20); + usleep(20); } void clock_disable_kfuse() @@ -436,7 +436,7 @@ void clock_sdmmc_enable(u32 id, u32 val) _clock_sdmmc_config_clock_source_inner(&div, id, val); _clock_sdmmc_set_enable(id); _clock_sdmmc_is_reset(id); - sleep((100000 + div - 1) / div); + usleep((100000 + div - 1) / div); _clock_sdmmc_clear_reset(id); _clock_sdmmc_is_reset(id); } diff --git a/ipl/cluster.c b/ipl/cluster.c index f88615e..b3e6542 100755 --- a/ipl/cluster.c +++ b/ipl/cluster.c @@ -44,7 +44,7 @@ int _cluster_pmc_enable_partition(u32 part, u32 toggle) u32 i = 5001; while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100) { - sleep(1); + usleep(1); i--; if (i < 1) return 0; @@ -57,7 +57,7 @@ int _cluster_pmc_enable_partition(u32 part, u32 toggle) { if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part) break; - sleep(1); + usleep(1); i--; } @@ -74,7 +74,7 @@ void cluster_boot_cpu0(u32 entry) if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) { CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; - sleep(2); + usleep(2); CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02; CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02; CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000; diff --git a/ipl/di.c b/ipl/di.c index 0422adb..99c7dd9 100755 --- a/ipl/di.c +++ b/ipl/di.c @@ -33,10 +33,10 @@ static u32 _display_ver = 0; static void _display_dsi_wait(u32 timeout, u32 off, u32 mask) { - u32 end = TMR(0x10) + timeout; - while (TMR(0x10) < end && DSI(off) & mask) + u32 end = get_tmr_us() + timeout; + while (get_tmr_us() < end && DSI(off) & mask) ; - sleep(5); + usleep(5); } void display_init() @@ -70,11 +70,11 @@ void display_init() gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE); //Backlight +-5V. gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); //Backlight +5V enable. - sleep(10000); + usleep(10000); gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); //Backlight -5V enable. - sleep(10000); + usleep(10000); gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO); //Backlight PWM, Enable, Reset. gpio_output_enable(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_OUTPUT_ENABLE); @@ -87,11 +87,11 @@ void display_init() exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94); exec_cfg((u32 *)DSI_BASE, _display_config_3, 60); - sleep(10000); + usleep(10000); gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_HIGH); //Backlight Reset enable. - sleep(60000); + usleep(60000); DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204; DSI(_DSIREG(DSI_WR_DATA)) = 0x337; @@ -105,7 +105,7 @@ void display_init() DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; _display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA); - sleep(5000); + usleep(5000); _display_ver = DSI(_DSIREG(DSI_RD_DATA)); if (_display_ver == 0x10) @@ -114,25 +114,25 @@ void display_init() DSI(_DSIREG(DSI_WR_DATA)) = 0x1105; DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; - sleep(180000); + usleep(180000); DSI(_DSIREG(DSI_WR_DATA)) = 0x2905; DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; - sleep(20000); + usleep(20000); exec_cfg((u32 *)DSI_BASE, _display_config_5, 21); exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3); DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; exec_cfg((u32 *)DSI_BASE, _display_config_7, 10); - sleep(10000); + usleep(10000); exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6); exec_cfg((u32 *)DSI_BASE, _display_config_9, 4); exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16); - sleep(10000); + usleep(10000); exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113); } @@ -161,7 +161,7 @@ void display_end() exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17); exec_cfg((u32 *)DSI_BASE, _display_config_13, 16); - sleep(10000); + usleep(10000); if (_display_ver == 0x10) exec_cfg((u32 *)DSI_BASE, _display_config_14, 22); @@ -169,19 +169,19 @@ void display_end() DSI(_DSIREG(DSI_WR_DATA)) = 0x1005; DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; - sleep(50000); + usleep(50000); //gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); //Backlight Reset disable. - //sleep(10000); + //usleep(10000); //gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); //Backlight -5V disable. - //sleep(10000); + //usleep(10000); //gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); //Backlight +5V disable. - //sleep(10000); + //usleep(10000); //Disable clocks. CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x1010000; @@ -209,7 +209,7 @@ void display_color_screen(u32 color) DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ; - sleep(35000); + usleep(35000); display_backlight(1); } @@ -221,7 +221,7 @@ u32 *display_init_framebuffer() //This configures the framebuffer @ 0xC0000000 with a resolution of 1280x720 (line stride 768). exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer, 32); - sleep(35000); + usleep(35000); //Enable backlight //display_backlight(1); diff --git a/ipl/hos.c b/ipl/hos.c index a8d2410..48b39f2 100755 --- a/ipl/hos.c +++ b/ipl/hos.c @@ -597,7 +597,7 @@ int hos_launch(ini_sec_t *cfg) //Wait for secmon to get ready. cluster_boot_cpu0(ctxt.pkg1_id->secmon_base); while (!*mb_out) - sleep(1); + usleep(1); //TODO: pkg1.1 locks PMC scratches, we can do that too at some point. /*PMC(0x4) = 0x7FFFF3; diff --git a/ipl/i2c.c b/ipl/i2c.c index 6d6c1c2..6aee644 100755 --- a/ipl/i2c.c +++ b/ipl/i2c.c @@ -26,7 +26,7 @@ static void _i2c_wait(vu32 *base) base[0x23] = 0x25; for (u32 i = 0; i < 20; i++) { - sleep(1); + usleep(1); if (!(base[0x23] & 1)) break; } @@ -89,7 +89,7 @@ void i2c_init(u32 idx) for (u32 i = 0; i < 10; i++) { - sleep(20000); + usleep(20000); if (base[0x1A] & 0x800) break; } diff --git a/ipl/main.c b/ipl/main.c index 6b12a86..f18d189 100755 --- a/ipl/main.c +++ b/ipl/main.c @@ -233,7 +233,7 @@ void mbist_workaround() CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40; CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000; CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; - sleep(2); + usleep(2); I2S(0x0A0) |= 0x400; I2S(0x088) &= 0xFFFFFFFE; @@ -247,7 +247,7 @@ void mbist_workaround() I2S(0x488) &= 0xFFFFFFFE; DISPLAY_A(0xCF8) |= 4; VIC(0x8C) = 0xFFFFFFFF; - sleep(2); + usleep(2); CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = 0x40; CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000; @@ -691,7 +691,7 @@ void reboot_rcm() PMC(APBDEV_PMC_SCRATCH0) = 2; // Reboot into rcm. PMC(0) |= 0x10; while (1) - sleep(1); + usleep(1); } void power_off() @@ -1028,7 +1028,7 @@ int dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part) EPRINTFARGS("Error reading %d blocks @ LBA %08X,\nfrom eMMC (try %d), retrying...", num, lba_curr, ++retryCount); - sleep(150000); + msleep(150); if (retryCount >= 3) { gfx_con.fntsz = 16; @@ -1305,7 +1305,7 @@ int restore_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part EPRINTFARGS("Error writing %d blocks @ LBA %08X\nto eMMC (try %d), retrying...", num, lba_curr, ++retryCount); - sleep(150000); + msleep(150); if (retryCount >= 3) { gfx_con.fntsz = 16; @@ -1376,7 +1376,7 @@ static void restore_emmc_selected(emmcPartType_t restoreType) { gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy); gfx_printf(&gfx_con, "%kWait... (%ds) %k", 0xFF888888, value, 0xFFCCCCCC); - sleep(1000000); + msleep(1000); value--; } gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy); @@ -1645,7 +1645,7 @@ void launch_firmware() if (!cfg_sec) { gfx_printf(&gfx_con, "\nUsing default launch configuration...\n"); - sleep(3000000); + msleep(3000); } #ifdef MENU_LOGO_ENABLE free(Kc_MENU_LOGO); @@ -2118,7 +2118,7 @@ void print_battery_info() for (int i = 0; i < 0x200; i += 2) { i2c_recv_buf_small(buf + i, 2, I2C_1, 0x36, i >> 1); - sleep(2500); + usleep(2500); } gfx_hexdump(&gfx_con, 0, (u8 *)buf, 0x200); @@ -2174,7 +2174,7 @@ void print_battery_info() if (btn & BTN_POWER) { max17050_fix_configuration(); - sleep(1000000); + msleep(1000); gfx_con_getpos(&gfx_con, &gfx_con.savedx, &gfx_con.savedy); u16 value = 0; gfx_printf(&gfx_con, "%kThe console will power off in 45 seconds.\n%k", 0xFFFFDD00, 0xFFCCCCCC); @@ -2182,10 +2182,10 @@ void print_battery_info() { gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy); gfx_printf(&gfx_con, "%2ds elapsed", value); - sleep(1000000); + msleep(1000); value++; } - sleep(2000000); + msleep(2000); power_off(); } @@ -2195,7 +2195,7 @@ void print_battery_info() else EPRINTF("You need a fully charged battery\nand connected to a wall adapter,\nto apply this fix!"); - sleep(500000); + msleep(500); btn_wait(); } */ @@ -2224,7 +2224,7 @@ void print_battery_info() { gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy); gfx_printf(&gfx_con, "%kWait... (%ds) %k", 0xFF888888, value, 0xFFCCCCCC); - sleep(1000000); + msleep(1000); value--; } gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy); @@ -2242,7 +2242,7 @@ void print_battery_info() "2. Press POWER for 15s.\n" "3. Reconnect the USB to power-on!%k\n", 0xFFFFDD00, 0xFFCCCCCC); } - sleep(500000); + msleep(500); btn_wait(); } }*/ diff --git a/ipl/max17050.c b/ipl/max17050.c index c2e3f3c..47c532f 100644 --- a/ipl/max17050.c +++ b/ipl/max17050.c @@ -236,7 +236,7 @@ int max17050_fix_configuration() /* After Power up, the MAX17050 requires 500ms in order * to perform signal debouncing and initial SOC reporting */ - sleep(500000); + msleep(500); /* Initialize configaration */ _max17050_write_config_regs(); @@ -248,7 +248,7 @@ int max17050_fix_configuration() /* delay must be atleast 350mS to allow VFSOC * to be calculated from the new configuration */ - sleep(350000); + msleep(350); /* reset vfsoc0 reg */ _max17050_reset_vfsoc0_reg(); diff --git a/ipl/max7762x.c b/ipl/max7762x.c index 8d139cd..b889f2c 100755 --- a/ipl/max7762x.c +++ b/ipl/max7762x.c @@ -103,7 +103,7 @@ int max77620_regulator_set_voltage(u32 id, u32 mv) u8 val = i2c_recv_byte(I2C_5, 0x3C, reg->volt_addr); val = (val & ~reg->volt_mask) | (mult & reg->volt_mask); i2c_send_byte(I2C_5, 0x3C, reg->volt_addr, val); - sleep(1000); + usleep(1000); return 1; } @@ -122,7 +122,7 @@ int max77620_regulator_enable(u32 id, int enable) else val &= ~reg->enable_mask; i2c_send_byte(I2C_5, 0x3C, addr, val); - sleep(1000); + usleep(1000); return 1; } diff --git a/ipl/mc.c b/ipl/mc.c index 7841abd..eae6622 100755 --- a/ipl/mc.c +++ b/ipl/mc.c @@ -127,7 +127,7 @@ void mc_enable() //Enable EMC DLL clock. CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF) | 0x4000; CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x2000001; //Clear EMC and MC reset. - sleep(5); + usleep(5); //#ifdef CONFIG_ENABLE_AHB_REDIRECT mc_disable_ahb_redirect(); diff --git a/ipl/sdmmc.c b/ipl/sdmmc.c index 5956402..8e9547d 100755 --- a/ipl/sdmmc.c +++ b/ipl/sdmmc.c @@ -175,7 +175,7 @@ static int _sdmmc_storage_readwrite(sdmmc_storage_t *storage, u32 sector, u32 nu else retries--; - sleep(100000); + msleep(100); } while (retries); return 0; @@ -228,7 +228,7 @@ static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *pout, u static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power) { - u32 timeout = get_tmr_us() + 1500000; + u32 timeout = get_tmr_ms() + 1500; while (1) { @@ -241,9 +241,9 @@ static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power) storage->has_sector_access = 1; return 1; } - if (get_tmr_us() > timeout) + if (get_tmr_ms() > timeout) break; - sleep(1000); + usleep(1000); } return 0; @@ -465,7 +465,7 @@ int sdmmc_storage_init_mmc(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32 return 0; DPRINTF("[MMC] after init\n"); - sleep(1000 + (74000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep(1000 + (74000 + sdmmc->divisor - 1) / sdmmc->divisor); if (!_sdmmc_storage_go_idle_state(storage)) return 0; @@ -605,7 +605,7 @@ static int _sd_storage_get_op_cond_once(sdmmc_storage_t *storage, u32 *cond, int static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, int is_version_1, int supports_low_voltage) { - u32 timeout = get_tmr_us() + 1500000; + u32 timeout = get_tmr_ms() + 1500; while (1) { @@ -633,9 +633,9 @@ static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, int is_version_1, i return 1; } - if (get_tmr_us() > timeout) + if (get_tmr_ms() > timeout) break; - sleep(10000); // Needs to be at least 10ms for some SD Cards + msleep(10); // Needs to be at least 10ms for some SD Cards } return 0; @@ -646,7 +646,7 @@ static int _sd_storage_get_rca(sdmmc_storage_t *storage) sdmmc_cmd_t cmdbuf; sdmmc_init_cmd(&cmdbuf, SD_SEND_RELATIVE_ADDR, 0, SDMMC_RSP_TYPE_4, 0); - u32 timeout = get_tmr_us() + 1500000; + u32 timeout = get_tmr_ms() + 1500; while (1) { @@ -663,9 +663,9 @@ static int _sd_storage_get_rca(sdmmc_storage_t *storage) return 1; } - if (get_tmr_us() > timeout) + if (get_tmr_ms() > timeout) break; - sleep(1000); + usleep(1000); } return 0; @@ -1019,7 +1019,7 @@ int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32 return 0; DPRINTF("[SD] after init\n"); - sleep(1000 + (74000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep(1000 + (74000 + sdmmc->divisor - 1) / sdmmc->divisor); if (!_sdmmc_storage_go_idle_state(storage)) return 0; @@ -1172,7 +1172,7 @@ int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc) return 0; DPRINTF("[gc] after init\n"); - sleep(1000 + (10000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep(1000 + (10000 + sdmmc->divisor - 1) / sdmmc->divisor); if (!sdmmc_config_tuning(storage->sdmmc, 14, MMC_SEND_TUNING_BLOCK_HS200)) return 0; diff --git a/ipl/sdmmc_driver.c b/ipl/sdmmc_driver.c index 409e387..7e9632d 100755 --- a/ipl/sdmmc_driver.c +++ b/ipl/sdmmc_driver.c @@ -161,20 +161,20 @@ static int _sdmmc_wait_type4(sdmmc_t *sdmmc) sdmmc->regs->field_1B0 |= 0x80000000; _sdmmc_get_clkcon(sdmmc); - u32 timeout = get_tmr_us() + 5000; + u32 timeout = get_tmr_ms() + 5; while (sdmmc->regs->field_1B0 & 0x80000000) { - if (get_tmr_us() > timeout) + if (get_tmr_ms() > timeout) { res = 0; goto out; } } - timeout = get_tmr_us() + 10000; + timeout = get_tmr_ms() + 10; while (sdmmc->regs->field_1BC & 0x80000000) { - if (get_tmr_us() > timeout) + if (get_tmr_ms() > timeout) { res = 0; goto out; @@ -376,8 +376,8 @@ static void _sdmmc_reset(sdmmc_t *sdmmc) sdmmc->regs->swrst |= TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE | TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE; _sdmmc_get_clkcon(sdmmc); - u32 timeout = get_tmr_us() + 2000000; - while (sdmmc->regs->swrst << 29 >> 30 && get_tmr_us() < timeout) + u32 timeout = get_tmr_ms() + 2000; + while (sdmmc->regs->swrst << 29 >> 30 && get_tmr_ms() < timeout) ; } @@ -385,9 +385,9 @@ static int _sdmmc_wait_prnsts_type0(sdmmc_t *sdmmc, u32 wait_dat) { _sdmmc_get_clkcon(sdmmc); - u32 timeout = get_tmr_us() + 2000000; + u32 timeout = get_tmr_ms() + 2000; while(sdmmc->regs->prnsts & 1) //CMD inhibit. - if (get_tmr_us() > timeout) + if (get_tmr_ms() > timeout) { _sdmmc_reset(sdmmc); return 0; @@ -395,9 +395,9 @@ static int _sdmmc_wait_prnsts_type0(sdmmc_t *sdmmc, u32 wait_dat) if (wait_dat) { - timeout = get_tmr_us() + 2000000; + timeout = get_tmr_ms() + 2000; while (sdmmc->regs->prnsts & 2) //DAT inhibit. - if (get_tmr_us() > timeout) + if (get_tmr_ms() > timeout) { _sdmmc_reset(sdmmc); return 0; @@ -411,9 +411,9 @@ static int _sdmmc_wait_prnsts_type1(sdmmc_t *sdmmc) { _sdmmc_get_clkcon(sdmmc); - u32 timeout = get_tmr_us() + 2000000; + u32 timeout = get_tmr_ms() + 2000; while (!(sdmmc->regs->prnsts & 0x100000)) //DAT0 line level. - if (get_tmr_us() > timeout) + if (get_tmr_ms() > timeout) { _sdmmc_reset(sdmmc); return 0; @@ -504,7 +504,7 @@ static int _sdmmc_config_tuning_once(sdmmc_t *sdmmc, u32 cmd) sdmmc->regs->clkcon &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; _sdmmc_parse_cmd_48(sdmmc, cmd); _sdmmc_get_clkcon(sdmmc); - sleep(1); + usleep(1); _sdmmc_reset(sdmmc); sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; _sdmmc_get_clkcon(sdmmc); @@ -517,14 +517,14 @@ static int _sdmmc_config_tuning_once(sdmmc_t *sdmmc, u32 cmd) sdmmc->regs->norintsts = 0x20; sdmmc->regs->norintstsen &= 0xFFDF; _sdmmc_get_clkcon(sdmmc); - sleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor); return 1; } } _sdmmc_reset(sdmmc); sdmmc->regs->norintstsen &= 0xFFDF; _sdmmc_get_clkcon(sdmmc); - sleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor); return 0; } @@ -573,10 +573,10 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc) //Enable internal clock and wait till it is stable. sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE; _sdmmc_get_clkcon(sdmmc); - u32 timeout = get_tmr_us() + 2000000; + u32 timeout = get_tmr_ms() + 2000; while (!(sdmmc->regs->clkcon & TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { - if (get_tmr_us() > timeout) + if (get_tmr_ms() > timeout) return 0; } @@ -642,17 +642,17 @@ static void _sdmmc_autocal_execute(sdmmc_t *sdmmc, u32 power) { sdmmc->regs->sdmemcmppadctl |= 0x80000000; _sdmmc_get_clkcon(sdmmc); - sleep(1); + usleep(1); } sdmmc->regs->autocalcfg |= 0xA0000000; _sdmmc_get_clkcon(sdmmc); - sleep(1); + usleep(1); - u32 timeout = get_tmr_us() + 10000; + u32 timeout = get_tmr_ms() + 10; while (sdmmc->regs->autocalcfg & 0x80000000) { - if (get_tmr_us() > timeout) + if (get_tmr_ms() > timeout) { //In case autocalibration fails, we load suggested standard values. _sdmmc_pad_config_fallback(sdmmc, power); @@ -710,13 +710,13 @@ static int _sdmmc_wait_request(sdmmc_t *sdmmc) { _sdmmc_get_clkcon(sdmmc); - u32 timeout = get_tmr_us() + 2000000; + u32 timeout = get_tmr_ms() + 2000; while (1) { int res = _sdmmc_check_mask_interrupt(sdmmc, 0, TEGRA_MMC_NORINTSTS_CMD_COMPLETE); if (res == SDMMC_MASKINT_MASKED) break; - if (res != SDMMC_MASKINT_NOERROR || get_tmr_us() > timeout) + if (res != SDMMC_MASKINT_NOERROR || get_tmr_ms() > timeout) { _sdmmc_reset(sdmmc); return 0; @@ -760,11 +760,11 @@ int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp) should_disable_sd_clock = 1; sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; _sdmmc_get_clkcon(sdmmc); - sleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); } int res = _sdmmc_stop_transmission_inner(sdmmc, rsp); - sleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); if (should_disable_sd_clock) sdmmc->regs->clkcon &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; @@ -817,7 +817,7 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc) do { blkcnt = sdmmc->regs->blkcnt; - u32 timeout = get_tmr_us() + 1500000; + u32 timeout = get_tmr_ms() + 1500; do { int res = 0; @@ -843,7 +843,7 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc) _sdmmc_reset(sdmmc); return 0; } - } while (get_tmr_us() < timeout); + } while (get_tmr_ms() < timeout); } while (sdmmc->regs->blkcnt != blkcnt); _sdmmc_reset(sdmmc); @@ -912,7 +912,7 @@ static int _sdmmc_config_sdmmc1() APB_MISC(APB_MISC_GP_VGPIO_GPIO_MUX_SEL) = 0; gpio_config(GPIO_PORT_Z, GPIO_PIN_1, GPIO_MODE_GPIO); gpio_output_enable(GPIO_PORT_Z, GPIO_PIN_1, GPIO_OUTPUT_DISABLE); - sleep(100); + usleep(100); if(!!gpio_read(GPIO_PORT_Z, GPIO_PIN_1)) return 0; @@ -945,18 +945,18 @@ static int _sdmmc_config_sdmmc1() gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_HIGH); gpio_output_enable(GPIO_PORT_E, GPIO_PIN_4, GPIO_OUTPUT_ENABLE); - sleep(1000); + usleep(1000); //Enable SD card power. max77620_regulator_set_voltage(REGULATOR_LDO2, 3300000); max77620_regulator_enable(REGULATOR_LDO2, 1); - sleep(1000); + usleep(1000); //For good measure. APB_MISC(APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL) = 0x10000000; - sleep(1000); + usleep(1000); return 1; } @@ -1026,7 +1026,7 @@ void sdmmc_end(sdmmc_t *sdmmc) if (sdmmc->id == SDMMC_1) { gpio_output_enable(GPIO_PORT_E, GPIO_PIN_4, GPIO_OUTPUT_DISABLE); - sleep(1000); // To power cycle min 1ms without power is needed. + msleep(1); // To power cycle min 1ms without power is needed. } _sdmmc_get_clkcon(sdmmc); @@ -1058,11 +1058,11 @@ int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *b should_disable_sd_clock = 1; sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; _sdmmc_get_clkcon(sdmmc); - sleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); } int res = _sdmmc_execute_cmd_inner(sdmmc, cmd, req, blkcnt_out); - sleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); if (should_disable_sd_clock) sdmmc->regs->clkcon &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; @@ -1086,13 +1086,13 @@ int sdmmc_enable_low_voltage(sdmmc_t *sdmmc) _sdmmc_autocal_execute(sdmmc, SDMMC_POWER_1_8); _sdmmc_set_voltage(sdmmc, SDMMC_POWER_1_8); _sdmmc_get_clkcon(sdmmc); - sleep(5000); + msleep(5); if (sdmmc->regs->hostctl2 & SDHCI_CTRL_VDD_180) { sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; _sdmmc_get_clkcon(sdmmc); - sleep(1000u); + msleep(1); if ((sdmmc->regs->prnsts & 0xF00000) == 0xF00000) return 1; } diff --git a/ipl/sdram.c b/ipl/sdram.c index c4fa701..ab0b95d 100755 --- a/ipl/sdram.c +++ b/ipl/sdram.c @@ -42,27 +42,27 @@ static u32 _get_sdram_id() static void _sdram_config(const sdram_params_t *params) { PMC(0x45C) = (((4 * params->emc_pmc_scratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF; - sleep(params->pmc_io_dpd3_req_wait); + usleep(params->pmc_io_dpd3_req_wait); u32 req = (4 * params->emc_pmc_scratch2 >> 2) + 0x80000000; PMC(APBDEV_PMC_IO_DPD4_REQ) = (req >> 16 << 16) ^ 0x3FFF0000; - sleep(params->pmc_io_dpd4_req_wait); + usleep(params->pmc_io_dpd4_req_wait); PMC(APBDEV_PMC_IO_DPD4_REQ) = (req ^ 0xFFFF) & 0xC000FFFF; - sleep(params->pmc_io_dpd4_req_wait); + usleep(params->pmc_io_dpd4_req_wait); PMC(APBDEV_PMC_WEAK_BIAS) = 0; - sleep(1); + usleep(1); CLOCK(CLK_RST_CONTROLLER_PLLM_MISC1) = params->pllm_setup_control; CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = 0; CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20); - u32 wait_end = TMR(0x10) + 300; + u32 wait_end = get_tmr_us() + 300; while (!(CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) & 0x8000000)) { - if (TMR(0x10) >= wait_end) + if (get_tmr_us() >= wait_end) goto break_nosleep; } - sleep(10); + usleep(10); break_nosleep: CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = ((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF); @@ -77,7 +77,7 @@ break_nosleep: EMC(EMC_PMACRO_VTTGEN_CTRL_1) = params->emc_pmacro_vttgen_ctrl1; EMC(EMC_PMACRO_VTTGEN_CTRL_2) = params->emc_pmacro_vttgen_ctrl2; EMC(EMC_TIMING_CONTROL) = 1; - sleep(1); + usleep(1); EMC(EMC_DBG) = (params->emc_dbg_write_mux << 1) | params->emc_dbg; if (params->emc_bct_spare2) *(vu32 *)params->emc_bct_spare2 = params->emc_bct_spare3; @@ -298,7 +298,7 @@ break_nosleep: EMC(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1; EMC(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval; EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; - sleep(params->emc_auto_cal_wait); + usleep(params->emc_auto_cal_wait); if (params->emc_bct_spare8) *(vu32 *)params->emc_bct_spare8 = params->emc_bct_spare9; EMC(EMC_CFG_2) = params->emc_cfg2; @@ -394,7 +394,7 @@ break_nosleep: MC(MC_TIMING_CONTROL) = 1; } PMC(0x45C) = ((4 * params->emc_pmc_scratch1 >> 2) + 0x40000000) & 0xCFFF0000; - sleep(params->pmc_io_dpd3_req_wait); + usleep(params->pmc_io_dpd3_req_wait); if (!params->emc_auto_cal_interval) EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config | 0x200; EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2; @@ -409,29 +409,29 @@ break_nosleep: } } EMC(EMC_TIMING_CONTROL) = 1; - sleep(params->emc_timing_control_wait); + usleep(params->emc_timing_control_wait); PMC(0x4E4) &= 0xFFF8007F; - sleep(params->pmc_ddr_ctrl_wait); + usleep(params->pmc_ddr_ctrl_wait); if (params->memory_type == 2) { EMC(EMC_PIN) = (params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12); - sleep(params->emc_pin_extra_wait + 200); + usleep(params->emc_pin_extra_wait + 200); EMC(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256; - sleep(params->emc_pin_extra_wait + 500); + usleep(params->emc_pin_extra_wait + 500); } if (params->memory_type == 3) { EMC(EMC_PIN) = (params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12); - sleep(params->emc_pin_extra_wait + 200); + usleep(params->emc_pin_extra_wait + 200); EMC(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256; - sleep(params->emc_pin_extra_wait + 2000); + usleep(params->emc_pin_extra_wait + 2000); } EMC(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 0x101; - sleep(params->emc_pin_program_wait); + usleep(params->emc_pin_program_wait); if (params->memory_type != 3) EMC(EMC_NOP) = (params->emc_dev_select << 30) + 1; if (params->memory_type == 1) - sleep(params->emc_pin_extra_wait + 200); + usleep(params->emc_pin_extra_wait + 200); if (params->memory_type == 3) { if (params->emc_bct_spare10) @@ -449,12 +449,12 @@ break_nosleep: if (params->emc_zcal_warm_cold_boot_enables & 1) { EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0; - sleep(params->emc_zcal_init_wait); + usleep(params->emc_zcal_init_wait); EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0 ^ 3; if (!(params->emc_dev_select & 2)) { EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1; - sleep(params->emc_zcal_init_wait); + usleep(params->emc_zcal_init_wait); EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1 ^ 3; } } @@ -511,7 +511,7 @@ void sdram_init() i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_SD1, 40); //40 = (1000 * 1100 - 600000) / 12500 -> 1.1V PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel; - sleep(params->pmc_vddp_sel_wait); + usleep(params->pmc_vddp_sel_wait); PMC(APBDEV_PMC_DDR_PWR) = PMC(APBDEV_PMC_DDR_PWR); PMC(APBDEV_PMC_NO_IOPOWER) = params->pmc_no_io_power; PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short; diff --git a/ipl/tsec.c b/ipl/tsec.c index 612a38a..de567ed 100755 --- a/ipl/tsec.c +++ b/ipl/tsec.c @@ -19,13 +19,14 @@ #include "clock.h" #include "t210.h" #include "heap.h" +#include "util.h" static int _tsec_dma_wait_idle() { - u32 timeout = TMR(0x10) + 10000000; + u32 timeout = get_tmr_ms() + 10000; while (!(TSEC(0x1118) & 2)) - if (TMR(0x10) > timeout) + if (get_tmr_ms() > timeout) return 0; return 1; @@ -93,9 +94,9 @@ int tsec_query(u8 *dst, u32 rev, void *fw) res = -3; goto out_free; } - u32 timeout = TMR(0x10) + 2000000; + u32 timeout = get_tmr_ms() + 2000; while (!TSEC(0x1044)) - if (TMR(0x10) > timeout) + if (get_tmr_ms() > timeout) { res = -4; goto out_free; diff --git a/ipl/uart.c b/ipl/uart.c index 2696cf5..9689ec3 100755 --- a/ipl/uart.c +++ b/ipl/uart.c @@ -36,7 +36,7 @@ void uart_init(u32 idx, u32 baud) uart->UART_IER_DLAB = 0; uart->UART_IIR_FCR = 7; //Enable and clear TX and RX FIFOs. (void)uart->UART_LSR; - sleep(3 * ((baud + 999999) / baud)); + usleep(3 * ((baud + 999999) / baud)); uart->UART_LCR = 3; //Set word length 8. uart->UART_MCR = 0; uart->UART_MSR = 0; diff --git a/ipl/util.c b/ipl/util.c index 776f142..5913656 100755 --- a/ipl/util.c +++ b/ipl/util.c @@ -20,7 +20,14 @@ u32 get_tmr_s() { - return RTC(0x8); //APBDEV_RTC_SECONDS + return RTC(0x8); //RTC_SECONDS +} + +u32 get_tmr_ms() +{ + // The registers must be read with the following order: + // -> RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0x8) + return (RTC(0x10) | (RTC(0xC)<< 10)); } u32 get_tmr_us() @@ -28,10 +35,17 @@ u32 get_tmr_us() return TMR(0x10); //TMRUS } -void sleep(u32 ticks) +void msleep(u32 milliseconds) { - u32 start = TMR(0x10); - while (TMR(0x10) - start <= ticks) + u32 start = get_tmr_ms(); + while ((get_tmr_ms() - start) <= milliseconds) + ; +} + +void usleep(u32 microseconds) +{ + u32 start = get_tmr_us(); + while ((get_tmr_us() - start) <= microseconds) ; } diff --git a/ipl/util.h b/ipl/util.h index 83dd1bb..e86a048 100755 --- a/ipl/util.h +++ b/ipl/util.h @@ -30,8 +30,10 @@ typedef struct _cfg_op_t } cfg_op_t; u32 get_tmr_us(); +u32 get_tmr_ms(); u32 get_tmr_s(); -void sleep(u32 ticks); +void usleep(u32 ticks); +void msleep(u32 milliseconds); void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops); u32 crc32c(const void *buf, u32 len);