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hekate/nyx: stylistic corrections

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CTCaer 2023-02-11 23:51:43 +02:00
parent 9a98c1afb9
commit 5193416658
11 changed files with 53 additions and 51 deletions
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2
bootloader/hos/hos.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018 st4rk
* Copyright (c) 2018 Ced2911
* Copyright (c) 2018-2022 CTCaer
* Copyright (c) 2018-2023 CTCaer
* Copyright (c) 2018 balika011
*
* This program is free software; you can redistribute it and/or modify it

2
bootloader/hos/pkg2.h
View file

@ -26,6 +26,8 @@
#define PKG2_SEC_INI1 1
#define INI1_MAGIC 0x31494E49
//! TODO: Update on kernel change if needed.
#define PKG2_NEWKERN_GET_INI1_HEURISTIC 0xD2800015 // Offset of OP + 12 is the INI1 offset.
#define PKG2_NEWKERN_START 0x800

2
bootloader/l4t/l4t.c
View file

@ -1,7 +1,7 @@
/*
* L4T Loader for Tegra X1
*
* Copyright (c) 2020-2022 CTCaer
* Copyright (c) 2020-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,

24
bootloader/main.c
View file

@ -1,7 +1,7 @@
/*
* Copyright (c) 2018 naehrwert
*
* Copyright (c) 2018-2022 CTCaer
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@ -144,7 +144,7 @@ static void _reloc_patcher(u32 payload_dst, u32 payload_src, u32 payload_size)
if (payload_size == 0x7000)
{
memcpy((u8 *)(payload_src + ALIGN(PATCHED_RELOC_SZ, 0x10)), coreboot_addr, 0x7000); //Bootblock
memcpy((u8 *)(payload_src + ALIGN(PATCHED_RELOC_SZ, 0x10)), coreboot_addr, 0x7000); // Bootblock.
*(vu32 *)CBFS_DRAM_EN_ADDR = CBFS_DRAM_MAGIC;
}
}
@ -311,6 +311,7 @@ static void _launch_payloads()
// Build configuration menu.
ments[0].type = MENT_BACK;
ments[0].caption = "Back";
ments[1].type = MENT_CHGLINE;
while (true)
@ -389,14 +390,15 @@ static void _launch_ini_list()
ment_t *ments = (ment_t *)malloc(sizeof(ment_t) * (max_entries + 3));
ments[0].type = MENT_BACK;
ments[0].caption = "Back";
ments[1].type = MENT_CHGLINE;
u32 sec_idx = 2;
LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_list_sections, link)
{
if (!strcmp(ini_sec->name, "config") ||
ini_sec->type == INI_COMMENT ||
ini_sec->type == INI_NEWLINE)
if (ini_sec->type == INI_COMMENT ||
ini_sec->type == INI_NEWLINE ||
!strcmp(ini_sec->name, "config"))
continue;
ments[sec_idx].type = ini_sec->type;
@ -517,6 +519,7 @@ static void _launch_config()
ment_t *ments = (ment_t *)malloc(sizeof(ment_t) * (max_entries + 6));
ments[0].type = MENT_BACK;
ments[0].caption = "Back";
ments[1].type = MENT_CHGLINE;
ments[2].type = MENT_HANDLER;
@ -532,9 +535,9 @@ static void _launch_config()
u32 sec_idx = 5;
LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link)
{
if (!strcmp(ini_sec->name, "config") ||
ini_sec->type == INI_COMMENT ||
ini_sec->type == INI_NEWLINE)
if (ini_sec->type == INI_COMMENT ||
ini_sec->type == INI_NEWLINE ||
!strcmp(ini_sec->name, "config"))
continue;
ments[sec_idx].type = ini_sec->type;
@ -693,15 +696,14 @@ static void _nyx_load_run()
reloc_meta_t *reloc = (reloc_meta_t *)(IPL_LOAD_ADDR + RELOC_META_OFF);
memcpy((u8 *)nyx_str->hekate, (u8 *)reloc->start, reloc->end - reloc->start);
void (*nyx_ptr)() = (void *)nyx;
bpmp_mmu_disable();
bpmp_clk_rate_set(BPMP_CLK_NORMAL);
minerva_periodic_training();
// Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms.
// Some cards (Sandisk U1), do not like a fast power cycle.
sdmmc_storage_init_wait_sd();
void (*nyx_ptr)() = (void *)nyx;
(*nyx_ptr)();
}

12
nyx/nyx_gui/nyx.c
View file

@ -30,10 +30,6 @@
#include "frontend/fe_emmc_tools.h"
#include "frontend/gui.h"
#ifdef MENU_LOGO_ENABLE
u8 *Kc_MENU_LOGO;
#endif //MENU_LOGO_ENABLE
nyx_config n_cfg;
hekate_config h_cfg;
@ -121,7 +117,7 @@ void reloc_patcher(u32 payload_dst, u32 payload_src, u32 payload_size)
if (payload_size == 0x7000)
{
memcpy((u8 *)(payload_src + ALIGN(PATCHED_RELOC_SZ, 0x10)), coreboot_addr, 0x7000); //Bootblock
memcpy((u8 *)(payload_src + ALIGN(PATCHED_RELOC_SZ, 0x10)), coreboot_addr, 0x7000); // Bootblock.
*(vu32 *)CBFS_DRAM_EN_ADDR = CBFS_DRAM_MAGIC;
}
}
@ -433,12 +429,13 @@ void nyx_init_load_res()
void ipl_main()
{
// Tegra/Horizon configuration goes to 0x80000000+, package2 goes to 0xA9800000, we place our heap in between.
// Set heap address.
heap_init((void *)IPL_HEAP_START);
b_cfg = (boot_cfg_t *)(nyx_str->hekate + 0x94);
#ifdef DEBUG_UART_PORT
// Enable the selected uart debug port.
#if (DEBUG_UART_PORT == UART_B)
gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
#elif (DEBUG_UART_PORT == UART_C)
@ -453,9 +450,10 @@ void ipl_main()
uart_wait_xfer(DEBUG_UART_PORT, UART_TX_IDLE);
#endif
// Initialize the rest of hw and load nyx's resources.
// Initialize the rest of hw and load Nyx resources.
nyx_init_load_res();
// Initialize Nyx GUI and show it.
nyx_load_and_run();
// Halt BPMP if we managed to get out of execution.