From 4eb5b5f91bdbf4baf710966b339e851fb1edc434 Mon Sep 17 00:00:00 2001 From: Kostas Missos Date: Sat, 10 Nov 2018 14:11:42 +0200 Subject: [PATCH] Name more hardcoded regs/vals --- bootloader/gfx/di.c | 14 ++++----- bootloader/gfx/di.h | 3 +- bootloader/gfx/di.inl | 44 +++++++++++++------------- bootloader/main.c | 59 ++++++++++++++++++++-------------- bootloader/mem/mc.c | 4 ++- bootloader/soc/clock.c | 68 +++++++++++++++++++++++++++------------- bootloader/soc/clock.h | 2 ++ bootloader/soc/cluster.c | 8 +++-- bootloader/soc/cluster.h | 8 ++--- bootloader/soc/fuse.h | 5 +++ bootloader/soc/pmc.h | 5 +++ bootloader/soc/t210.h | 45 +++++++++++++++++++++++--- bootloader/utils/util.c | 15 ++++----- 13 files changed, 185 insertions(+), 95 deletions(-) diff --git a/bootloader/gfx/di.c b/bootloader/gfx/di.c index 4dcfe01..cb159d0 100644 --- a/bootloader/gfx/di.c +++ b/bootloader/gfx/di.c @@ -81,7 +81,7 @@ void display_init() gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Backlight Enable enable. // Config display interface and display. - MIPI_CAL(0x60) = 0; + MIPI_CAL(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0; exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4); exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94); @@ -94,11 +94,11 @@ void display_init() usleep(60000); DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204; - DSI(_DSIREG(DSI_WR_DATA)) = 0x337; + DSI(_DSIREG(DSI_WR_DATA)) = 0x337; // MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; _display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO); - DSI(_DSIREG(DSI_WR_DATA)) = 0x406; + DSI(_DSIREG(DSI_WR_DATA)) = 0x406; // MIPI_DCS_GET_DISPLAY_ID DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; _display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO); @@ -111,12 +111,12 @@ void display_init() if (_display_ver == 0x10) exec_cfg((u32 *)DSI_BASE, _display_config_4, 43); - DSI(_DSIREG(DSI_WR_DATA)) = 0x1105; + DSI(_DSIREG(DSI_WR_DATA)) = 0x1105; // MIPI_DCS_EXIT_SLEEP_MODE DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; usleep(180000); - DSI(_DSIREG(DSI_WR_DATA)) = 0x2905; + DSI(_DSIREG(DSI_WR_DATA)) = 0x2905; // MIPI_DCS_SET_DISPLAY_ON DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; usleep(20000); @@ -187,7 +187,7 @@ void display_end() display_backlight_brightness(0, 1000); DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 1; - DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; + DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX; DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; @@ -200,7 +200,7 @@ void display_end() if (_display_ver == 0x10) exec_cfg((u32 *)DSI_BASE, _display_config_14, 22); - DSI(_DSIREG(DSI_WR_DATA)) = 0x1005; + DSI(_DSIREG(DSI_WR_DATA)) = 0x1005; // MIPI_DCS_ENTER_SLEEP_MODE DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; usleep(50000); diff --git a/bootloader/gfx/di.h b/bootloader/gfx/di.h index b3dad4d..f750c12 100644 --- a/bootloader/gfx/di.h +++ b/bootloader/gfx/di.h @@ -342,9 +342,10 @@ #define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) #define DSI_PAD_CONTROL_4 0x52 - #define DSI_INIT_SEQ_DATA_15 0x5F +#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60 + /*! Display backlight related PWM registers. */ #define PWM_CONTROLLER_PWM_CSR 0x00 diff --git a/bootloader/gfx/di.inl b/bootloader/gfx/di.inl index fb6a93c..3d2471b 100644 --- a/bootloader/gfx/di.inl +++ b/bootloader/gfx/di.inl @@ -287,12 +287,12 @@ static const cfg_op_t _display_config_7[10] = { //MIPI CAL config. static const cfg_op_t _display_config_8[6] = { - {0x18, 0}, - {2, 0xF3F10000}, - {0x16, 0}, - {0x18, 0}, - {0x18, 0x10010}, - {0x17, 0x300} + {0x18, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2 + {0x02, 0xF3F10000}, // MIPI_CAL_CIL_MIPI_CAL_STATUS + {0x16, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG0 + {0x18, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2 + {0x18, 0x10010}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2 + {0x17, 0x300} // MIPI_CAL_MIPI_BIAS_PAD_CFG1 }; //DSI config. @@ -305,22 +305,22 @@ static const cfg_op_t _display_config_9[4] = { //MIPI CAL config. static const cfg_op_t _display_config_10[16] = { - {0xE, 0x200200}, - {0xF, 0x200200}, - {0x19, 0x200002}, - {0x1A, 0x200002}, - {5, 0}, - {6, 0}, - {7, 0}, - {8, 0}, - {9, 0}, - {0xA, 0}, - {0x10, 0}, - {0x11, 0}, - {0x1A, 0}, - {0x1C, 0}, - {0x1D, 0}, - {0, 0x2A000001} + {0x0E, 0x200200}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG + {0x0F, 0x200200}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG + {0x19, 0x200002}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 + {0x1A, 0x200002}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 + {0x05, 0}, // MIPI_CAL_CILA_MIPI_CAL_CONFIG + {0x06, 0}, // MIPI_CAL_CILB_MIPI_CAL_CONFIG + {0x07, 0}, // MIPI_CAL_CILC_MIPI_CAL_CONFIG + {0x08, 0}, // MIPI_CAL_CILD_MIPI_CAL_CONFIG + {0x09, 0}, // MIPI_CAL_CILE_MIPI_CAL_CONFIG + {0x0A, 0}, // MIPI_CAL_CILF_MIPI_CAL_CONFIG + {0x10, 0}, // MIPI_CAL_DSIC_MIPI_CAL_CONFIG + {0x11, 0}, // MIPI_CAL_DSID_MIPI_CAL_CONFIG + {0x1A, 0}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 + {0x1C, 0}, // MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 + {0x1D, 0}, // MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 + {0, 0x2A000001} // MIPI_CAL_DSIA_MIPI_CAL_CONFIG }; //Display A config. diff --git a/bootloader/main.c b/bootloader/main.c index a675f91..79079a9 100644 --- a/bootloader/main.c +++ b/bootloader/main.c @@ -212,10 +212,10 @@ void panic(u32 val) // Set panic code. PMC(APBDEV_PMC_SCRATCH200) = val; //PMC(APBDEV_PMC_CRYPTO_OP) = 1; // Disable SE. - TMR(0x18C) = 0xC45A; - TMR(0x80) = 0xC0000000; - TMR(0x180) = 0x8019; - TMR(0x188) = 1; + TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN; + TMR(TIMER_TMR9_TMR_PTV) = TIMER_EN | TIMER_PER_EN; + TMR(TIMER_WDT4_CONFIG) = TIMER_SRC(9) | TIMER_PER(1) | TIMER_PMCRESET_EN; + TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT; while (1) ; } @@ -238,7 +238,7 @@ void reboot_rcm() #endif //MENU_LOGO_ENABLE display_end(); PMC(APBDEV_PMC_SCRATCH0) = 2; // Reboot into rcm. - PMC(0) |= 0x10; + PMC(APBDEV_PMC_CNTRL) |= PMC_CNTRL_MAIN_RST; while (true) usleep(1); } @@ -280,7 +280,7 @@ void config_oscillators() { CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; SYSCTR0(SYSCTR0_CNTFID0) = 19200000; - TMR(0x14) = 0x45F; + TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m. CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | 0x400000; @@ -338,16 +338,16 @@ void mbist_workaround() CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; usleep(2); - I2S(0x0A0) |= 0x400; - I2S(0x088) &= 0xFFFFFFFE; - I2S(0x1A0) |= 0x400; - I2S(0x188) &= 0xFFFFFFFE; - I2S(0x2A0) |= 0x400; - I2S(0x288) &= 0xFFFFFFFE; - I2S(0x3A0) |= 0x400; - I2S(0x388) &= 0xFFFFFFFE; - I2S(0x4A0) |= 0x400; - I2S(0x488) &= 0xFFFFFFFE; + I2S(I2S1_CTRL) |= I2S_CTRL_MASTER_EN; + I2S(I2S1_CG) &= ~I2S_CG_SLCG_ENABLE; + I2S(I2S2_CTRL) |= I2S_CTRL_MASTER_EN; + I2S(I2S2_CG) &= ~I2S_CG_SLCG_ENABLE; + I2S(I2S3_CTRL) |= I2S_CTRL_MASTER_EN; + I2S(I2S3_CG) &= ~I2S_CG_SLCG_ENABLE; + I2S(I2S4_CTRL) |= I2S_CTRL_MASTER_EN; + I2S(I2S4_CG) &= ~I2S_CG_SLCG_ENABLE; + I2S(I2S5_CTRL) |= I2S_CTRL_MASTER_EN; + I2S(I2S5_CG) &= ~I2S_CG_SLCG_ENABLE; DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4; VIC(0x8C) = 0xFFFFFFFF; usleep(2); @@ -377,20 +377,30 @@ void mbist_workaround() void config_se_brom() { // Bootrom part we skipped. - u32 sbk[4] = { FUSE(0x1A4), FUSE(0x1A8), FUSE(0x1AC), FUSE(0x1B0) }; + u32 sbk[4] = { + FUSE(FUSE_PRIVATE_KEY0), + FUSE(FUSE_PRIVATE_KEY1), + FUSE(FUSE_PRIVATE_KEY2), + FUSE(FUSE_PRIVATE_KEY3) + }; + // Set SBK to slot 14. se_aes_key_set(14, sbk, 0x10); + // Lock SBK from being read. SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 14 * 4) = 0x7E; + // This memset needs to happen here, else TZRAM will behave weirdly later on. - memset((void *)0x7C010000, 0, 0x10000); + memset((void *)TZRAM_BASE, 0, 0x10000); PMC(APBDEV_PMC_CRYPTO_OP) = 0; SE(SE_INT_STATUS_REG_OFFSET) = 0x1F; + // Lock SSK (although it's not set and unused anyways). SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 15 * 4) = 0x7E; + // Clear the boot reason to avoid problems later PMC(APBDEV_PMC_SCRATCH200) = 0x0; PMC(APBDEV_PMC_RST_STATUS) = 0x0; - APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = 0x1C00; + APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) |= (7 << 10); } void config_hw() @@ -456,13 +466,13 @@ void config_hw() void reconfig_hw_workaround(bool extra_reconfig, u32 magic) { // Re-enable clocks to Audio Processing Engine as a workaround to hanging. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= 0x400; // Enable AHUB clock. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= 0x40; // Enable APE clock. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock. + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock. if (extra_reconfig) { msleep(10); - PMC(APBDEV_PMC_PWR_DET_VAL) |= (1 << 12); + PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN; clock_disable_cl_dvfs(); @@ -499,7 +509,7 @@ void print_fuseinfo() burntFuses++; } - gfx_printf(&gfx_con, "\nSKU: %X - ", FUSE(0x110)); + gfx_printf(&gfx_con, "\nSKU: %X - ", FUSE(FUSE_SKU_INFO)); switch (fuse_read_odm(4) & 3) { case 0: @@ -512,7 +522,8 @@ void print_fuseinfo() gfx_printf(&gfx_con, "Sdram ID: %d\n", (fuse_read_odm(4) >> 3) & 0x1F); gfx_printf(&gfx_con, "Burnt fuses: %d\n", burntFuses); gfx_printf(&gfx_con, "Secure key: %08X%08X%08X%08X\n\n\n", - byte_swap_32(FUSE(0x1A4)), byte_swap_32(FUSE(0x1A8)), byte_swap_32(FUSE(0x1AC)), byte_swap_32(FUSE(0x1B0))); + byte_swap_32(FUSE(FUSE_PRIVATE_KEY0)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY1)), + byte_swap_32(FUSE(FUSE_PRIVATE_KEY2)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY3))); gfx_printf(&gfx_con, "%k(Unlocked) fuse cache:\n\n%k", 0xFF00DDFF, 0xFFCCCCCC); gfx_hexdump(&gfx_con, 0x7000F900, (u8 *)0x7000F900, 0x2FC); diff --git a/bootloader/mem/mc.c b/bootloader/mem/mc.c index 1e8d1c9..0795acc 100644 --- a/bootloader/mem/mc.c +++ b/bootloader/mem/mc.c @@ -107,6 +107,7 @@ void mc_config_carveout_finalize() void mc_enable_ahb_redirect() { + // Enable ARC_CLK_OVR_ON. CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = (CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) & 0xFFF7FFFF) | 0x80000; //MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE; MC(MC_IRAM_BOM) = 0x40000000; @@ -119,7 +120,8 @@ void mc_disable_ahb_redirect() MC(MC_IRAM_TOM) = 0; // Disable IRAM_CFG_WRITE_ACCESS (sticky). //MC(MC_IRAM_REG_CTRL) = MC(MC_IRAM_REG_CTRL) & 0xFFFFFFFE | 1; - CLOCK(0x3A4) &= 0xFFF7FFFF; + // Disable ARC_CLK_OVR_ON. + CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= 0xFFF7FFFF; } void mc_enable() diff --git a/bootloader/soc/clock.c b/bootloader/soc/clock.c index e745797..411b593 100644 --- a/bootloader/soc/clock.c +++ b/bootloader/soc/clock.c @@ -19,37 +19,61 @@ #include "../utils/util.h" #include "../storage/sdmmc.h" +/* clock_t: reset, enable, source, index, clk_src, clk_div */ + static const clock_t _clock_uart[] = { - /* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 0 }, - /* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 0 }, + /* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 0 }, + /* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 0 }, /* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 0x17, 0, 0 }, /* UART D */ { 0 }, /* UART E */ { 0 } }; static const clock_t _clock_i2c[] = { - /* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 0xC, 6, 0 }, - /* I2C2 */ { 0 }, - /* I2C3 */ { 0 }, - /* I2C4 */ { 0 }, - /* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 6, 0 }, +/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 0xC, 6, 0 }, +/* I2C2 */ { 0 }, +/* I2C3 */ { 0 }, +/* I2C4 */ { 0 }, +/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 6, 0 }, /* I2C6 */ { 0 } }; -static clock_t _clock_se = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 0x1F, 0, 0 }; -static clock_t _clock_unk2 = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_RST_SOURCE, 0x1E, 0, 0 }; +static clock_t _clock_se = { + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 0x1F, 0, 0 +}; +static clock_t _clock_unk2 = { + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, 0x1E, 0, 0 +}; -static clock_t _clock_host1x = { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3 }; -static clock_t _clock_tsec = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2 }; -static clock_t _clock_sor_safe = { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_RST_SOURCE, 0x1E, 0, 0 }; -static clock_t _clock_sor0 = { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_RST_SOURCE, 0x16, 0, 0 }; -static clock_t _clock_sor1 = { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 0x17, 0, 2 }; -static clock_t _clock_kfuse = { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_RST_SOURCE, 8, 0, 0 }; +static clock_t _clock_host1x = { + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3 +}; +static clock_t _clock_tsec = { + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2 +}; +static clock_t _clock_sor_safe = { + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, 0x1E, 0, 0 +}; +static clock_t _clock_sor0 = { + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, 0x16, 0, 0 +}; +static clock_t _clock_sor1 = { + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 0x17, 0, 2 +}; +static clock_t _clock_kfuse = { + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, 8, 0, 0 +}; -static clock_t _clock_cl_dvfs = { CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_RST_CONTROLLER_RST_SOURCE, 0x1B, 0, 0 }; -static clock_t _clock_coresight = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4}; +static clock_t _clock_cl_dvfs = { + CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, 0x1B, 0, 0 +}; +static clock_t _clock_coresight = { + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4 +}; -static clock_t _clock_pwm = { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 0x11, 6, 4}; +static clock_t _clock_pwm = { + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 0x11, 6, 4 +}; void clock_enable(const clock_t *clk) { @@ -157,11 +181,11 @@ void clock_disable_sor1() void clock_enable_kfuse() { //clock_enable(&_clock_kfuse); - CLOCK(0x8) = (CLOCK(0x8) & 0xFFFFFEFF) | 0x100; - CLOCK(0x14) &= 0xFFFFFEFF; - CLOCK(0x14) = (CLOCK(0x14) & 0xFFFFFEFF) | 0x100; + CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) = (CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) & 0xFFFFFEFF) | 0x100; + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) &= 0xFFFFFEFF; + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) & 0xFFFFFEFF) | 0x100; usleep(10); - CLOCK(0x8) &= 0xFFFFFEFF; + CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= 0xFFFFFEFF; usleep(20); } diff --git a/bootloader/soc/clock.h b/bootloader/soc/clock.h index 5b60329..8e36069 100644 --- a/bootloader/soc/clock.h +++ b/bootloader/soc/clock.h @@ -116,6 +116,8 @@ #define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0 #define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704 +#define CLK_NO_SOURCE 0x0 + /*! Generic clock descriptor. */ typedef struct _clock_t { diff --git a/bootloader/soc/cluster.c b/bootloader/soc/cluster.c index 857641a..d158349 100644 --- a/bootloader/soc/cluster.c +++ b/bootloader/soc/cluster.c @@ -30,10 +30,12 @@ void _cluster_enable_power() i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH); // Enable cores power. + // 1-3.x: MAX77621_NFSR_ENABLE. i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, - MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE); // 1-3.x: MAX77621_NFSR_ENABLE + MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE); + // 1.0.0-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL. i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG, - MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL); // 1-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL + MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL); i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | 0x37); i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | 0x37); } @@ -112,7 +114,7 @@ void cluster_boot_cpu0(u32 entry) while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2)) ; - EXCP_VEC(0x100) = 0; + EXCP_VEC(EVP_CPU_RESET_VECTOR) = 0; // Set reset vector. SB(SB_AA64_RESET_LOW) = entry | 1; diff --git a/bootloader/soc/cluster.h b/bootloader/soc/cluster.h index 76e80c0..5cecd19 100644 --- a/bootloader/soc/cluster.h +++ b/bootloader/soc/cluster.h @@ -20,10 +20,10 @@ #include "../utils/types.h" /*! Flow controller registers. */ -#define LOW_CTLR_HALT_CPU0_EVENTS 0x0 -#define LOW_CTLR_HALT_CPU1_EVENTS 0x14 -#define LOW_CTLR_HALT_CPU2_EVENTS 0x1C -#define LOW_CTLR_HALT_CPU3_EVENTS 0x24 +#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0 +#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14 +#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C +#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24 #define FLOW_CTLR_HALT_COP_EVENTS 0x4 #define FLOW_CTLR_CPU0_CSR 0x8 #define FLOW_CTLR_CPU1_CSR 0x18 diff --git a/bootloader/soc/fuse.h b/bootloader/soc/fuse.h index 1145478..b2f04e0 100644 --- a/bootloader/soc/fuse.h +++ b/bootloader/soc/fuse.h @@ -36,7 +36,12 @@ #define FUSE_DISABLEREGPROGRAM 0x2C #define FUSE_WRITE_ACCESS_SW 0x30 #define FUSE_PWR_GOOD_SW 0x34 +#define FUSE_SKU_INFO 0x110 #define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19c +#define FUSE_PRIVATE_KEY0 0x1A4 +#define FUSE_PRIVATE_KEY1 0x1A8 +#define FUSE_PRIVATE_KEY2 0x1AC +#define FUSE_PRIVATE_KEY3 0x1B0 /*! Fuse commands. */ #define FUSE_READ 0x1 diff --git a/bootloader/soc/pmc.h b/bootloader/soc/pmc.h index f319287..7f3c826 100644 --- a/bootloader/soc/pmc.h +++ b/bootloader/soc/pmc.h @@ -19,6 +19,8 @@ #define _PMC_H_ /*! PMC registers. */ +#define APBDEV_PMC_CNTRL 0x0 +#define PMC_CNTRL_MAIN_RST (1 << 4) #define APBDEV_PMC_SEC_DISABLE 0x4 #define APBDEV_PMC_PWRGATE_TOGGLE 0x30 #define APBDEV_PMC_PWRGATE_STATUS 0x38 @@ -27,6 +29,7 @@ #define APBDEV_PMC_SCRATCH1 0x54 #define APBDEV_PMC_SCRATCH20 0xA0 #define APBDEV_PMC_PWR_DET_VAL 0xE4 +#define PMC_PWR_DET_SDMMC1_IO_EN (1 << 12) #define APBDEV_PMC_DDR_PWR 0xE8 #define APBDEV_PMC_CRYPTO_OP 0xF4 #define APBDEV_PMC_OSC_EDPD_OVER 0x1A4 @@ -34,6 +37,7 @@ #define APBDEV_PMC_IO_DPD_REQ 0x1B8 #define APBDEV_PMC_IO_DPD2_REQ 0x1C0 #define APBDEV_PMC_VDDP_SEL 0x1CC +#define APBDEV_PMC_DDR_CFG 0x1D0 #define APBDEV_PMC_SCRATCH49 0x244 #define APBDEV_PMC_TSC_MULT 0x2B4 #define APBDEV_PMC_SEC_DISABLE2 0x2C4 @@ -44,6 +48,7 @@ #define APBDEV_PMC_SECURE_SCRATCH32 0x360 #define APBDEV_PMC_SECURE_SCRATCH49 0x3A4 #define APBDEV_PMC_CNTRL2 0x440 +#define APBDEV_PMC_IO_DPD3_REQ 0x45C #define APBDEV_PMC_IO_DPD4_REQ 0x464 #define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4 #define APBDEV_PMC_UTMIP_PAD_CFG3 0x4CC diff --git a/bootloader/soc/t210.h b/bootloader/soc/t210.h index fe662cf..bd7e4f9 100644 --- a/bootloader/soc/t210.h +++ b/bootloader/soc/t210.h @@ -56,8 +56,9 @@ #define MC_BASE 0x70019000 #define EMC_BASE 0x7001B000 #define MIPI_CAL_BASE 0x700E3000 -#define I2S_BASE 0x702D1000 #define CL_DVFS_BASE 0x70110000 +#define I2S_BASE 0x702D1000 +#define TZRAM_BASE 0x7C010000 #define _REG(base, off) *(vu32 *)((base) + (off)) @@ -99,6 +100,9 @@ #define CL_DVFS(off) _REG(CL_DVFS_BASE, off) #define TEST_REG(off) _REG(0x0, off) +/*! EVP registers. */ +#define EVP_CPU_RESET_VECTOR 0x100 + /*! Misc registers. */ #define APB_MISC_PP_STRAPPING_OPT_A 0x08 #define APB_MISC_PP_PINMUX_GLOBAL 0x40 @@ -112,10 +116,43 @@ /*! Secure boot registers. */ #define SB_CSR 0x0 -#define SB_AA64_RESET_LOW 0x30 +#define SB_AA64_RESET_LOW 0x30 #define SB_AA64_RESET_HIGH 0x34 -/*! SYSCTR0 registers. */ -#define SYSCTR0_CNTFID0 0x20 +/*! RTC registers. */ +#define APBDEV_RTC_SECONDS 0x8 +#define APBDEV_RTC_SHADOW_SECONDS 0xC +#define APBDEV_RTC_MILLI_SECONDS 0x10 + +/*! TMR registers. */ +#define TIMERUS_CNTR_1US (0x10 + 0x0) +#define TIMERUS_USEC_CFG (0x10 + 0x4) +#define TIMER_TMR9_TMR_PTV 0x80 +#define TIMER_EN (1 << 31) +#define TIMER_PER_EN (1 << 30) +#define TIMER_WDT4_CONFIG (0x100 + 0x80) +#define TIMER_SRC(TMR) (TMR & 0xF) +#define TIMER_PER(PER) ((PER & 0xFF) << 4) +#define TIMER_SYSRESET_EN (1 << 14) +#define TIMER_PMCRESET_EN (1 << 15) +#define TIMER_WDT4_COMMAND (0x108 + 0x80) +#define TIMER_START_CNT (1 << 0) +#define TIMER_CNT_DISABLE (1 << 1) +#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80) +#define TIMER_MAGIC_PTRN 0xC45A + +/*! I2S registers. */ +#define I2S1_CG 0x88 +#define I2S1_CTRL 0xA0 +#define I2S2_CG 0x188 +#define I2S2_CTRL 0x1A0 +#define I2S3_CG 0x288 +#define I2S3_CTRL 0x2A0 +#define I2S4_CG 0x388 +#define I2S4_CTRL 0x3A0 +#define I2S5_CG 0x488 +#define I2S5_CTRL 0x4A0 +#define I2S_CG_SLCG_ENABLE (1 << 0) +#define I2S_CTRL_MASTER_EN (1 << 10) #endif diff --git a/bootloader/utils/util.c b/bootloader/utils/util.c index e048777..7e80c2f 100644 --- a/bootloader/utils/util.c +++ b/bootloader/utils/util.c @@ -20,32 +20,33 @@ u32 get_tmr_s() { - return RTC(0x8); //RTC_SECONDS + return RTC(APBDEV_RTC_SECONDS); } u32 get_tmr_ms() { // The registers must be read with the following order: // -> RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC) - return (RTC(0x10) | (RTC(0xC)<< 10)); + return (RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS)<< 10)); } u32 get_tmr_us() { - return TMR(0x10); //TIMERUS_CNTR_1US + return TMR(TIMERUS_CNTR_1US); //TIMERUS_CNTR_1US } void msleep(u32 milliseconds) { - u32 start = RTC(0x10) | (RTC(0xC)<< 10); - while (((RTC(0x10) | (RTC(0xC)<< 10)) - start) <= milliseconds) + u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS)<< 10); + while (((RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS)<< 10)) - start) <= milliseconds) ; } void usleep(u32 microseconds) { - u32 start = TMR(0x10); - while ((TMR(0x10) - start) <= microseconds) + u32 start = TMR(TIMERUS_CNTR_1US); + // Casting to u32 is important! + while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= microseconds) ; }