diff --git a/bdk/mem/mc_t210.h b/bdk/mem/mc_t210.h index 5bf8ce8..a4590b3 100644 --- a/bdk/mem/mc_t210.h +++ b/bdk/mem/mc_t210.h @@ -464,6 +464,98 @@ #define MC_UNTRANSLATED_REGION_CHECK 0x948 #define MC_DA_CONFIG0 0x9dc +/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS0 */ +#define SEC_CARVEOUT_CA0_R_PTCR BIT(0) +#define SEC_CARVEOUT_CA0_R_DISPLAY0A BIT(1) +#define SEC_CARVEOUT_CA0_R_DISPLAY0AB BIT(2) +#define SEC_CARVEOUT_CA0_R_DISPLAY0B BIT(3) +#define SEC_CARVEOUT_CA0_R_DISPLAY0BB BIT(4) +#define SEC_CARVEOUT_CA0_R_DISPLAY0C BIT(5) +#define SEC_CARVEOUT_CA0_R_DISPLAY0CB BIT(6) +#define SEC_CARVEOUT_CA0_R_AFI BIT(14) +#define SEC_CARVEOUT_CA0_R_BPMP_C BIT(15) +#define SEC_CARVEOUT_CA0_R_DISPLAYHC BIT(16) +#define SEC_CARVEOUT_CA0_R_DISPLAYHCB BIT(17) +#define SEC_CARVEOUT_CA0_R_HDA BIT(21) +#define SEC_CARVEOUT_CA0_R_HOST1XDMA BIT(22) +#define SEC_CARVEOUT_CA0_R_HOST1X BIT(23) +#define SEC_CARVEOUT_CA0_R_NVENC BIT(28) +#define SEC_CARVEOUT_CA0_R_PPCSAHBDMA BIT(29) +#define SEC_CARVEOUT_CA0_R_PPCSAHBSLV BIT(30) +#define SEC_CARVEOUT_CA0_R_SATAR BIT(31) + +/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS1 */ +#define SEC_CARVEOUT_CA1_R_VDEBSEV BIT(2) +#define SEC_CARVEOUT_CA1_R_VDEMBE BIT(3) +#define SEC_CARVEOUT_CA1_R_VDEMCE BIT(4) +#define SEC_CARVEOUT_CA1_R_VDETPE BIT(5) +#define SEC_CARVEOUT_CA1_R_CCPLEXLP_C BIT(6) +#define SEC_CARVEOUT_CA1_R_CCPLEX_C BIT(7) +#define SEC_CARVEOUT_CA1_W_NVENC BIT(11) +#define SEC_CARVEOUT_CA1_W_AFI BIT(17) +#define SEC_CARVEOUT_CA1_W_BPMP_C BIT(18) +#define SEC_CARVEOUT_CA1_W_HDA BIT(21) +#define SEC_CARVEOUT_CA1_W_HOST1X BIT(22) +#define SEC_CARVEOUT_CA1_W_CCPLEXLP_C BIT(24) +#define SEC_CARVEOUT_CA1_W_CCPLEX_C BIT(25) +#define SEC_CARVEOUT_CA1_W_PPCSAHBDMA BIT(27) +#define SEC_CARVEOUT_CA1_W_PPCSAHBSLV BIT(28) +#define SEC_CARVEOUT_CA1_W_SATA BIT(29) +#define SEC_CARVEOUT_CA1_W_VDEBSEV BIT(30) +#define SEC_CARVEOUT_CA1_W_VDEDBG BIT(31) + +/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS2 */ +#define SEC_CARVEOUT_CA2_W_VDEMBE BIT(0) +#define SEC_CARVEOUT_CA2_W_VDETPM BIT(1) +#define SEC_CARVEOUT_CA2_R_ISPRA BIT(4) +#define SEC_CARVEOUT_CA2_W_ISPWA BIT(6) +#define SEC_CARVEOUT_CA2_W_ISPWB BIT(7) +#define SEC_CARVEOUT_CA2_R_XUSB_HOST BIT(10) +#define SEC_CARVEOUT_CA2_W_XUSB_HOST BIT(11) +#define SEC_CARVEOUT_CA2_R_XUSB_DEV BIT(12) +#define SEC_CARVEOUT_CA2_W_XUSB_DEV BIT(13) +#define SEC_CARVEOUT_CA2_R_SE2 BIT(14) +#define SEC_CARVEOUT_CA2_W_SE2 BIT(16) +#define SEC_CARVEOUT_CA2_R_TSEC BIT(20) +#define SEC_CARVEOUT_CA2_W_TSEC BIT(21) +#define SEC_CARVEOUT_CA2_R_ADSP_SC BIT(22) +#define SEC_CARVEOUT_CA2_W_ADSP_SC BIT(23) +#define SEC_CARVEOUT_CA2_R_GPU BIT(24) +#define SEC_CARVEOUT_CA2_W_GPU BIT(25) +#define SEC_CARVEOUT_CA2_R_DISPLAYT BIT(26) + +/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS3 */ +#define SEC_CARVEOUT_CA3_R_SDMMCA BIT(0) +#define SEC_CARVEOUT_CA3_R_SDMMCAA BIT(1) +#define SEC_CARVEOUT_CA3_R_SDMMC BIT(2) +#define SEC_CARVEOUT_CA3_R_SDMMCAB BIT(3) +#define SEC_CARVEOUT_CA3_W_SDMMCA BIT(4) +#define SEC_CARVEOUT_CA3_W_SDMMCAA BIT(5) +#define SEC_CARVEOUT_CA3_W_SDMMC BIT(6) +#define SEC_CARVEOUT_CA3_W_SDMMCAB BIT(7) +#define SEC_CARVEOUT_CA3_R_VIC BIT(12) +#define SEC_CARVEOUT_CA3_W_VIC BIT(13) +#define SEC_CARVEOUT_CA3_W_VIW BIT(18) +#define SEC_CARVEOUT_CA3_R_DISPLAYD BIT(19) +#define SEC_CARVEOUT_CA3_R_NVDEC BIT(24) +#define SEC_CARVEOUT_CA3_W_NVDEC BIT(25) +#define SEC_CARVEOUT_CA3_R_APE BIT(26) +#define SEC_CARVEOUT_CA3_W_APE BIT(27) +#define SEC_CARVEOUT_CA3_R_NVJPG BIT(30) +#define SEC_CARVEOUT_CA3_W_NVJPG BIT(31) + +/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS4 */ +#define SEC_CARVEOUT_CA4_R_SE BIT(0) +#define SEC_CARVEOUT_CA4_W_SE BIT(1) +#define SEC_CARVEOUT_CA4_R_AXIAP BIT(2) +#define SEC_CARVEOUT_CA4_W_AXIAP BIT(3) +#define SEC_CARVEOUT_CA4_R_ETR BIT(4) +#define SEC_CARVEOUT_CA4_W_ETR BIT(5) +#define SEC_CARVEOUT_CA4_R_TSECB BIT(6) +#define SEC_CARVEOUT_CA4_W_TSECB BIT(7) +#define SEC_CARVEOUT_CA4_R_GPU2 BIT(8) +#define SEC_CARVEOUT_CA4_W_GPU2 BIT(9) + // MC_VIDEO_PROTECT_REG_CTRL #define VPR_LOCK_MODE_SHIFT 0 #define VPR_CTRL_UNLOCKED (0 << VPR_LOCK_MODE_SHIFT) @@ -475,8 +567,8 @@ // MC_SECURITY_CARVEOUTX_CFG0 // Mode of LOCK_MODE. #define PROTECT_MODE_SHIFT 0 -#define SEC_CARVEOUT_CFG_SECURE (0 << PROTECT_MODE_SHIFT) -#define SEC_CARVEOUT_CFG_TZ_SECURE (1 << PROTECT_MODE_SHIFT) +#define SEC_CARVEOUT_CFG_ALL_SECURE (0 << PROTECT_MODE_SHIFT) +#define SEC_CARVEOUT_CFG_TZ_SECURE (1 << PROTECT_MODE_SHIFT) // Enables PROTECT_MODE. #define LOCK_MODE_SHIFT 1 #define SEC_CARVEOUT_CFG_UNLOCKED (0 << LOCK_MODE_SHIFT) @@ -499,6 +591,7 @@ #define SEC_CARVEOUT_CFG_WR_FALCON_HS (8 << WRITE_ACCESS_LEVEL_SHIFT) #define SEC_CARVEOUT_CFG_APERTURE_ID_MASK (3 << 11) +#define SEC_CARVEOUT_CFG_APERTURE_ID(id) ((id) << 11) #define DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT 14 #define SEC_CARVEOUT_CFG_DIS_RD_CHECK_L0 (1 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT) diff --git a/bdk/soc/clock.c b/bdk/soc/clock.c index b122cf9..8362d9e 100644 --- a/bdk/soc/clock.c +++ b/bdk/soc/clock.c @@ -61,17 +61,21 @@ static const clock_t _clock_i2c[] = { static clock_t _clock_se = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, CLK_V_SE, 0, 0 // 408MHz. }; - static clock_t _clock_tzram = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, CLK_V_TZRAM, 0, 0 }; - static clock_t _clock_host1x = { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, CLK_L_HOST1X, 4, 3 // 163.2MHz. }; static clock_t _clock_tsec = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, CLK_U_TSEC, 0, 2 // 204MHz. }; +static clock_t _clock_nvdec = { + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, 0x698, CLK_Y_NVDEC, 4, 0 // 408 MHz. +}; +static clock_t _clock_nvjpg = { + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, 0x69C, CLK_Y_NVJPG, 4, 0 // 408 MHz. +}; static clock_t _clock_sor_safe = { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, CLK_Y_SOR_SAFE, 0, 0 }; @@ -84,30 +88,24 @@ static clock_t _clock_sor1 = { static clock_t _clock_kfuse = { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_KFUSE, 0, 0 }; - static clock_t _clock_cl_dvfs = { CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, CLK_W_DVFS, 0, 0 }; static clock_t _clock_coresight = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, CLK_U_CSITE, 0, 4 // 136MHz. }; - static clock_t _clock_pwm = { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, CLK_L_PWM, 6, 4 // Fref: 6.4MHz. HOS: PLLP / 54 = 7.55MHz. }; - static clock_t _clock_sdmmc_legacy_tm = { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, CLK_Y_SDMMC_LEGACY_TM, 4, 66 }; - static clock_t _clock_apbdma = { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_APBDMA, 0, 0 }; - static clock_t _clock_ahbdma = { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_AHBDMA, 0, 0 }; - static clock_t _clock_actmon = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON, CLK_V_ACTMON, 6, 0 // 19.2MHz. }; @@ -215,6 +213,26 @@ void clock_disable_tsec() clock_disable(&_clock_tsec); } +void clock_enable_nvdec() +{ + clock_enable(&_clock_nvdec); +} + +void clock_disable_nvdec() +{ + clock_disable(&_clock_nvdec); +} + +void clock_enable_nvjpg() +{ + clock_enable(&_clock_nvjpg); +} + +void clock_disable_nvjpg() +{ + clock_disable(&_clock_nvjpg); +} + void clock_enable_sor_safe() { clock_enable(&_clock_sor_safe); diff --git a/bdk/soc/clock.h b/bdk/soc/clock.h index 6b504f8..1733992 100644 --- a/bdk/soc/clock.h +++ b/bdk/soc/clock.h @@ -646,6 +646,10 @@ void clock_enable_host1x(); void clock_disable_host1x(); void clock_enable_tsec(); void clock_disable_tsec(); +void clock_enable_nvdec(); +void clock_disable_nvdec(); +void clock_enable_nvjpg(); +void clock_disable_nvjpg(); void clock_enable_sor_safe(); void clock_disable_sor_safe(); void clock_enable_sor0(); diff --git a/bdk/soc/t210.h b/bdk/soc/t210.h index cbacfdf..47934f1 100644 --- a/bdk/soc/t210.h +++ b/bdk/soc/t210.h @@ -227,20 +227,22 @@ #define APBDEV_RTC_MILLI_SECONDS 0x10 /*! SYSCTR0 registers. */ -#define SYSCTR0_CNTFID0 0x20 -#define SYSCTR0_CNTCR 0x00 -#define SYSCTR0_COUNTERID0 0xFE0 -#define SYSCTR0_COUNTERID1 0xFE4 -#define SYSCTR0_COUNTERID2 0xFE8 -#define SYSCTR0_COUNTERID3 0xFEC -#define SYSCTR0_COUNTERID4 0xFD0 -#define SYSCTR0_COUNTERID5 0xFD4 -#define SYSCTR0_COUNTERID6 0xFD8 -#define SYSCTR0_COUNTERID7 0xFDC -#define SYSCTR0_COUNTERID8 0xFF0 -#define SYSCTR0_COUNTERID9 0xFF4 -#define SYSCTR0_COUNTERID10 0xFF8 -#define SYSCTR0_COUNTERID11 0xFFC +#define SYSCTR0_CNTCR 0x00 +#define SYSCTR0_CNTFID0 0x20 +#define SYSCTR0_COUNTERS_BASE 0xFD0 +#define SYSCTR0_COUNTERS 12 +#define SYSCTR0_COUNTERID0 0xFE0 +#define SYSCTR0_COUNTERID1 0xFE4 +#define SYSCTR0_COUNTERID2 0xFE8 +#define SYSCTR0_COUNTERID3 0xFEC +#define SYSCTR0_COUNTERID4 0xFD0 +#define SYSCTR0_COUNTERID5 0xFD4 +#define SYSCTR0_COUNTERID6 0xFD8 +#define SYSCTR0_COUNTERID7 0xFDC +#define SYSCTR0_COUNTERID8 0xFF0 +#define SYSCTR0_COUNTERID9 0xFF4 +#define SYSCTR0_COUNTERID10 0xFF8 +#define SYSCTR0_COUNTERID11 0xFFC /*! TMR registers. */ #define TIMERUS_CNTR_1US (0x10 + 0x0)