From 3db55df0a66e4d194ee83cbbdda8f81f9edc09f6 Mon Sep 17 00:00:00 2001 From: CTCaer Date: Thu, 30 Apr 2020 13:45:28 +0300 Subject: [PATCH] display v2: Refactor everything --- Makefile | 2 +- bootloader/gfx/di.c | 57 ++++++---- bootloader/gfx/di.h | 44 +++++++- bootloader/gfx/di.inl | 177 +++++++++++++---------------- nyx/nyx_gui/frontend/gui.c | 2 +- nyx/nyx_gui/gfx/di.c | 81 ++++++------- nyx/nyx_gui/gfx/di.h | 48 +++++++- nyx/nyx_gui/gfx/di.inl | 226 +++++++++++++++++-------------------- 8 files changed, 350 insertions(+), 287 deletions(-) diff --git a/Makefile b/Makefile index a739cdd..a574862 100755 --- a/Makefile +++ b/Makefile @@ -29,7 +29,7 @@ OBJS = $(addprefix $(BUILDDIR)/$(TARGET)/, \ # Hardware. OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \ bpmp.o clock.o cluster.o di.o gpio.o i2c.o irq.o mc.o sdram.o \ - pinmux.o se.o smmu.o timer.o tsec.o uart.o \ + pinmux.o se.o smmu.o tsec.o uart.o \ fuse.o kfuse.o minerva.o \ sdmmc.o sdmmc_driver.o emummc.o nx_emmc.o nx_sd.o \ bq24193.o max17050.o max7762x.o max77620-rtc.o \ diff --git a/bootloader/gfx/di.c b/bootloader/gfx/di.c index 200d412..183698b 100644 --- a/bootloader/gfx/di.c +++ b/bootloader/gfx/di.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2019 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -60,16 +60,16 @@ void display_init() CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000; // Set enable clock DSIA_LP. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10; // Set PLLP_OUT and div 6 (68MHz). - // Disable deap power down. + // Disable deep power down. PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000; PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000; // Config LCD and Backlight pins. - PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE; - PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE; - PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; - PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE; - PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE; + PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN + PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE; // PULL_DOWN + PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; // PULL_DOWN | 1 + PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN + PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE; // PULL_DOWN // Set Backlight +-5V pins mode and direction gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO); @@ -87,14 +87,18 @@ void display_init() gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Enable Backlight EN. // Power up supply regulator for display interface. - MIPI_CAL(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0; + MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0; - // Set DISP1 clock source and parrent clock. - exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4); + // Set DISP1 clock source and parent clock. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1) = 0x40000000; // PLLD_OUT. + u32 plld_div = (3 << 20) | (20 << 11) | 1; // DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 96 MHz. + CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div; + CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20; // PLLD_SETUP. + CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2D0AAA; // PLLD_ENABLE_CLK. // Setup display communication interfaces. - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94); - exec_cfg((u32 *)DSI_BASE, _display_config_3, 61); + exec_cfg((u32 *)DISPLAY_A_BASE, _display_dc_setup_win_config, 94); + exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config, 61); usleep(10000); // Enable Backlight Reset. @@ -118,7 +122,7 @@ void display_init() _display_ver = DSI(_DSIREG(DSI_RD_DATA)); if (_display_ver == 0x10) - exec_cfg((u32 *)DSI_BASE, _display_config_4, 43); + exec_cfg((u32 *)DSI_BASE, _display_init_config_jdi, 43); DSI(_DSIREG(DSI_WR_DATA)) = 0x1105; // MIPI_DCS_EXIT_SLEEP_MODE DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; @@ -131,22 +135,25 @@ void display_init() usleep(20000); // Configure PLLD for DISP1. - exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3); + plld_div = (1 << 20) | (24 << 11) | 1; // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 460.8 MHz. + CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div; + CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20; + CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00; // Use new PLLD_SDM_DIN. // Finalize DSI configuration. - exec_cfg((u32 *)DSI_BASE, _display_config_5, 21); - DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; - exec_cfg((u32 *)DSI_BASE, _display_config_7, 10); + exec_cfg((u32 *)DSI_BASE, _display_dsi_packet_config, 21); + DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; // PCD1 | div3. + exec_cfg((u32 *)DSI_BASE, _display_dsi_mode_config, 10); usleep(10000); // Calibrate display communication pads. - exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6); - exec_cfg((u32 *)DSI_BASE, _display_config_9, 4); - exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16); + exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_pad_cal_config, 6); + exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config, 4); + exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_apply_dsi_cal_config, 16); usleep(10000); // Enable video display controller. - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113); + exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_enable_config, 113); } void display_backlight_pwm_init() @@ -197,20 +204,20 @@ void display_end() { display_backlight_brightness(0, 1000); - DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 1; + DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE; DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX; DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; // Disable host cmd packet. // De-initialize video controller. - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17); - exec_cfg((u32 *)DSI_BASE, _display_config_13, 16); + exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_disable_config, 17); + exec_cfg((u32 *)DSI_BASE, _display_dsi_timing_deinit_config, 16); usleep(10000); // De-initialize display panel. if (_display_ver == 0x10) - exec_cfg((u32 *)DSI_BASE, _display_config_14, 22); + exec_cfg((u32 *)DSI_BASE, _display_deinit_config_jdi, 22); DSI(_DSIREG(DSI_WR_DATA)) = 0x1005; // MIPI_DCS_ENTER_SLEEP_MODE DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; diff --git a/bootloader/gfx/di.h b/bootloader/gfx/di.h index ee796a7..bdb8a1e 100644 --- a/bootloader/gfx/di.h +++ b/bootloader/gfx/di.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2019 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -187,6 +187,13 @@ #define CSC_ENABLE (1 << 18) #define WIN_ENABLE (1 << 30) +#define DC_WIN_BUFFER_CONTROL 0x702 +#define BUFFER_CONTROL_HOST 0 +#define BUFFER_CONTROL_VI 1 +#define BUFFER_CONTROL_EPP 2 +#define BUFFER_CONTROL_MPEGE 3 +#define BUFFER_CONTROL_SB2D 4 + #define DC_WIN_COLOR_DEPTH 0x703 #define WIN_COLOR_DEPTH_P1 0x0 #define WIN_COLOR_DEPTH_P2 0x1 @@ -336,6 +343,7 @@ #define DSI_PAD_CONTROL_CD 0x4C #define DSI_VIDEO_MODE_CONTROL 0x4E +#define DSI_CMD_PKT_VID_ENABLE 1 #define DSI_PAD_CONTROL_1 0x4F #define DSI_PAD_CONTROL_2 0x50 @@ -349,7 +357,39 @@ #define DSI_PAD_CONTROL_4 0x52 #define DSI_INIT_SEQ_DATA_15 0x5F -#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60 +/*! MIPI registers. */ +#define MIPI_CAL_MIPI_CAL_CTRL (0x00 / 0x4) +#define MIPI_CAL_CIL_MIPI_CAL_STATUS (0x08 / 0x4) +#define MIPI_CAL_CILA_MIPI_CAL_CONFIG (0x14 / 0x4) +#define MIPI_CAL_CILB_MIPI_CAL_CONFIG (0x18 / 0x4) +#define MIPI_CAL_CILC_MIPI_CAL_CONFIG (0x1C / 0x4) +#define MIPI_CAL_CILD_MIPI_CAL_CONFIG (0x20 / 0x4) +#define MIPI_CAL_CILE_MIPI_CAL_CONFIG (0x24 / 0x4) +#define MIPI_CAL_CILF_MIPI_CAL_CONFIG (0x28 / 0x4) +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG (0x38 / 0x4) +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG (0x3C / 0x4) +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG (0x40 / 0x4) +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG (0x44 / 0x4) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 (0x58 / 0x4) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 (0x5C / 0x4) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 (0x60 / 0x4) +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 (0x64 / 0x4) +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 (0x68 / 0x4) +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 (0x70 / 0x4) +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x74 / 0x4) + +/*! MIPI CMDs. */ +#define MIPI_DSI_DCS_SHORT_WRITE 0x05 +#define MIPI_DSI_DCS_READ 0x06 +#define MIPI_DSI_DCS_SHORT_WRITE_PARAM 0x15 +#define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37 +#define MIPI_DSI_DCS_LONG_WRITE 0x39 + +/*! MIPI DCS CMDs. */ +#define MIPI_DCS_GET_DISPLAY_ID 0x04 +#define MIPI_DCS_ENTER_SLEEP_MODE 0x10 +#define MIPI_DCS_EXIT_SLEEP_MODE 0x11 +#define MIPI_DCS_SET_DISPLAY_ON 0x29 void display_init(); void display_backlight_pwm_init(); diff --git a/bootloader/gfx/di.inl b/bootloader/gfx/di.inl index dd82899..cbed2a1 100644 --- a/bootloader/gfx/di.inl +++ b/bootloader/gfx/di.inl @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert -* Copyright (c) 2018 CTCaer +* Copyright (c) 2018-2019 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,16 +15,8 @@ * along with this program. If not, see . */ -//Clock config. -static const cfg_op_t _display_config_1[4] = { - {0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 - {0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC -}; - //Display A config. -static const cfg_op_t _display_config_2[94] = { +static const cfg_op_t _display_dc_setup_win_config[94] = { {DC_CMD_STATE_ACCESS, 0}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, @@ -128,7 +120,7 @@ static const cfg_op_t _display_config_2[94] = { }; //DSI Init config. -static const cfg_op_t _display_config_3[61] = { +static const cfg_op_t _display_dsi_init_config[61] = { {DSI_WR_DATA, 0}, {DSI_INT_ENABLE, 0}, {DSI_INT_STATUS, 0}, @@ -192,14 +184,14 @@ static const cfg_op_t _display_config_3[61] = { {DSI_INIT_SEQ_CONTROL, 0} }; -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_4[43] = { - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0x9483FFB9}, +//DSI panel config. +static const cfg_op_t _display_init_config_jdi[43] = { + {DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. + {DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94). {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xBD15}, + {DSI_WR_DATA, 0x00BD15}, // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x0BD. {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x1939}, + {DSI_WR_DATA, 0x1939}, // MIPI_DSI_DCS_LONG_WRITE: 25 bytes. {DSI_WR_DATA, 0xAAAAAAD8}, {DSI_WR_DATA, 0xAAAAAAEB}, {DSI_WR_DATA, 0xAAEBAAAA}, @@ -208,9 +200,9 @@ static const cfg_op_t _display_config_4[43] = { {DSI_WR_DATA, 0xAAEBAAAA}, {DSI_WR_DATA, 0xAA}, {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x1BD15}, + {DSI_WR_DATA, 0x01BD15}, // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x1BD. {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2739}, + {DSI_WR_DATA, 0x2739}, // MIPI_DSI_DCS_LONG_WRITE: 39 bytes. {DSI_WR_DATA, 0xFFFFFFD8}, {DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF}, @@ -222,25 +214,25 @@ static const cfg_op_t _display_config_4[43] = { {DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFF}, {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2BD15}, + {DSI_WR_DATA, 0x02BD15}, // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x2BD. {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xF39}, + {DSI_WR_DATA, 0xF39}, // MIPI_DSI_DCS_LONG_WRITE: 15 bytes. {DSI_WR_DATA, 0xFFFFFFD8}, {DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFF}, {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xBD15}, + {DSI_WR_DATA, 0x00BD15}, // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x0BD. {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x6D915}, + {DSI_WR_DATA, 0x06D915}, // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x6D9. {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0xB9}, + {DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. + {DSI_WR_DATA, 0x000000B9}, // Disable extension cmd. {DSI_TRIGGER, DSI_TRIGGER_HOST} }; -//DSI config. -static const cfg_op_t _display_config_5[21] = { +//DSI packet config. +static const cfg_op_t _display_dsi_packet_config[21] = { {DSI_PAD_CONTROL_1, 0}, {DSI_PHY_TIMING_0, 0x6070601}, {DSI_PHY_TIMING_1, 0x40A0E05}, @@ -264,15 +256,8 @@ static const cfg_op_t _display_config_5[21] = { {DSI_HOST_CONTROL, 0}, }; -//Clock config. -static const cfg_op_t _display_config_6[3] = { - {0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC -}; - -//DSI config. -static const cfg_op_t _display_config_7[10] = { +//DSI mode config. +static const cfg_op_t _display_dsi_mode_config[10] = { {DSI_TRIGGER, 0}, {DSI_CONTROL, 0}, {DSI_SOL_DELAY, 6}, @@ -286,17 +271,17 @@ static const cfg_op_t _display_config_7[10] = { }; //MIPI CAL config. -static const cfg_op_t _display_config_8[6] = { - {0x18, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2 - {0x02, 0xF3F10000}, // MIPI_CAL_CIL_MIPI_CAL_STATUS - {0x16, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG0 - {0x18, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2 - {0x18, 0x10010}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2 - {0x17, 0x300} // MIPI_CAL_MIPI_BIAS_PAD_CFG1 +static const cfg_op_t _display_mipi_pad_cal_config[6] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, + {MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG0, 0}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0x300} }; //DSI config. -static const cfg_op_t _display_config_9[4] = { +static const cfg_op_t _display_dsi_pad_cal_config[4] = { {DSI_PAD_CONTROL_1, 0}, {DSI_PAD_CONTROL_2, 0}, {DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, @@ -304,27 +289,27 @@ static const cfg_op_t _display_config_9[4] = { }; //MIPI CAL config. -static const cfg_op_t _display_config_10[16] = { - {0x0E, 0x200200}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG - {0x0F, 0x200200}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG - {0x19, 0x200002}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 - {0x1A, 0x200002}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 - {0x05, 0}, // MIPI_CAL_CILA_MIPI_CAL_CONFIG - {0x06, 0}, // MIPI_CAL_CILB_MIPI_CAL_CONFIG - {0x07, 0}, // MIPI_CAL_CILC_MIPI_CAL_CONFIG - {0x08, 0}, // MIPI_CAL_CILD_MIPI_CAL_CONFIG - {0x09, 0}, // MIPI_CAL_CILE_MIPI_CAL_CONFIG - {0x0A, 0}, // MIPI_CAL_CILF_MIPI_CAL_CONFIG - {0x10, 0}, // MIPI_CAL_DSIC_MIPI_CAL_CONFIG - {0x11, 0}, // MIPI_CAL_DSID_MIPI_CAL_CONFIG - {0x1A, 0}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 - {0x1C, 0}, // MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 - {0x1D, 0}, // MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 - {0, 0x2A000001} // MIPI_CAL_DSIA_MIPI_CAL_CONFIG +static const cfg_op_t _display_mipi_apply_dsi_cal_config[16] = { + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILD_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILE_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILF_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001} }; //Display A config. -static const cfg_op_t _display_config_11[113] = { +static const cfg_op_t _display_video_disp_controller_enable_config[113] = { {DC_CMD_STATE_ACCESS, 0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, @@ -449,7 +434,7 @@ static const cfg_op_t _display_config_11[113] = { }; ////Display A config. -static const cfg_op_t _display_config_12[17] = { +static const cfg_op_t _display_video_disp_controller_disable_config[17] = { {DC_DISP_FRONT_PORCH, 0xA0088}, {DC_CMD_INT_MASK, 0}, {DC_CMD_STATE_ACCESS, 0}, @@ -470,7 +455,7 @@ static const cfg_op_t _display_config_12[17] = { }; //DSI config. -static const cfg_op_t _display_config_13[16] = { +static const cfg_op_t _display_dsi_timing_deinit_config[16] = { {DSI_POWER_CONTROL, 0}, {DSI_PAD_CONTROL_1, 0}, {DSI_PHY_TIMING_0, 0x6070601}, @@ -490,11 +475,11 @@ static const cfg_op_t _display_config_13[16] = { }; //DSI config (if ver == 0x10). -static const cfg_op_t _display_config_14[22] = { - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0x9483FFB9}, +static const cfg_op_t _display_deinit_config_jdi[22] = { + {DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. + {DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94). {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2139}, + {DSI_WR_DATA, 0x2139}, // MIPI_DSI_DCS_LONG_WRITE: 33 bytes. {DSI_WR_DATA, 0x191919D5}, {DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19191919}, @@ -505,60 +490,60 @@ static const cfg_op_t _display_config_14[22] = { {DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19}, {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xB39}, - {DSI_WR_DATA, 0x4F0F41B1}, + {DSI_WR_DATA, 0xB39}, // MIPI_DSI_DCS_LONG_WRITE: 11 bytes. + {DSI_WR_DATA, 0x4F0F41B1}, // Set Power control. {DSI_WR_DATA, 0xF179A433}, - {DSI_WR_DATA, 0x2D81}, + {DSI_WR_DATA, 0x002D81}, {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0xB9}, + {DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. + {DSI_WR_DATA, 0x000000B9}, // Disable extension cmd. {DSI_TRIGGER, DSI_TRIGGER_HOST} }; //Display A config. static const cfg_op_t cfg_display_one_color[8] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display. + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} // Continuous display. }; //Display A config. static const cfg_op_t cfg_display_framebuffer[32] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 {DC_WIN_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0}, {DC_WIN_POSITION, 0}, //(0,0) {DC_WIN_H_INITIAL_DDA, 0}, {DC_WIN_V_INITIAL_DDA, 0}, - {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. - {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, - {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. - {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. - {DC_WIN_BUFFER_CONTROL, 0}, - {DC_WINBUF_SURFACE_KIND, 0}, //Regular surface. + {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, + {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x + {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, + {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST}, + {DC_WINBUF_SURFACE_KIND, PITCH}, {DC_WINBUF_START_ADDR, IPL_FB_ADDRESS}, // Framebuffer address. {DC_WINBUF_ADDR_H_OFFSET, 0}, {DC_WINBUF_ADDR_V_OFFSET, 0}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD. - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display. - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update. - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request. + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {DC_WIN_WIN_OPTIONS, WIN_ENABLE}, // Enable window AD. + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display. + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} }; diff --git a/nyx/nyx_gui/frontend/gui.c b/nyx/nyx_gui/frontend/gui.c index d8ee007..dc79e75 100644 --- a/nyx/nyx_gui/frontend/gui.c +++ b/nyx/nyx_gui/frontend/gui.c @@ -94,7 +94,7 @@ static gui_status_bar_ctx status_bar; static void _nyx_disp_init() { display_backlight_brightness(0, 1000); - display_init_framebuffer(); + display_init_framebuffer_pitch(); display_backlight_brightness(h_cfg.backlight - 20, 1000); } diff --git a/nyx/nyx_gui/gfx/di.c b/nyx/nyx_gui/gfx/di.c index f7ccc4d..20a4adb 100644 --- a/nyx/nyx_gui/gfx/di.c +++ b/nyx/nyx_gui/gfx/di.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2019 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -60,16 +60,16 @@ void display_init() CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000; // Set enable clock DSIA_LP. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10; // Set PLLP_OUT and div 6 (68MHz). - // Disable deap power down. + // Disable deep power down. PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000; PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000; // Config LCD and Backlight pins. - PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE; - PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE; - PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; - PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE; - PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE; + PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN + PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE; // PULL_DOWN + PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; // PULL_DOWN | 1 + PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN + PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE; // PULL_DOWN // Set Backlight +-5V pins mode and direction gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO); @@ -87,14 +87,18 @@ void display_init() gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Enable Backlight EN. // Power up supply regulator for display interface. - MIPI_CAL(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0; + MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0; - // Set DISP1 clock source and parrent clock. - exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4); + // Set DISP1 clock source and parent clock. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1) = 0x40000000; // PLLD_OUT. + u32 plld_div = (3 << 20) | (20 << 11) | 1; // DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 96 MHz. + CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div; + CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20; // PLLD_SETUP. + CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2D0AAA; // PLLD_ENABLE_CLK. // Setup display communication interfaces. - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94); - exec_cfg((u32 *)DSI_BASE, _display_config_3, 61); + exec_cfg((u32 *)DISPLAY_A_BASE, _display_dc_setup_win_config, 94); + exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config, 61); usleep(10000); // Enable Backlight Reset. @@ -118,7 +122,7 @@ void display_init() _display_ver = DSI(_DSIREG(DSI_RD_DATA)); if (_display_ver == 0x10) - exec_cfg((u32 *)DSI_BASE, _display_config_4, 43); + exec_cfg((u32 *)DSI_BASE, _display_init_config_jdi, 43); DSI(_DSIREG(DSI_WR_DATA)) = 0x1105; // MIPI_DCS_EXIT_SLEEP_MODE DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; @@ -131,22 +135,25 @@ void display_init() usleep(20000); // Configure PLLD for DISP1. - exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3); + plld_div = (1 << 20) | (24 << 11) | 1; // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 460.8 MHz. + CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div; + CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20; + CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00; // Use new PLLD_SDM_DIN. // Finalize DSI configuration. - exec_cfg((u32 *)DSI_BASE, _display_config_5, 21); - DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; - exec_cfg((u32 *)DSI_BASE, _display_config_7, 10); + exec_cfg((u32 *)DSI_BASE, _display_dsi_packet_config, 21); + DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; // PCD1 | div3. + exec_cfg((u32 *)DSI_BASE, _display_dsi_mode_config, 10); usleep(10000); // Calibrate display communication pads. - exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6); - exec_cfg((u32 *)DSI_BASE, _display_config_9, 4); - exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16); + exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_pad_cal_config, 6); + exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config, 4); + exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_apply_dsi_cal_config, 16); usleep(10000); // Enable video display controller. - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113); + exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_enable_config, 113); } void display_backlight_pwm_init() @@ -197,20 +204,20 @@ void display_end() { display_backlight_brightness(0, 1000); - DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 1; + DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE; DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX; DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; // Disable host cmd packet. // De-initialize video controller. - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17); - exec_cfg((u32 *)DSI_BASE, _display_config_13, 16); + exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_disable_config, 17); + exec_cfg((u32 *)DSI_BASE, _display_dsi_timing_deinit_config, 16); usleep(10000); // De-initialize display panel. if (_display_ver == 0x10) - exec_cfg((u32 *)DSI_BASE, _display_config_14, 22); + exec_cfg((u32 *)DSI_BASE, _display_deinit_config_jdi, 22); DSI(_DSIREG(DSI_WR_DATA)) = 0x1005; // MIPI_DCS_ENTER_SLEEP_MODE DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; @@ -254,26 +261,24 @@ void display_color_screen(u32 color) DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0; DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ; - usleep(35000); display_backlight(true); } -u32 *display_init_framebuffer() +u32 *display_init_framebuffer_pitch() { // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720). - exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer, 32); - - usleep(35000); - - return (u32 *)NYX_FB_ADDRESS; -} - -u32 *display_init_framebuffer2() -{ - // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720). - exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer2, 32); + exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch, 32); + usleep(35000); + + return (u32 *)NYX_FB_ADDRESS; +} + +u32 *display_init_framebuffer_block() +{ + // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720). + exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_block, 32); usleep(35000); diff --git a/nyx/nyx_gui/gfx/di.h b/nyx/nyx_gui/gfx/di.h index 10c1e85..34b2b85 100644 --- a/nyx/nyx_gui/gfx/di.h +++ b/nyx/nyx_gui/gfx/di.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2019 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -187,6 +187,13 @@ #define CSC_ENABLE (1 << 18) #define WIN_ENABLE (1 << 30) +#define DC_WIN_BUFFER_CONTROL 0x702 +#define BUFFER_CONTROL_HOST 0 +#define BUFFER_CONTROL_VI 1 +#define BUFFER_CONTROL_EPP 2 +#define BUFFER_CONTROL_MPEGE 3 +#define BUFFER_CONTROL_SB2D 4 + #define DC_WIN_COLOR_DEPTH 0x703 #define WIN_COLOR_DEPTH_P1 0x0 #define WIN_COLOR_DEPTH_P2 0x1 @@ -336,6 +343,7 @@ #define DSI_PAD_CONTROL_CD 0x4C #define DSI_VIDEO_MODE_CONTROL 0x4E +#define DSI_CMD_PKT_VID_ENABLE 1 #define DSI_PAD_CONTROL_1 0x4F #define DSI_PAD_CONTROL_2 0x50 @@ -349,7 +357,39 @@ #define DSI_PAD_CONTROL_4 0x52 #define DSI_INIT_SEQ_DATA_15 0x5F -#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60 +/*! MIPI registers. */ +#define MIPI_CAL_MIPI_CAL_CTRL (0x00 / 0x4) +#define MIPI_CAL_CIL_MIPI_CAL_STATUS (0x08 / 0x4) +#define MIPI_CAL_CILA_MIPI_CAL_CONFIG (0x14 / 0x4) +#define MIPI_CAL_CILB_MIPI_CAL_CONFIG (0x18 / 0x4) +#define MIPI_CAL_CILC_MIPI_CAL_CONFIG (0x1C / 0x4) +#define MIPI_CAL_CILD_MIPI_CAL_CONFIG (0x20 / 0x4) +#define MIPI_CAL_CILE_MIPI_CAL_CONFIG (0x24 / 0x4) +#define MIPI_CAL_CILF_MIPI_CAL_CONFIG (0x28 / 0x4) +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG (0x38 / 0x4) +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG (0x3C / 0x4) +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG (0x40 / 0x4) +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG (0x44 / 0x4) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 (0x58 / 0x4) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 (0x5C / 0x4) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 (0x60 / 0x4) +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 (0x64 / 0x4) +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 (0x68 / 0x4) +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 (0x70 / 0x4) +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x74 / 0x4) + +/*! MIPI CMDs. */ +#define MIPI_DSI_DCS_SHORT_WRITE 0x05 +#define MIPI_DSI_DCS_READ 0x06 +#define MIPI_DSI_DCS_SHORT_WRITE_PARAM 0x15 +#define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37 +#define MIPI_DSI_DCS_LONG_WRITE 0x39 + +/*! MIPI DCS CMDs. */ +#define MIPI_DCS_GET_DISPLAY_ID 0x04 +#define MIPI_DCS_ENTER_SLEEP_MODE 0x10 +#define MIPI_DCS_EXIT_SLEEP_MODE 0x11 +#define MIPI_DCS_SET_DISPLAY_ON 0x29 void display_init(); void display_backlight_pwm_init(); @@ -363,7 +403,7 @@ void display_backlight(bool enable); void display_backlight_brightness(u32 brightness, u32 step_delay); /*! Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */ -u32 *display_init_framebuffer(); -u32 *display_init_framebuffer2(); +u32 *display_init_framebuffer_pitch(); +u32 *display_init_framebuffer_block(); #endif diff --git a/nyx/nyx_gui/gfx/di.inl b/nyx/nyx_gui/gfx/di.inl index 7ec0115..8b3010a 100644 --- a/nyx/nyx_gui/gfx/di.inl +++ b/nyx/nyx_gui/gfx/di.inl @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert -* Copyright (c) 2018 CTCaer +* Copyright (c) 2018-2019 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,16 +15,8 @@ * along with this program. If not, see . */ -//Clock config. -static const cfg_op_t _display_config_1[4] = { - {0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 - {0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC -}; - //Display A config. -static const cfg_op_t _display_config_2[94] = { +static const cfg_op_t _display_dc_setup_win_config[94] = { {DC_CMD_STATE_ACCESS, 0}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, @@ -128,7 +120,7 @@ static const cfg_op_t _display_config_2[94] = { }; //DSI Init config. -static const cfg_op_t _display_config_3[61] = { +static const cfg_op_t _display_dsi_init_config[61] = { {DSI_WR_DATA, 0}, {DSI_INT_ENABLE, 0}, {DSI_INT_STATUS, 0}, @@ -192,14 +184,14 @@ static const cfg_op_t _display_config_3[61] = { {DSI_INIT_SEQ_CONTROL, 0} }; -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_4[43] = { - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0x9483FFB9}, +//DSI panel config. +static const cfg_op_t _display_init_config_jdi[43] = { + {DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. + {DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94). {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xBD15}, + {DSI_WR_DATA, 0x00BD15}, // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x0BD. {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x1939}, + {DSI_WR_DATA, 0x1939}, // MIPI_DSI_DCS_LONG_WRITE: 25 bytes. {DSI_WR_DATA, 0xAAAAAAD8}, {DSI_WR_DATA, 0xAAAAAAEB}, {DSI_WR_DATA, 0xAAEBAAAA}, @@ -208,9 +200,9 @@ static const cfg_op_t _display_config_4[43] = { {DSI_WR_DATA, 0xAAEBAAAA}, {DSI_WR_DATA, 0xAA}, {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x1BD15}, + {DSI_WR_DATA, 0x01BD15}, // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x1BD. {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2739}, + {DSI_WR_DATA, 0x2739}, // MIPI_DSI_DCS_LONG_WRITE: 39 bytes. {DSI_WR_DATA, 0xFFFFFFD8}, {DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF}, @@ -222,25 +214,25 @@ static const cfg_op_t _display_config_4[43] = { {DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFF}, {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2BD15}, + {DSI_WR_DATA, 0x02BD15}, // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x2BD. {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xF39}, + {DSI_WR_DATA, 0xF39}, // MIPI_DSI_DCS_LONG_WRITE: 15 bytes. {DSI_WR_DATA, 0xFFFFFFD8}, {DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFFFF}, {DSI_WR_DATA, 0xFFFFFF}, {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xBD15}, + {DSI_WR_DATA, 0x00BD15}, // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x0BD. {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x6D915}, + {DSI_WR_DATA, 0x06D915}, // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x6D9. {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0xB9}, + {DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. + {DSI_WR_DATA, 0x000000B9}, // Disable extension cmd. {DSI_TRIGGER, DSI_TRIGGER_HOST} }; -//DSI config. -static const cfg_op_t _display_config_5[21] = { +//DSI packet config. +static const cfg_op_t _display_dsi_packet_config[21] = { {DSI_PAD_CONTROL_1, 0}, {DSI_PHY_TIMING_0, 0x6070601}, {DSI_PHY_TIMING_1, 0x40A0E05}, @@ -264,15 +256,8 @@ static const cfg_op_t _display_config_5[21] = { {DSI_HOST_CONTROL, 0}, }; -//Clock config. -static const cfg_op_t _display_config_6[3] = { - {0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC -}; - -//DSI config. -static const cfg_op_t _display_config_7[10] = { +//DSI mode config. +static const cfg_op_t _display_dsi_mode_config[10] = { {DSI_TRIGGER, 0}, {DSI_CONTROL, 0}, {DSI_SOL_DELAY, 6}, @@ -286,17 +271,17 @@ static const cfg_op_t _display_config_7[10] = { }; //MIPI CAL config. -static const cfg_op_t _display_config_8[6] = { - {0x18, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2 - {0x02, 0xF3F10000}, // MIPI_CAL_CIL_MIPI_CAL_STATUS - {0x16, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG0 - {0x18, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2 - {0x18, 0x10010}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2 - {0x17, 0x300} // MIPI_CAL_MIPI_BIAS_PAD_CFG1 +static const cfg_op_t _display_mipi_pad_cal_config[6] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, + {MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG0, 0}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0x300} }; //DSI config. -static const cfg_op_t _display_config_9[4] = { +static const cfg_op_t _display_dsi_pad_cal_config[4] = { {DSI_PAD_CONTROL_1, 0}, {DSI_PAD_CONTROL_2, 0}, {DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, @@ -304,27 +289,27 @@ static const cfg_op_t _display_config_9[4] = { }; //MIPI CAL config. -static const cfg_op_t _display_config_10[16] = { - {0x0E, 0x200200}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG - {0x0F, 0x200200}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG - {0x19, 0x200002}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 - {0x1A, 0x200002}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 - {0x05, 0}, // MIPI_CAL_CILA_MIPI_CAL_CONFIG - {0x06, 0}, // MIPI_CAL_CILB_MIPI_CAL_CONFIG - {0x07, 0}, // MIPI_CAL_CILC_MIPI_CAL_CONFIG - {0x08, 0}, // MIPI_CAL_CILD_MIPI_CAL_CONFIG - {0x09, 0}, // MIPI_CAL_CILE_MIPI_CAL_CONFIG - {0x0A, 0}, // MIPI_CAL_CILF_MIPI_CAL_CONFIG - {0x10, 0}, // MIPI_CAL_DSIC_MIPI_CAL_CONFIG - {0x11, 0}, // MIPI_CAL_DSID_MIPI_CAL_CONFIG - {0x1A, 0}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 - {0x1C, 0}, // MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 - {0x1D, 0}, // MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 - {0, 0x2A000001} // MIPI_CAL_DSIA_MIPI_CAL_CONFIG +static const cfg_op_t _display_mipi_apply_dsi_cal_config[16] = { + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILD_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILE_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILF_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001} }; //Display A config. -static const cfg_op_t _display_config_11[113] = { +static const cfg_op_t _display_video_disp_controller_enable_config[113] = { {DC_CMD_STATE_ACCESS, 0}, {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, @@ -449,7 +434,7 @@ static const cfg_op_t _display_config_11[113] = { }; ////Display A config. -static const cfg_op_t _display_config_12[17] = { +static const cfg_op_t _display_video_disp_controller_disable_config[17] = { {DC_DISP_FRONT_PORCH, 0xA0088}, {DC_CMD_INT_MASK, 0}, {DC_CMD_STATE_ACCESS, 0}, @@ -470,7 +455,7 @@ static const cfg_op_t _display_config_12[17] = { }; //DSI config. -static const cfg_op_t _display_config_13[16] = { +static const cfg_op_t _display_dsi_timing_deinit_config[16] = { {DSI_POWER_CONTROL, 0}, {DSI_PAD_CONTROL_1, 0}, {DSI_PHY_TIMING_0, 0x6070601}, @@ -490,11 +475,11 @@ static const cfg_op_t _display_config_13[16] = { }; //DSI config (if ver == 0x10). -static const cfg_op_t _display_config_14[22] = { - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0x9483FFB9}, +static const cfg_op_t _display_deinit_config_jdi[22] = { + {DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. + {DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94). {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2139}, + {DSI_WR_DATA, 0x2139}, // MIPI_DSI_DCS_LONG_WRITE: 33 bytes. {DSI_WR_DATA, 0x191919D5}, {DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19191919}, @@ -505,95 +490,96 @@ static const cfg_op_t _display_config_14[22] = { {DSI_WR_DATA, 0x19191919}, {DSI_WR_DATA, 0x19}, {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xB39}, - {DSI_WR_DATA, 0x4F0F41B1}, + {DSI_WR_DATA, 0xB39}, // MIPI_DSI_DCS_LONG_WRITE: 11 bytes. + {DSI_WR_DATA, 0x4F0F41B1}, // Set Power control. {DSI_WR_DATA, 0xF179A433}, - {DSI_WR_DATA, 0x2D81}, + {DSI_WR_DATA, 0x002D81}, {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0xB9}, + {DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. + {DSI_WR_DATA, 0x000000B9}, // Disable extension cmd. {DSI_TRIGGER, DSI_TRIGGER_HOST} }; //Display A config. static const cfg_op_t cfg_display_one_color[8] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display. + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} // Continuous display. }; -//Display A config. -static const cfg_op_t cfg_display_framebuffer[32] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. +//Display A config pitch. +static const cfg_op_t cfg_display_framebuffer_pitch[32] = { + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8. {DC_WIN_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0}, {DC_WIN_POSITION, 0}, //(0,0) {DC_WIN_H_INITIAL_DDA, 0}, {DC_WIN_V_INITIAL_DDA, 0}, - {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. - {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, - {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. - {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. - {DC_WIN_BUFFER_CONTROL, 0}, - {DC_WINBUF_SURFACE_KIND, 0}, //Regular surface. + {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, + {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. + {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, + {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST}, + {DC_WINBUF_SURFACE_KIND, PITCH}, {DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address. - {DC_WINBUF_ADDR_H_OFFSET, 0}, //Linear: 0x383FFC, Block: 0x3813FC - {DC_WINBUF_ADDR_V_OFFSET, 1279}, //Linear: 1279, Block: 0 + {DC_WINBUF_ADDR_H_OFFSET, 0}, // Linear: 0x383FFC, Block: 0x3813FC. + {DC_WINBUF_ADDR_V_OFFSET, 1279}, // Linear: 1279, Block: 0. {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_WIN_OPTIONS, WIN_ENABLE | V_DIRECTION}, // Enable window AD. - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display. - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update. - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request. + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display. + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} }; -static const cfg_op_t cfg_display_framebuffer2[32] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. +//Display A config block linear. +static const cfg_op_t cfg_display_framebuffer_block[32] = { + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8. {DC_WIN_WIN_OPTIONS, 0}, {DC_WIN_WIN_OPTIONS, 0}, {DC_WIN_POSITION, 0}, //(0,0) {DC_WIN_H_INITIAL_DDA, 0}, {DC_WIN_V_INITIAL_DDA, 0}, - {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. - {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, - {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. - {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(1280 * 2) | LINE_STRIDE(1280 * 4)}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. - {DC_WIN_BUFFER_CONTROL, 0}, - {DC_WINBUF_SURFACE_KIND, BLOCK_HEIGHT(4) | BLOCK}, //Regular surface. + {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, + {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. + {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, + {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(1280 * 2) | LINE_STRIDE(1280 * 4)}, //720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST}, + {DC_WINBUF_SURFACE_KIND, BLOCK_HEIGHT(4) | BLOCK}, {DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address. - {DC_WINBUF_ADDR_H_OFFSET, 0x3813FC}, //Linear: 0x383FFC, Block: 0x3813FC - {DC_WINBUF_ADDR_V_OFFSET, 0}, //Linear: 1279, Block: 0 + {DC_WINBUF_ADDR_H_OFFSET, 0x3813FC}, // Linear: 0x383FFC, Block: 0x3813FC. + {DC_WINBUF_ADDR_V_OFFSET, 0}, // Linear: 1279, Block: 0. {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, WIN_ENABLE | SCAN_COLUMN | H_DIRECTION}, //Enable window AD. | SCAN_COLUMN | H_DIRECTION - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display. - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update. - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request. + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {DC_WIN_WIN_OPTIONS, WIN_ENABLE | SCAN_COLUMN | H_DIRECTION}, // Enable window AD. | SCAN_COLUMN | H_DIRECTION. + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display. + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} };