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https://github.com/CTCaer/hekate
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l4t: disable AHB aperture and pllc war
We don't need AHB aperture after that point and new deinit fixes the pllc init issue on L4T boot.
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080e3e2aa7
commit
361aaf8629
1 changed files with 3 additions and 11 deletions
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@ -719,9 +719,6 @@ static void _l4t_mc_config_carveout(bool t210b01)
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static void _l4t_late_hw_config(bool t210b01)
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static void _l4t_late_hw_config(bool t210b01)
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{
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{
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// Turn on PLLC to default OUT0 frequency to mitigate kernel broken init.
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clock_enable_pllc(53); // VCO/OUT0: 508.8 MHz. (VCO is half.)
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// Reset System Counters.
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// Reset System Counters.
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for (u32 i = 0; i < SYSCTR0_COUNTERS; i += sizeof(u32))
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for (u32 i = 0; i < SYSCTR0_COUNTERS; i += sizeof(u32))
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SYSCTR0(SYSCTR0_COUNTERS_BASE + i) = 0;
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SYSCTR0(SYSCTR0_COUNTERS_BASE + i) = 0;
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@ -1045,6 +1042,9 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
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// Done loading bootloaders/firmware.
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// Done loading bootloaders/firmware.
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sd_end();
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sd_end();
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// We don't need AHB aperture open.
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mc_disable_ahb_redirect();
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// Enable debug port.
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// Enable debug port.
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if (ctxt.serial_port)
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if (ctxt.serial_port)
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{
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{
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@ -1205,11 +1205,3 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
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while (true)
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while (true)
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bpmp_halt();
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bpmp_halt();
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}
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}
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// t210 t210b01 hoag/aula
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// pp1 b0000001 b0000001 b0000001 pcie_port1_lane_map
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// pp0 b0010000 b0001000 b0000000 -- pcie_port0_lane_map
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// pci b0011111 b0001101 b0001101 - pcie_lane_map
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// usb b1100000 b0110010 b0110010 - usb_lane_map
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// rpd b0000011 b0000011 b0000011 root_port_mask_dev
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// rpp b0000010 b0000010 b0000010 root_port_mask_prod
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