From 32e58d2bb3584591944bffba549122cf25b8c6bf Mon Sep 17 00:00:00 2001 From: CTCaer Date: Fri, 17 Jul 2020 18:08:27 +0300 Subject: [PATCH] hw init: Cosmetic refactoring --- bdk/soc/hw_init.c | 45 +++++++++++++------ bdk/soc/hw_init.h | 4 +- bdk/utils/util.c | 6 +-- bootloader/hos/sept.c | 2 +- bootloader/main.c | 6 +-- nyx/nyx_gui/frontend/gui.c | 4 +- .../frontend/gui_tools_partition_manager.c | 2 +- nyx/nyx_gui/hos/sept.c | 2 +- nyx/nyx_gui/nyx.c | 4 +- 9 files changed, 46 insertions(+), 29 deletions(-) diff --git a/bdk/soc/hw_init.c b/bdk/soc/hw_init.c index 2e0f78e..6c92251 100644 --- a/bdk/soc/hw_init.c +++ b/bdk/soc/hw_init.c @@ -73,14 +73,17 @@ void _config_oscillators() PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz) - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set SCLK div to 1. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set clk source to Run and PLLP_OUT2 (204MHz). + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set BPMP/SCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set BPMP/SCLK source to Run and PLLP_OUT2 (204MHz). CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1. CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3. } void _config_gpios() { + // Clamp inputs when tristated. + APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0; + PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0; PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0; @@ -122,7 +125,7 @@ void _config_gpios() void _config_pmc_scratch() { - PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option. + PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option. PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT; } @@ -222,11 +225,11 @@ void _mbist_workaround() CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE) = 0; // Set child clock sources. - CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF; // Disable PLLD and set reference clock and csi clock. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF; // Set SOR1 to automatic muxing of safe clock (24MHz) or SOR1 clk switch. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. + CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF; // Disable PLLD and set reference clock and csi clock. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF; // Set SOR1 to automatic muxing of safe clock (24MHz) or SOR1 clk switch. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. } void _config_se_brom() @@ -317,7 +320,7 @@ void _config_regulators() MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL); } -void config_hw() +void hw_init() { // Bootrom stuff we skipped by going through rcm. _config_se_brom(); @@ -325,19 +328,25 @@ void config_hw() SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F; // Unset APB2JTAG_OVERRIDE_EN and OBS_OVERRIDE_EN. PMC(APBDEV_PMC_SCRATCH49) = PMC(APBDEV_PMC_SCRATCH49) & 0xFFFFFFFC; + // Perform Memory Built-In Self Test WAR if T210. _mbist_workaround(); + + // Enable Security Engine clock. clock_enable_se(); - // Enable fuse clock. + // Enable Fuse clock. clock_enable_fuse(true); - // Disable fuse programming. + // Disable Fuse programming. fuse_disable_program(); + // Enable clocks to Memory controllers and disable AHB redirect. mc_enable(); + // Initialize counters, CLKM, BPMP and other clocks based on 38.4MHz oscillator. _config_oscillators(); - APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0; + + // Initialize pin configuration. _config_gpios(); #ifdef DEBUG_UART_PORT @@ -345,34 +354,42 @@ void config_hw() uart_init(DEBUG_UART_PORT, 115200); #endif + // Enable Dynamic Voltage and Frequency Scaling device clock. clock_enable_cl_dvfs(); + // Enable clocks to I2C1 and I2CPWR. clock_enable_i2c(I2C_1); clock_enable_i2c(I2C_5); + // Enable clock to TZRAM. clock_enable_tzram(); + // Initialize I2C5, mandatory for PMIC comms. i2c_init(I2C_1); i2c_init(I2C_5); // Enable charger in case it's disabled. bq24193_enable_charger(); + // Initialize various regulators based on Erista/Mariko platform. _config_regulators(); _config_pmc_scratch(); // Missing from 4.x+ - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz). + // Set BPMP/SCLK to PLLP_OUT (408MHz). + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; + + // Initialize External memory controller and configure DRAM parameters. sdram_init(); bpmp_mmu_enable(); - // Clear flags from PMC_SCRATCH0 + // L4T: Clear flags from PMC_SCRATCH0. PMC(APBDEV_PMC_SCRATCH0) &= ~PMC_SCRATCH0_MODE_PAYLOAD; } -void reconfig_hw_workaround(bool extra_reconfig, u32 magic) +void hw_reinit_workaround(bool extra_reconfig, u32 magic) { // Disable BPMP max clock. bpmp_clk_rate_set(BPMP_CLK_NORMAL); diff --git a/bdk/soc/hw_init.h b/bdk/soc/hw_init.h index d19f271..9cbd917 100644 --- a/bdk/soc/hw_init.h +++ b/bdk/soc/hw_init.h @@ -20,7 +20,7 @@ #include -void config_hw(); -void reconfig_hw_workaround(bool extra_reconfig, u32 magic); +void hw_init(); +void hw_reinit_workaround(bool extra_reconfig, u32 magic); #endif diff --git a/bdk/utils/util.c b/bdk/utils/util.c index dd10781..7cdf09d 100644 --- a/bdk/utils/util.c +++ b/bdk/utils/util.c @@ -135,7 +135,7 @@ void panic(u32 val) void reboot_normal() { sd_end(); - reconfig_hw_workaround(false, 0); + hw_reinit_workaround(false, 0); panic(0x21); // Bypass fuse programming in package1. } @@ -143,7 +143,7 @@ void reboot_normal() void reboot_rcm() { sd_end(); - reconfig_hw_workaround(false, 0); + hw_reinit_workaround(false, 0); PMC(APBDEV_PMC_SCRATCH0) = PMC_SCRATCH0_MODE_RCM; PMC(APBDEV_PMC_CNTRL) |= PMC_CNTRL_MAIN_RST; @@ -155,7 +155,7 @@ void reboot_rcm() void power_off() { sd_end(); - reconfig_hw_workaround(false, 0); + hw_reinit_workaround(false, 0); // Stop the alarm, in case we injected and powered off too fast. max77620_rtc_stop_alarm(); diff --git a/bootloader/hos/sept.c b/bootloader/hos/sept.c index 3ee6dd3..a7ed898 100644 --- a/bootloader/hos/sept.c +++ b/bootloader/hos/sept.c @@ -243,7 +243,7 @@ int reboot_to_sept(const u8 *tsec_fw, u32 kb, ini_sec_t *cfg_sec) PMC(APBDEV_PMC_SCRATCH33) = SEPT_PRI_ADDR; PMC(APBDEV_PMC_SCRATCH40) = 0x6000F208; - reconfig_hw_workaround(false, 0); + hw_reinit_workaround(false, 0); (*sept)(); diff --git a/bootloader/main.c b/bootloader/main.c index 560c78f..dcf491d 100644 --- a/bootloader/main.c +++ b/bootloader/main.c @@ -255,12 +255,12 @@ int launch_payload(char *path, bool update) else reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, ALIGN(size, 0x10)); - reconfig_hw_workaround(false, byte_swap_32(*(u32 *)(buf + size - sizeof(u32)))); + hw_reinit_workaround(false, byte_swap_32(*(u32 *)(buf + size - sizeof(u32)))); } else { reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, 0x7000); - reconfig_hw_workaround(true, 0); + hw_reinit_workaround(true, 0); } // Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. @@ -1459,7 +1459,7 @@ extern void pivot_stack(u32 stack_top); void ipl_main() { // Do initial HW configuration. This is compatible with consecutive reruns without a reset. - config_hw(); + hw_init(); // Pivot the stack so we have enough space. pivot_stack(IPL_STACK_TOP); diff --git a/nyx/nyx_gui/frontend/gui.c b/nyx/nyx_gui/frontend/gui.c index 6c2a0a9..28df37c 100644 --- a/nyx/nyx_gui/frontend/gui.c +++ b/nyx/nyx_gui/frontend/gui.c @@ -862,7 +862,7 @@ static void _launch_hos(u8 autoboot, u8 autoboot_list) sd_end(); - reconfig_hw_workaround(false, 0); + hw_reinit_workaround(false, 0); // Mitigate L4T Joy-Con driver issue. if ((autoboot & 0x80) && h_cfg.bootwait < 2) @@ -882,7 +882,7 @@ void reload_nyx() sd_end(); - reconfig_hw_workaround(false, 0); + hw_reinit_workaround(false, 0); // Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. sdmmc_storage_init_wait_sd(); diff --git a/nyx/nyx_gui/frontend/gui_tools_partition_manager.c b/nyx/nyx_gui/frontend/gui_tools_partition_manager.c index 45881c5..ee6adde 100644 --- a/nyx/nyx_gui/frontend/gui_tools_partition_manager.c +++ b/nyx/nyx_gui/frontend/gui_tools_partition_manager.c @@ -867,7 +867,7 @@ static lv_res_t _action_reboot_twrp(lv_obj_t * btns, const char * txt) sd_end(); - reconfig_hw_workaround(false, 0); + hw_reinit_workaround(false, 0); (*main_ptr)(); } diff --git a/nyx/nyx_gui/hos/sept.c b/nyx/nyx_gui/hos/sept.c index e3b25d8..460ed32 100644 --- a/nyx/nyx_gui/hos/sept.c +++ b/nyx/nyx_gui/hos/sept.c @@ -226,7 +226,7 @@ int reboot_to_sept(const u8 *tsec_fw, u32 kb) PMC(APBDEV_PMC_SCRATCH33) = SEPT_PRI_ADDR; PMC(APBDEV_PMC_SCRATCH40) = 0x6000F208; - reconfig_hw_workaround(false, 0); + hw_reinit_workaround(false, 0); (*sept)(); diff --git a/nyx/nyx_gui/nyx.c b/nyx/nyx_gui/nyx.c index 6a9a842..7db06cf 100644 --- a/nyx/nyx_gui/nyx.c +++ b/nyx/nyx_gui/nyx.c @@ -185,12 +185,12 @@ lv_res_t launch_payload(lv_obj_t *list) if (size < 0x30000) { reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, ALIGN(size, 0x10)); - reconfig_hw_workaround(false, byte_swap_32(*(u32 *)(buf + size - sizeof(u32)))); + hw_reinit_workaround(false, byte_swap_32(*(u32 *)(buf + size - sizeof(u32)))); } else { reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, 0x7000); - reconfig_hw_workaround(true, 0); + hw_reinit_workaround(true, 0); } void (*ext_payload_ptr)() = (void *)EXT_PAYLOAD_ADDR;