diff --git a/bdk/mem/sdram.c b/bdk/mem/sdram.c index 2ef4c6d..2002375 100644 --- a/bdk/mem/sdram.c +++ b/bdk/mem/sdram.c @@ -54,7 +54,7 @@ static const u8 dram_encoding_t210b01[] = { /* 04 */ LPDDR4X_UNUSED, /* 05 */ LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, /* 06 */ LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, -/* 07 */ LPDDR4X_4GB_SAMSUNG_X1X2, +/* 07 */ LPDDR4X_UNUSED, /* 08 */ LPDDR4X_NO_PATCH, /* 09 */ LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ, /* 10 */ LPDDR4X_NO_PATCH, @@ -63,7 +63,7 @@ static const u8 dram_encoding_t210b01[] = { /* 13 */ LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ, /* 14 */ LPDDR4X_NO_PATCH, /* 15 */ LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE, -/* 16 */ LPDDR4X_4GB_SAMSUNG_Y, +/* 16 */ LPDDR4X_UNUSED, /* 17 */ LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL, /* 18 */ LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, /* 19 */ LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL, @@ -76,6 +76,12 @@ static const u8 dram_encoding_t210b01[] = { /* 26 */ LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF, /* 27 */ LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF, /* 28 */ LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, +/* 29 */ LPDDR4X_4GB_NEW0, +/* 30 */ LPDDR4X_4GB_NEW0, +/* 31 */ LPDDR4X_4GB_NEW0, +/* 32 */ LPDDR4X_4GB_NEW1, +/* 33 */ LPDDR4X_4GB_NEW1, +/* 34 */ LPDDR4X_4GB_NEW1, }; #include "sdram_config.inl" diff --git a/bdk/mem/sdram.h b/bdk/mem/sdram.h index f367628..23b6960 100644 --- a/bdk/mem/sdram.h +++ b/bdk/mem/sdram.h @@ -51,10 +51,8 @@ enum sdram_ids_erista LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH = 0, LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 1, LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT = 2, // WT:C. - LPDDR4_COPPER_4GB_SAMSUNG_K4F6E304HB_MGCH = 3, // Changed to Iowa Hynix 4GB 1Y-A. + LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH = 4, - LPDDR4_COPPER_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 5, // Changed to Hoag Hynix 4GB 1Y-A. - LPDDR4_COPPER_4GB_MICRON_MT53B512M32D2NP_062_WT = 6, // Changed to Aula Hynix 4GB 1Y-A. }; enum sdram_ids_mariko @@ -65,8 +63,6 @@ enum sdram_ids_mariko LPDDR4X_AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 6, // Replaced from Copper. Die-M. (1y-01). // LPDDR4X 3733Mbps. - LPDDR4X_IOWA_4GB_SAMSUNG_X1X2 = 7, - LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 8, // Die-M. LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 9, // Die-M. LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 10, // Die-M. @@ -78,8 +74,6 @@ enum sdram_ids_mariko LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE = 15, // 4266Mbps. Die-E. // LPDDR4X 4266Mbps. - LPDDR4X_IOWA_4GB_SAMSUNG_Y = 16, // (Y01). - LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 17, // Die-A. (1y-X03). LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 18, // Die-A. (1y-X03). LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 19, // Die-A. (1y-X03). @@ -96,6 +90,14 @@ enum sdram_ids_mariko LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 27, // 4266Mbps. Die-F. D9XRR. 10nm-class (1y-01). LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 28, // Die-A. + + LPDDR4X_UNK0_4GB_NEW0 = 29, + LPDDR4X_UNK1_4GB_NEW0 = 30, + LPDDR4X_UNK2_4GB_NEW0 = 31, + + LPDDR4X_UNK0_4GB_NEW1 = 32, + LPDDR4X_UNK1_4GB_NEW1 = 33, + LPDDR4X_UNK2_4GB_NEW1 = 34, }; enum sdram_codes_mariko @@ -106,15 +108,16 @@ enum sdram_codes_mariko // LPDDR4X_4GB_SAMSUNG_K4U6E3S4AM_MGCJ DRAM IDs: 08, 12. // LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLHR_NME DRAM IDs: 10, 14. - LPDDR4X_4GB_SAMSUNG_X1X2 = 1, // DRAM IDs: 07. - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 2, // DRAM IDs: 09, 13. - LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE = 3, // DRAM IDs: 11, 15. - LPDDR4X_4GB_SAMSUNG_Y = 4, // DRAM IDs: 16. - LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 5, // DRAM IDs: 17, 19, 24. - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 6, // DRAM IDs: 18, 23, 28. - LPDDR4X_4GB_SAMSUNG_1Z = 7, // DRAM IDs: 20, 21, 22. - LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF = 8, // DRAM IDs: 25, 26, 27. - LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 9, // DRAM IDs: 03, 05, 06. + LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 1, // DRAM IDs: 09, 13. + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE = 2, // DRAM IDs: 11, 15. + LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 3, // DRAM IDs: 17, 19, 24. + LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 4, // DRAM IDs: 18, 23, 28. + LPDDR4X_4GB_SAMSUNG_1Z = 5, // DRAM IDs: 20, 21, 22. + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF = 6, // DRAM IDs: 25, 26, 27. + LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 7, // DRAM IDs: 03, 05, 06. + + LPDDR4X_4GB_NEW0 = 8, // DRAM IDs: 29, 30, 31. + LPDDR4X_4GB_NEW1 = 9, // DRAM IDs: 32, 33, 34. }; void sdram_init(); diff --git a/bdk/mem/sdram_config_t210b01.inl b/bdk/mem/sdram_config_t210b01.inl index 6c996a3..7758301 100644 --- a/bdk/mem/sdram_config_t210b01.inl +++ b/bdk/mem/sdram_config_t210b01.inl @@ -708,82 +708,42 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = { #define DRAM_CC_LPDDR4X_AUTOCAL_VPR (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ) | \ DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \ - DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) | \ DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL) | \ DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL) | \ DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \ DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE) | \ + DRAM_CC(LPDDR4X_4GB_NEW0) | \ DRAM_CC(LPDDR4X_4GB_SAMSUNG_1Z)) + #define DRAM_CC_LPDDR4X_DYN_SELF_CTRL (DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \ - DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) | \ DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL) | \ DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \ DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE) | \ + DRAM_CC(LPDDR4X_4GB_NEW0) | \ DRAM_CC(LPDDR4X_4GB_SAMSUNG_1Z)) + #define DRAM_CC_LPDDR4X_QUSE_EINPUT (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ) | \ DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL) | \ DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL) | \ DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \ DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE) | \ + DRAM_CC(LPDDR4X_4GB_NEW0) | \ DRAM_CC(LPDDR4X_4GB_SAMSUNG_1Z)) + #define DRAM_CC_LPDDR4X_FAW (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL) | \ DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \ - DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)) + DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE) | \ + DRAM_CC(LPDDR4X_4GB_NEW1)) + #define DRAM_CC_LPDDR4X_VPR (DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE) | \ + DRAM_CC(LPDDR4X_4GB_NEW0) | \ DRAM_CC(LPDDR4X_4GB_SAMSUNG_1Z)) + #define DRAM_CC_LPDDR4X_SAMSUNG_8GB (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ) | \ DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL)) static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = { - // Samsung LPDDR4X 4GB X1X2 for prototype Iowa. - { 0x000E0022, 0x3AC / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dq_rank0_4. - { 0x001B0010, 0x3B0 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dq_rank0_5. - { 0x000E0022, 0x3C4 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dq_rank1_4. - { 0x001B0010, 0x3C8 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dq_rank1_5. - { 0x00490043, 0x3CC / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank0_0. - { 0x00420045, 0x3D0 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank0_1. - { 0x00490047, 0x3D4 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank0_2. - { 0x00460047, 0x3D8 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank0_3. - { 0x00000016, 0x3DC / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank0_4. - { 0x00100000, 0x3E0 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank0_5. - { 0x00490043, 0x3E4 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank1_0. - { 0x00420045, 0x3E8 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank1_1. - { 0x00490047, 0x3EC / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank1_2. - { 0x00460047, 0x3F0 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank1_3. - { 0x00000016, 0x3F4 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank1_4. - { 0x00100000, 0x3F8 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ob_ddll_long_dqs_rank1_5. - { 0x00220022, 0x41C / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ddll_long_cmd_0. - { 0x000E000E, 0x420 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ddll_long_cmd_1. - { 0x00100010, 0x424 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ddll_long_cmd_2. - { 0x001B001B, 0x428 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ddll_long_cmd_3. - { 0x00000022, 0x42C / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_X1X2) }, // emc_pmacro_ddll_long_cmd_4. - - // Samsung LPDDR4X 4GB (Y01) Die-? for Iowa. - { 0x32323232, 0x350 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ib_vref_dq_0. - { 0x32323232, 0x354 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ib_vref_dq_1. - { 0x000F0018, 0x3AC / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ob_ddll_long_dq_rank0_4. - { 0x000F0018, 0x3C4 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ob_ddll_long_dq_rank1_4. - { 0x00440048, 0x3CC / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ob_ddll_long_dqs_rank0_0. - { 0x00440045, 0x3D0 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ob_ddll_long_dqs_rank0_1. - { 0x00470047, 0x3D4 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ob_ddll_long_dqs_rank0_2. - { 0x0005000D, 0x3DC / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ob_ddll_long_dqs_rank0_4. - { 0x00440048, 0x3E4 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ob_ddll_long_dqs_rank1_0. - { 0x00440045, 0x3E8 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ob_ddll_long_dqs_rank1_1. - { 0x00470047, 0x3EC / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ob_ddll_long_dqs_rank1_2. - { 0x0005000D, 0x3F4 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ob_ddll_long_dqs_rank1_4. - { 0x00780078, 0x3FC / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ib_ddll_long_dqs_rank0_0. - { 0x00780078, 0x400 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ib_ddll_long_dqs_rank0_1. - { 0x00780078, 0x404 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ib_ddll_long_dqs_rank0_2. - { 0x00780078, 0x408 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ib_ddll_long_dqs_rank0_3. - { 0x00780078, 0x40C / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ib_ddll_long_dqs_rank1_0. - { 0x00780078, 0x410 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ib_ddll_long_dqs_rank1_1. - { 0x00780078, 0x414 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ib_ddll_long_dqs_rank1_2. - { 0x00780078, 0x418 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ib_ddll_long_dqs_rank1_3. - { 0x00180018, 0x41C / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ddll_long_cmd_0. - { 0x000F000F, 0x420 / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ddll_long_cmd_1. - { 0x00000018, 0x42C / 4, DRAM_CC(LPDDR4X_4GB_SAMSUNG_Y) }, // emc_pmacro_ddll_long_cmd_4. - // Samsung LPDDR4X 8GB K4UBE3D4AM-MGCJ Die-M for SDEV Iowa and Hoag. { 0x35353535, 0x350 / 4, DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ) }, // emc_pmacro_ib_vref_dq_0. { 0x35353535, 0x354 / 4, DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ) }, // emc_pmacro_ib_vref_dq_1. diff --git a/bdk/soc/fuse.c b/bdk/soc/fuse.c index da9063f..5b43d53 100644 --- a/bdk/soc/fuse.c +++ b/bdk/soc/fuse.c @@ -88,19 +88,26 @@ u32 fuse_read_odm_keygen_rev() u32 fuse_read_dramid(bool raw_id) { - u32 dramid = (fuse_read_odm(4) & 0xF8) >> 3; + bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210; + u32 odm4 = fuse_read_odm(4); + + u32 dramid = (odm4 & 0xF8) >> 3; + + // Get extended dram id info. + if (!tegra_t210) + dramid |= (odm4 & 0x7000) >> 7; if (raw_id) return dramid; - if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210) + if (tegra_t210) { if (dramid > 6) dramid = 0; } else { - if (dramid > 28) + if (dramid > 34) dramid = 8; }