From 2aa251c44f4e051d3fa1eb7c3741e8dd046ec48c Mon Sep 17 00:00:00 2001 From: CTCaer Date: Tue, 11 Oct 2022 03:53:17 +0300 Subject: [PATCH] bdk: max77812: uncomment RAM regulator --- bdk/power/max77620.h | 2 +- bdk/power/max7762x.c | 20 ++++++++++---------- bdk/power/max7762x.h | 26 +++++++++++++------------- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/bdk/power/max77620.h b/bdk/power/max77620.h index 03c9512..3d41459 100644 --- a/bdk/power/max77620.h +++ b/bdk/power/max77620.h @@ -318,7 +318,7 @@ #define MAX77620_REG_CID2 0x5A #define MAX77620_REG_CID3 0x5B #define MAX77620_REG_CID4 0x5C // OTP version. -#define MAX77620_REG_CID5 0x5D +#define MAX77620_REG_CID5 0x5D // ES version. #define MAX77620_CID_DIDO_MASK 0xF #define MAX77620_CID_DIDO_SHIFT 0 #define MAX77620_CID_DIDM_MASK 0xF0 diff --git a/bdk/power/max7762x.c b/bdk/power/max7762x.c index e69bb4c..fde39c7 100644 --- a/bdk/power/max7762x.c +++ b/bdk/power/max7762x.c @@ -88,11 +88,11 @@ static const max77620_regulator_t _pmic_regulators[] = { { "ldo7", 50000, 800000, 1050000, 1050000, REGULATOR_LDO, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO7, 1, 4, 3 }} }, { "ldo8", 50000, 800000, 1050000, 2800000, REGULATOR_LDO, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO8, 3, 7, 0 }} }, - { "max77621_CPU", 6250, 606250, 1000000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} }, - { "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} }, + { "max77621_CPU", 6250, 606250, 1000000, 1400000, REGULATOR_BC0, MAX77621_REG_VOUT, MAX77621_REG_VOUT_DVS, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} }, + { "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_REG_VOUT, MAX77621_REG_VOUT_DVS, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} }, { "max77812_CPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} }, + { "max77812_RAM", 5000, 250000, 600000, 650000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration. //{ "max77812_GPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} }, - //{ "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration. }; static u8 _max77812_get_address() @@ -175,20 +175,20 @@ int max77620_regulator_config_fps(u32 id) return 1; } -int max7762x_regulator_set_voltage(u32 id, u32 mv) +int max7762x_regulator_set_voltage(u32 id, u32 uv) { if (id > REGULATOR_MAX) return 0; const max77620_regulator_t *reg = &_pmic_regulators[id]; - if (mv < reg->uv_min || mv > reg->uv_max) + if (uv < reg->uv_min || uv > reg->uv_max) return 0; u8 addr = _max7762x_get_i2c_address(id); // Calculate voltage multiplier. - u32 mult = (mv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step; + u32 mult = (uv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step; u8 val = i2c_recv_byte(I2C_5, addr, reg->volt_addr); val = (val & ~reg->volt_mask) | (mult & reg->volt_mask); @@ -299,13 +299,13 @@ void max77621_config_default(u32 id, bool por) max7762x_regulator_enable(id, false); // Configure to default. - i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_por); - i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_por); + i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL1, reg->ctrl.ctrl1_por); + i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL2, reg->ctrl.ctrl2_por); } else { - i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_hos); - i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_hos); + i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL1, reg->ctrl.ctrl1_hos); + i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL2, reg->ctrl.ctrl2_hos); } } diff --git a/bdk/power/max7762x.h b/bdk/power/max7762x.h index 379b946..6e6735b 100644 --- a/bdk/power/max7762x.h +++ b/bdk/power/max7762x.h @@ -66,22 +66,22 @@ #define REGULATOR_LDO6 10 #define REGULATOR_LDO7 11 #define REGULATOR_LDO8 12 -#define REGULATOR_CPU0 13 -#define REGULATOR_GPU0 14 -#define REGULATOR_CPU1 15 -//#define REGULATOR_GPU1 16 -//#define REGULATOR_GPU1 17 -#define REGULATOR_MAX 15 +#define REGULATOR_CPU0 13 // T210 CPU. +#define REGULATOR_GPU0 14 // T210 CPU. +#define REGULATOR_CPU1 15 // T210B01 CPU. +#define REGULATOR_RAM1 16 // T210B01 RAM for PHASE211. +//#define REGULATOR_GPU1 17 // T210B01 CPU. +#define REGULATOR_MAX REGULATOR_RAM1 #define MAX77621_CPU_I2C_ADDR 0x1B #define MAX77621_GPU_I2C_ADDR 0x1C -#define MAX77621_VOUT_REG 0x00 -#define MAX77621_VOUT_DVS_REG 0x01 -#define MAX77621_CONTROL1_REG 0x02 -#define MAX77621_CONTROL2_REG 0x03 -#define MAX77621_CHIPID1_REG 0x04 -#define MAX77621_CHIPID2_REG 0x05 +#define MAX77621_REG_VOUT 0x00 +#define MAX77621_REG_VOUT_DVS 0x01 +#define MAX77621_REG_CONTROL1 0x02 +#define MAX77621_REG_CONTROL2 0x03 +#define MAX77621_REG_CHIPID1 0x04 +#define MAX77621_REG_CHIPID2 0x05 /* MAX77621_VOUT_DVC_DVS */ #define MAX77621_DVC_DVS_VOLT_MASK 0x7F @@ -145,7 +145,7 @@ int max77620_regulator_get_status(u32 id); int max77620_regulator_config_fps(u32 id); -int max7762x_regulator_set_voltage(u32 id, u32 mv); +int max7762x_regulator_set_voltage(u32 id, u32 uv); int max7762x_regulator_enable(u32 id, bool enable); void max77620_config_gpio(u32 id, bool enable); void max77620_config_default();