From 24795891ecbde45263cb24f84036a5f314329b6e Mon Sep 17 00:00:00 2001 From: CTCaer Date: Mon, 19 Dec 2022 04:31:54 +0200 Subject: [PATCH] loader: refactor --- loader/Makefile | 2 +- loader/link.ld | 8 ++++++++ loader/loader.c | 39 ++++++++++++++++++++------------------- 3 files changed, 29 insertions(+), 20 deletions(-) diff --git a/loader/Makefile b/loader/Makefile index d59ed08..522ddee 100644 --- a/loader/Makefile +++ b/loader/Makefile @@ -30,7 +30,7 @@ CUSTOMDEFINES := -DBL_MAGIC=$(IPL_MAGIC) CUSTOMDEFINES += -DBL_VER_MJ=$(BLVERSION_MAJOR) -DBL_VER_MN=$(BLVERSION_MINOR) -DBL_VER_HF=$(BLVERSION_HOTFX) -DBL_RESERVED=$(BLVERSION_RSVD) #TODO: Considering reinstating some of these when pointer warnings have been fixed. -WARNINGS := -Wall -Wno-array-bounds -Wno-stringop-overflow +WARNINGS := -Wall -Wsign-compare -Wno-array-bounds -Wno-stringop-overflow ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork CFLAGS = $(ARCH) -O2 -g -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 $(WARNINGS) $(CUSTOMDEFINES) diff --git a/loader/link.ld b/loader/link.ld index b217fd3..81e1085 100644 --- a/loader/link.ld +++ b/loader/link.ld @@ -15,6 +15,14 @@ SECTIONS { *(.rodata*); *(._payload_00); *(._payload_01); + + /* + * To mitigate bad injectors/chainloaders, + * miss-align binary size to account for version info. + * !If version text is not appended, then use ". = ALIGN(4)"! + */ + data_end_ua = .; + . = ((data_end_ua + 0x6 + 4 - 1) & ~(4 - 1)) - 6; } __ldr_end = .; . = ALIGN(0x10); diff --git a/loader/loader.c b/loader/loader.c index fc1a1f7..7cff34e 100644 --- a/loader/loader.c +++ b/loader/loader.c @@ -60,39 +60,40 @@ const volatile char __attribute__((section ("._octopus"))) octopus[] = void loader_main() { // Preliminary BPMP clocks init. - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set SCLK div to 1. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set clk source to Run and PLLP_OUT2 (204MHz). + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set SCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set clk source to Run and PLLP_OUT2 (204MHz). CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1. - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz). + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz). - // Get Loader and Payload size. - u32 payload_size = sizeof(payload_00) + sizeof(payload_01); // Actual payload size. - payload_size += (u32)payload_01 - (u32)payload_00 - sizeof(payload_00); // Add array alignment. + // Get Payload size. + u32 payload_size = sizeof(payload_00) + sizeof(payload_01); // Actual payload size. + payload_size += (u32)payload_01 - (u32)payload_00 - sizeof(payload_00); // Add compiler alignment. + payload_size = ALIGN(payload_size, 4); // Align size to 4 bytes. u32 *payload_addr = (u32 *)payload_00; // Relocate payload to a safer place. - u32 bytes = ALIGN(payload_size, 4) >> 2; - u32 *addr = payload_addr + bytes - 1; - u32 *dst = (u32 *)(IPL_RELOC_TOP - 4); - while (bytes) + u32 words = payload_size >> 2; + u32 *src = payload_addr + words - 1; + u32 *dst = (u32 *)(IPL_RELOC_TOP - 4); + while (words) { - *dst = *addr; + *dst = *src; + src--; dst--; - addr--; - bytes--; + words--; } // Set source address of the first part. - u8 *src_addr = (void *)(IPL_RELOC_TOP - ALIGN(payload_size, 4)); + u8 *src_addr = (void *)(IPL_RELOC_TOP - payload_size); // Uncompress first part. - u32 dst_pos = LZ_Uncompress((const u8 *)src_addr, (u8*)IPL_LOAD_ADDR, sizeof(payload_00)); + u32 dst_pos = LZ_Uncompress((const u8 *)src_addr, (u8 *)IPL_LOAD_ADDR, sizeof(payload_00)); - // Set source address of the second part. Includes array alignment. + // Set source address of the second part. Includes compiler alignment. src_addr += (u32)payload_01 - (u32)payload_00; // Uncompress second part. - LZ_Uncompress((const u8 *)src_addr, (u8*)IPL_LOAD_ADDR + dst_pos, sizeof(payload_01)); + LZ_Uncompress((const u8 *)src_addr, (u8 *)IPL_LOAD_ADDR + dst_pos, sizeof(payload_01)); // Copy over boot configuration storage. memcpy((u8 *)(IPL_LOAD_ADDR + IPL_PATCHED_RELOC_SZ), &b_cfg, sizeof(boot_cfg_t));