From 20e661fc0190fce2cc73cec08891e0b97f0c845b Mon Sep 17 00:00:00 2001 From: CTCaer Date: Wed, 13 Mar 2024 01:50:45 +0200 Subject: [PATCH] bdk: refactor flow control defines --- bdk/soc/bpmp.c | 10 ++++---- bdk/soc/t210.h | 64 ++++++++++++++++++++++++++++++++------------------ 2 files changed, 46 insertions(+), 28 deletions(-) diff --git a/bdk/soc/bpmp.c b/bdk/soc/bpmp.c index 5a33f4b..669dcc2 100644 --- a/bdk/soc/bpmp.c +++ b/bdk/soc/bpmp.c @@ -287,10 +287,10 @@ void bpmp_usleep(u32 us) // Each iteration takes 1us. while (us) { - delay = (us > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : us; + delay = (us > HALT_MAX_CNT) ? HALT_MAX_CNT : us; us -= delay; - FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_USEC | delay; + FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_WAITEVENT | HALT_USEC | delay; } } @@ -301,14 +301,14 @@ void bpmp_msleep(u32 ms) // Iteration time is variable. ~200 - 1000us. while (ms) { - delay = (ms > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : ms; + delay = (ms > HALT_MAX_CNT) ? HALT_MAX_CNT : ms; ms -= delay; - FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_MSEC | delay; + FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_WAITEVENT | HALT_MSEC | delay; } } void bpmp_halt() { - FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_JTAG; + FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_WAITEVENT | HALT_JTAG; } diff --git a/bdk/soc/t210.h b/bdk/soc/t210.h index 97819a6..37bebae 100644 --- a/bdk/soc/t210.h +++ b/bdk/soc/t210.h @@ -308,29 +308,47 @@ #define EMC_HEKA_UPD BIT(30) /*! Flow controller registers. */ -#define FLOW_CTLR_HALT_COP_EVENTS 0x4 -#define HALT_COP_GIC_IRQ BIT(9) -#define HALT_COP_LIC_IRQ BIT(11) -#define HALT_COP_SEC BIT(23) -#define HALT_COP_MSEC BIT(24) -#define HALT_COP_USEC BIT(25) -#define HALT_COP_JTAG BIT(28) -#define HALT_COP_WAIT_EVENT BIT(30) -#define HALT_COP_STOP_UNTIL_IRQ BIT(31) -#define HALT_COP_MAX_CNT 0xFF -#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0 -#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14 -#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C -#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24 -#define FLOW_CTLR_CPU0_CSR 0x8 -#define FLOW_CTLR_CPU1_CSR 0x18 -#define FLOW_CTLR_CPU2_CSR 0x20 -#define FLOW_CTLR_CPU3_CSR 0x28 -#define FLOW_CTLR_RAM_REPAIR 0x40 -#define RAM_REPAIR_REQ BIT(0) -#define RAM_REPAIR_STS BIT(1) -#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98 -#define CLUSTER_CTRL_ACTIVE_SLOW BIT(0) +#define FLOW_CTLR_HALT_COP_EVENTS 0x4 +#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0 +#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14 +#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C +#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24 +#define HALT_GIC_IRQ BIT(9) +#define HALT_LIC_IRQ BIT(11) +#define HALT_SEC BIT(23) +#define HALT_MSEC BIT(24) +#define HALT_USEC BIT(25) +#define HALT_JTAG BIT(28) +#define HALT_MODE_NONE (0 << 29u) +#define HALT_MODE_RUN_AND_INT (1 << 29u) +#define HALT_MODE_WAITEVENT (2 << 29u) +#define HALT_MODE_WAITEVENT_AND_INT (3 << 29u) +#define HALT_MODE_STOP_UNTIL_IRQ (4 << 29u) +#define HALT_MODE_STOP_UNTIL_IRQ_AND_INT (5 << 29u) +#define HALT_MODE_STOP_UNTIL_EVENT_AND_IRQ (6 << 29u) +#define HALT_MAX_CNT 0xFF +#define FLOW_CTLR_COP_CSR 0xC +#define FLOW_CTLR_CPU0_CSR 0x8 +#define FLOW_CTLR_CPU1_CSR 0x18 +#define FLOW_CTLR_CPU2_CSR 0x20 +#define FLOW_CTLR_CPU3_CSR 0x28 +#define CSR_ENABLE BIT(0) +#define CSR_WAIT_WFI_NONE (0 << 8u) +#define CSR_WAIT_WFI_CPU0 (BIT(0) << 8u) +#define CSR_ENABLE_EXT_CPU_ONLY (0 << 12u) +#define CSR_ENABLE_EXT_CPU_NCPU (1 << 12u) +#define CSR_ENABLE_EXT_CPU_RAIL (2 << 12u) +#define CSR_EVENT_FLAG BIT(14) +#define CSR_INTR_FLAG BIT(15) +#define CSR_HALT BIT(22) +#define FLOW_CTLR_CPU_PWR_CSR 0x38 +#define CPU_PWR_RAIL_STS_MASK (3 << 1u) +#define CPU_PWR_RAIL_OFF 0 +#define FLOW_CTLR_RAM_REPAIR 0x40 +#define RAM_REPAIR_REQ BIT(0) +#define RAM_REPAIR_STS BIT(1) +#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98 +#define CLUSTER_CTRL_ACTIVE_SLOW BIT(0) /* MSelect registers */ #define MSELECT_CONFIG 0x00