From 20c4d6dba671868a4faa0dbfb7211c9fe566cfda Mon Sep 17 00:00:00 2001 From: CTCaer Date: Thu, 20 Jan 2022 13:22:39 +0200 Subject: [PATCH] minerva: update copyright years --- modules/hekate_libsys_minerva/mtc.h | 2 +- modules/hekate_libsys_minerva/sys_sdrammtc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/modules/hekate_libsys_minerva/mtc.h b/modules/hekate_libsys_minerva/mtc.h index a88321b..2dc5bd8 100644 --- a/modules/hekate_libsys_minerva/mtc.h +++ b/modules/hekate_libsys_minerva/mtc.h @@ -2,7 +2,7 @@ * Minerva Training Cell * DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4. * - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/modules/hekate_libsys_minerva/sys_sdrammtc.c b/modules/hekate_libsys_minerva/sys_sdrammtc.c index 8d96fec..774b2ff 100644 --- a/modules/hekate_libsys_minerva/sys_sdrammtc.c +++ b/modules/hekate_libsys_minerva/sys_sdrammtc.c @@ -2,7 +2,7 @@ * Minerva Training Cell * DRAM Training for Tegra X1 SoC. Supports LPDDR4. * - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License,